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[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [ml605/] [UDP_integration_example.vhd] - Blame information for rev 6

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1 2 pjf
----------------------------------------------------------------------------------
2
-- Company: 
3
-- Engineer: 
4
-- 
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-- Create Date:    11:01:00 06/11/2011 
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-- Design Name: 
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-- Module Name:    UDP_integration_example - Behavioral 
8
-- Project Name: 
9
-- Target Devices: 
10
-- Tool versions: 
11
-- Description: 
12
--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
19
----------------------------------------------------------------------------------
20
library IEEE;
21
use IEEE.STD_LOGIC_1164.ALL;
22
use IEEE.NUMERIC_STD.ALL;
23
use work.axi.all;
24
use work.ipv4_types.all;
25
use work.arp_types.all;
26
 
27
entity UDP_integration_example is
28
    port (
29
                -- System signals
30
                ------------------
31
      reset                             : in  std_logic;                                        -- asynchronous reset
32
      clk_in_p                                  : in  std_logic;                                        -- 200MHz clock input from board
33
      clk_in_n                                  : in  std_logic;
34
 
35
                -- System controls
36
                ------------------
37
                PBTX                                                                    : in std_logic;
38
                UDP_RX                                                          : out std_logic;
39
                UDP_Start                                                       : out std_logic;
40
                PBTX_LED                                                                : out std_logic;
41
                TX_Started                                                      : out std_logic;
42
                TX_Completed                                            : out std_logic;
43
                reset_leds                                                      : in std_logic;
44
      display                           : out std_logic_vector(7 downto 0);
45
 
46
      -- GMII Interface
47
      -----------------     
48
      phy_resetn                                : out std_logic;
49
      gmii_txd                      : out std_logic_vector(7 downto 0);
50
      gmii_tx_en                    : out std_logic;
51
      gmii_tx_er                    : out std_logic;
52
      gmii_tx_clk                   : out std_logic;
53
      gmii_rxd                      : in  std_logic_vector(7 downto 0);
54
      gmii_rx_dv                    : in  std_logic;
55
      gmii_rx_er                    : in  std_logic;
56
      gmii_rx_clk                   : in  std_logic;
57
      gmii_col                      : in  std_logic;
58
      gmii_crs                      : in  std_logic;
59
      mii_tx_clk                    : in  std_logic
60
    );
61
end UDP_integration_example;
62
 
63
architecture Behavioral of UDP_integration_example is
64
 
65
  ------------------------------------------------------------------------------
66
  -- Component Declaration for the complete IP layer
67
  ------------------------------------------------------------------------------
68
component UDP_Complete
69
    Port (
70
                        -- UDP TX signals
71
                        udp_tx_start                    : in std_logic;                                                 -- indicates req to tx UDP
72
                        udp_txi                                 : in udp_tx_type;                                                       -- UDP tx cxns
73
                        udp_tx_result                   : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
74
                        udp_tx_data_out_ready: out std_logic;                                                   -- indicates udp_tx is ready to take data
75
                        -- UDP RX signals
76
                        udp_rx_start                    : out std_logic;                                                        -- indicates receipt of udp header
77
                        udp_rxo                                 : out udp_rx_type;
78
                        -- IP RX signals
79
                        ip_rx_hdr                               : out ipv4_rx_header_type;
80
                        -- system signals
81
                        clk_in_p             : in  std_logic;                                           -- 200MHz clock input from board
82
                        clk_in_n             : in  std_logic;
83
                        clk_out                                 : out std_logic;
84
                        reset                                   : in  STD_LOGIC;
85
                        our_ip_address          : in STD_LOGIC_VECTOR (31 downto 0);
86
                        our_mac_address                 : in std_logic_vector (47 downto 0);
87
                        -- status signals
88
                        arp_pkt_count                   : out STD_LOGIC_VECTOR(7 downto 0);                      -- count of arp pkts received
89
                        ip_pkt_count                    : out STD_LOGIC_VECTOR(7 downto 0);                      -- number of IP pkts received for us
90
                        -- GMII Interface
91
                        phy_resetn           : out std_logic;
92
                        gmii_txd             : out std_logic_vector(7 downto 0);
93
                        gmii_tx_en           : out std_logic;
94
                        gmii_tx_er           : out std_logic;
95
                        gmii_tx_clk          : out std_logic;
96
                        gmii_rxd             : in  std_logic_vector(7 downto 0);
97
                        gmii_rx_dv           : in  std_logic;
98
                        gmii_rx_er           : in  std_logic;
99
                        gmii_rx_clk          : in  std_logic;
100
                        gmii_col             : in  std_logic;
101
                        gmii_crs             : in  std_logic;
102
                        mii_tx_clk           : in  std_logic
103
                        );
104
end component;
105
 
106
 
107
        type state_type is (IDLE, DATA_OUT);
108
        type count_mode_type is (RST, INCR, HOLD);
109
        type set_clr_type is (SET, CLR, HOLD);
110
 
111
        -- system signals
112
        signal clk_int                                                  : std_logic;
113
        signal our_mac                                          : STD_LOGIC_VECTOR (47 downto 0);
114
        signal our_ip                                                   : STD_LOGIC_VECTOR (31 downto 0);
115
        signal udp_tx_int                                               : udp_tx_type;
116
        signal udp_tx_result_int                        : std_logic_vector (1 downto 0);
117
        signal udp_tx_data_out_ready_int        : std_logic;
118
        signal udp_rx_int                                               : udp_rx_type;
119
        signal udp_tx_start_int                         : std_logic;
120
        signal udp_rx_start_int                         : std_logic;
121
        signal arp_pkt_count_int                        : STD_LOGIC_VECTOR(7 downto 0);
122
        signal ip_pkt_count_int                         : STD_LOGIC_VECTOR(7 downto 0);
123
        signal ip_rx_hdr_int                                    : ipv4_rx_header_type;
124
 
125
        -- state signals
126
        signal state                                                    : state_type;
127
        signal count                                                    : unsigned (7 downto 0);
128
        signal tx_hdr                                                   : udp_tx_header_type;
129
        signal tx_start_reg                                     : std_logic;
130
        signal tx_started_reg                           : std_logic;
131
        signal tx_fin_reg                                               : std_logic;
132
        signal udp_rx_start_reg                         : std_logic;
133
 
134
        -- control signals
135
        signal next_state                                               : state_type;
136
        signal set_state                                                : std_logic;
137
        signal set_count                                                : count_mode_type;
138
        signal set_hdr                                                  : std_logic;
139
        signal set_tx_start                                     : set_clr_type;
140
        signal set_last                                         : std_logic;
141
        signal set_tx_started                           : set_clr_type;
142
        signal set_tx_fin                                               : set_clr_type;
143
        signal set_udp_rx_start_reg             : set_clr_type;
144 6 pjf
        signal first_byte_rx                                    : STD_LOGIC_VECTOR(7 downto 0);
145 2 pjf
 
146
begin
147
 
148
        process (
149
                our_ip, our_mac, udp_rx_int, udp_tx_start_int, udp_rx_start_int, ip_rx_hdr_int, udp_rx_start_reg,
150
                udp_tx_int, count, clk_int, ip_pkt_count_int, arp_pkt_count_int,
151
                reset, tx_started_reg, tx_fin_reg, tx_start_reg
152
                )
153
        begin
154
                -- set up our local addresses
155
                our_ip  <= x"c0a80509";         -- 192.168.5.9
156
                our_mac         <= x"002320212223";
157
 
158
                -- determine RX good and error LEDs
159
                if udp_rx_int.hdr.is_valid = '1' then
160
                        UDP_RX <= '1';
161
                else
162
                        UDP_RX <= '0';
163
                end if;
164
 
165
                UDP_Start <= udp_rx_start_reg;
166
                TX_Started <= tx_start_reg; --tx_started_reg;
167
                TX_Completed <= tx_fin_reg;
168
 
169
                -- set display leds to show IP pkt rx count on 7..4 and arp rx count on 3..0
170
                display (7 downto 4) <= ip_pkt_count_int (3 downto 0);
171
                display (3 downto 0) <= arp_pkt_count_int (3 downto 0);
172
 
173
        end process;
174
 
175 6 pjf
        -- AUTO TX process - on receipt of any UDP pkt, send a response,
176 2 pjf
 
177
        -- TX response process - COMB
178
   tx_proc_combinatorial: process(
179
                -- inputs
180 6 pjf
                udp_rx_start_int, udp_tx_data_out_ready_int, udp_tx_int.data.data_out_valid,
181
                udp_rx_int, PBTX, reset_leds,
182 2 pjf
                -- state
183
                state, count, tx_hdr, tx_start_reg, tx_started_reg, tx_fin_reg, udp_rx_start_reg,
184
                -- controls
185
                next_state, set_state, set_count, set_hdr, set_tx_start, set_last,
186 6 pjf
                set_tx_started, set_tx_fin, set_udp_rx_start_reg, first_byte_rx
187 2 pjf
                )
188
   begin
189
                -- set output_followers
190
                udp_tx_int.hdr <= tx_hdr;
191
                udp_tx_int.data.data_out_last <= set_last;
192
                udp_tx_start_int <= tx_start_reg;
193
 
194
                -- set control signal defaults
195
                next_state <= IDLE;
196
                set_state <= '0';
197
                set_count <= HOLD;
198
                set_hdr <= '0';
199
                set_tx_start <= HOLD;
200
                set_last <= '0';
201
                set_tx_started <= HOLD;
202
                set_tx_fin <= HOLD;
203
                set_udp_rx_start_reg <= HOLD;
204 6 pjf
                first_byte_rx <= (others => '0');
205 2 pjf
 
206
                -- FSM
207
                case state is
208
 
209
                        when IDLE =>
210
                                udp_tx_int.data.data_out <= (others => '0');
211
                                udp_tx_int.data.data_out_valid <= '0';
212
                                if udp_rx_start_int = '1' or PBTX = '1' then
213 6 pjf
                                        if udp_rx_start_int = '1' then
214
                                                first_byte_rx <= udp_rx_int.data.data_in;
215
                                        else
216
                                                first_byte_rx <= x"00";
217
                                        end if;
218 2 pjf
                                        set_udp_rx_start_reg <= SET;
219
                                        set_tx_started <= SET;
220
                                        set_hdr <= '1';
221
                                        set_tx_start <= SET;
222
                                        set_tx_fin <= CLR;
223
                                        set_count <= RST;
224
                                        next_state <= DATA_OUT;
225
                                        set_state <= '1';
226
                                elsif reset_leds = '1' then
227
                                        set_udp_rx_start_reg <= CLR;
228
                                        set_tx_started <= CLR;
229
                                        set_tx_fin <= CLR;
230
                                end if;
231
 
232
                        when DATA_OUT =>
233
                                udp_tx_int.data.data_out <= std_logic_vector(count) or x"40";
234
                                udp_tx_int.data.data_out_valid <= udp_tx_data_out_ready_int;
235
                                if udp_tx_data_out_ready_int = '1' then
236
                                        set_tx_start <= CLR;
237
                                        if unsigned(count) = x"03" then
238
                                                set_last <= '1';
239
                                                set_tx_fin <= SET;
240
                                                set_tx_started <= CLR;
241
                                                next_state <= IDLE;
242
                                                set_state <= '1';
243
                                        else
244
                                                set_count <= INCR;
245
                                        end if;
246
                                end if;
247
 
248
                end case;
249
        end process;
250
 
251
 
252
 
253
   -- TX response process - SEQ
254
   tx_proc_sequential: process(clk_int)
255
   begin
256
                if rising_edge(clk_int) then
257
                        if reset = '1' then
258
                                -- reset state variables
259
                                state <= IDLE;
260
                                count <= x"00";
261
                                tx_start_reg <= '0';
262
                                tx_hdr.dst_ip_addr <= (others => '0');
263
                                tx_hdr.dst_port <= (others => '0');
264
                                tx_hdr.src_port <= (others => '0');
265
                                tx_hdr.data_length <= (others => '0');
266
                                tx_hdr.checksum <= (others => '0');
267
                                tx_started_reg <= '0';
268
                                tx_fin_reg <= '0';
269
                                PBTX_LED <= '0';
270
                        else
271
                                PBTX_LED <= PBTX;
272
 
273
                                -- Next rx_state processing
274
                                if set_state = '1' then
275
                                        state <= next_state;
276
                                else
277
                                        state <= state;
278
                                end if;
279
 
280
                                -- count processing
281
                                case set_count is
282
                                        when RST =>             count <= x"00";
283
                                        when INCR =>            count <= count + 1;
284
                                        when HOLD =>            count <= count;
285
                                end case;
286
 
287
                                -- set tx hdr
288
                                if set_hdr = '1' then
289 6 pjf
                                        -- if the first byte of the rx pkt is 'B' then send to broadcast, otherwise send to reply IP
290
                                        if first_byte_rx = x"42" then
291
                                                tx_hdr.dst_ip_addr <= IP_BC_ADDR;
292
                                        else
293
                                                tx_hdr.dst_ip_addr <= udp_rx_int.hdr.src_ip_addr;
294
                                        end if;
295 2 pjf
                                        tx_hdr.dst_port <= udp_rx_int.hdr.src_port;
296
                                        tx_hdr.src_port <= udp_rx_int.hdr.dst_port;
297
                                        tx_hdr.data_length <= x"0004";
298
                                        tx_hdr.checksum <= x"0000";
299
                                else
300
                                        tx_hdr <= tx_hdr;
301
                                end if;
302
 
303
                                -- set tx start signal
304
                                case set_tx_start is
305
                                        when SET  => tx_start_reg <= '1';
306
                                        when CLR  => tx_start_reg <= '0';
307
                                        when HOLD => tx_start_reg <= tx_start_reg;
308
                                end case;
309
 
310
                                -- set tx started signal
311
                                case set_tx_started is
312
                                        when SET  => tx_started_reg <= '1';
313
                                        when CLR  => tx_started_reg <= '0';
314
                                        when HOLD => tx_started_reg <= tx_started_reg;
315
                                end case;
316
 
317
                                -- set tx finished signal
318
                                case set_tx_fin is
319
                                        when SET  => tx_fin_reg <= '1';
320
                                        when CLR  => tx_fin_reg <= '0';
321
                                        when HOLD => tx_fin_reg <= tx_fin_reg;
322
                                end case;
323
 
324
                                -- set UDP START signal
325
                                case set_udp_rx_start_reg is
326
                                        when SET  => udp_rx_start_reg <= '1';
327
                                        when CLR  => udp_rx_start_reg <= '0';
328
                                        when HOLD => udp_rx_start_reg <= udp_rx_start_reg;
329
                                end case;
330
 
331
 
332
                        end if;
333
                end if;
334
 
335
        end process;
336
 
337
 
338
   ------------------------------------------------------------------------------
339
   -- Instantiate the UDP layer
340
   ------------------------------------------------------------------------------
341
    UDP_block : UDP_Complete PORT MAP
342
                (
343
                                -- UDP interface
344
                                udp_tx_start                    => udp_tx_start_int,
345
                                udp_txi                                         => udp_tx_int,
346
                                udp_tx_result                   => udp_tx_result_int,
347
                                udp_tx_data_out_ready=> udp_tx_data_out_ready_int,
348
                                udp_rx_start                    => udp_rx_start_int,
349
                                udp_rxo                                         => udp_rx_int,
350
                                -- IP RX signals
351
                                ip_rx_hdr                               => ip_rx_hdr_int,
352
                                -- System interface
353
                                clk_in_p             => clk_in_p,
354
                                clk_in_n             => clk_in_n,
355
                                clk_out                                 => clk_int,
356
                                reset                                   => reset,
357
                                our_ip_address          => our_ip,
358
                                our_mac_address                 => our_mac,
359
                                -- status signals
360
                                arp_pkt_count                   => arp_pkt_count_int,
361
                                ip_pkt_count                    => ip_pkt_count_int,
362
                                -- GMII Interface
363
                                -----------------     
364
                                phy_resetn        => phy_resetn,
365
                                gmii_txd                => gmii_txd,
366
                                gmii_tx_en        => gmii_tx_en,
367
                                gmii_tx_er        => gmii_tx_er,
368
                                gmii_tx_clk       => gmii_tx_clk,
369
                                gmii_rxd                => gmii_rxd,
370
                                gmii_rx_dv        => gmii_rx_dv,
371
                                gmii_rx_er        => gmii_rx_er,
372
                                gmii_rx_clk       => gmii_rx_clk,
373
                                gmii_col        => gmii_col,
374
                                gmii_crs                => gmii_crs,
375
                                mii_tx_clk        => mii_tx_clk
376
        );
377
 
378
 
379
end Behavioral;
380
 

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