URL https://opencores.org/ocsvn/udp_ip_stack/udp_ip_stack/trunk

Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [tx_arbitrator.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log


----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:03:30 06/04/2011 
-- Design Name: 
-- Module Name:    tx_arbitrator - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description:         arbitrate between two sources that want to transmit onto a bus
--                                              handles arbitration and multiplexing
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity tx_arbitrator is
    port (
                clk                             : in std_logic;
                reset                           : in std_logic;
 
                req_1                           : in  std_logic;
                grant_1                 : out std_logic;
      data_1         : in  std_logic_vector(7 downto 0); -- data byte to tx
      valid_1        : in  std_logic;                                                   -- tdata is valid
      last_1         : in  std_logic;                                                   -- indicates last byte of frame
 
                req_2                           : in  std_logic;
                grant_2                 : out std_logic;
      data_2         : in  std_logic_vector(7 downto 0); -- data byte to tx
      valid_2        : in  std_logic;                                                   -- tdata is valid
      last_2         : in  std_logic;                                                   -- indicates last byte of frame
 
      data              : out  std_logic_vector(7 downto 0);     -- data byte to tx
      valid             : out  std_logic;                                                       -- tdata is valid
      last              : out  std_logic                                                        -- indicates last byte of frame
    );
end tx_arbitrator;
 
architecture Behavioral of tx_arbitrator is
 
        type grant_type is (M1,M2);
 
        signal grant :  grant_type;
 
begin
        combinatorial : process (
                grant,
                data_1, valid_1, last_1,
                data_2, valid_2, last_2
                )
        begin
                -- grant outputs
                case grant is
                        when M1 =>
                                grant_1 <= '1';
                                grant_2 <= '0';
                        when M2 =>
                                grant_1 <= '0';
                                grant_2 <= '1';
                end case;
 
                -- multiplexer
                if grant = M1 then
                        data <= data_1;
                        valid <= valid_1;
                        last <= last_1;
                else
                        data <= data_2;
                        valid <= valid_2;
                        last <= last_2;
                end if;
        end process;
 
        sequential : process (clk, reset, req_1, req_2, grant)
        begin
                if rising_edge(clk) then
                        if reset = '1' then
                                grant <= M1;
                        else
                                case grant is
                                        when M1 =>
                                                if req_1 = '1' then
                                                        grant <= M1;
                                                elsif req_2 = '1' then
                                                        grant <= M2;
                                                end if;
                                        when M2 =>
                                                if req_2 = '1' then
                                                        grant <= M2;
                                                else
                                                        grant <= M1;
                                                end if;
                                end case;
                        end if;
                end if;
        end process;
 
 
end Behavioral;
 

Line No.	Rev	Author	Line
1	2	pjf	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer:`
4			`--`
5			`-- Create Date: 08:03:30 06/04/2011`
6			`-- Design Name:`
7			`-- Module Name: tx_arbitrator - Behavioral`
8			`-- Project Name:`
9			`-- Target Devices:`
10			`-- Tool versions:`
11			`-- Description: arbitrate between two sources that want to transmit onto a bus`
12			`-- handles arbitration and multiplexing`
13			`--`
14			`-- Dependencies:`
15			`--`
16			`-- Revision:`
17			`-- Revision 0.01 - File Created`
18			`-- Revision 0.02 - Made sticky on port M1 to optimise access on this port and allow immediate grant`
19			`-- Additional Comments:`
20			`--`
21			`----------------------------------------------------------------------------------`
22			`library IEEE;`
23			`use IEEE.STD_LOGIC_1164.ALL;`
24
25
26			`entity tx_arbitrator is`
27			`port (`
28			`clk : in std_logic;`
29			`reset : in std_logic;`
30
31			`req_1 : in std_logic;`
32			`grant_1 : out std_logic;`
33			`data_1 : in std_logic_vector(7 downto 0); -- data byte to tx`
34			`valid_1 : in std_logic; -- tdata is valid`
35			`last_1 : in std_logic; -- indicates last byte of frame`
36
37			`req_2 : in std_logic;`
38			`grant_2 : out std_logic;`
39			`data_2 : in std_logic_vector(7 downto 0); -- data byte to tx`
40			`valid_2 : in std_logic; -- tdata is valid`
41			`last_2 : in std_logic; -- indicates last byte of frame`
42
43			`data : out std_logic_vector(7 downto 0); -- data byte to tx`
44			`valid : out std_logic; -- tdata is valid`
45			`last : out std_logic -- indicates last byte of frame`
46			`);`
47			`end tx_arbitrator;`
48
49			`architecture Behavioral of tx_arbitrator is`
50
51			`type grant_type is (M1,M2);`
52
53			`signal grant : grant_type;`
54
55			`begin`
56			`combinatorial : process (`
57			`grant,`
58			`data_1, valid_1, last_1,`
59			`data_2, valid_2, last_2`
60			`)`
61			`begin`
62			`-- grant outputs`
63			`case grant is`
64			`when M1 =>`
65			`grant_1 <= '1';`
66			`grant_2 <= '0';`
67			`when M2 =>`
68			`grant_1 <= '0';`
69			`grant_2 <= '1';`
70			`end case;`
71
72			`-- multiplexer`
73			`if grant = M1 then`
74			`data <= data_1;`
75			`valid <= valid_1;`
76			`last <= last_1;`
77			`else`
78			`data <= data_2;`
79			`valid <= valid_2;`
80			`last <= last_2;`
81			`end if;`
82			`end process;`
83
84			`sequential : process (clk, reset, req_1, req_2, grant)`
85			`begin`
86			`if rising_edge(clk) then`
87			`if reset = '1' then`
88			`grant <= M1;`
89			`else`
90			`case grant is`
91			`when M1 =>`
92			`if req_1 = '1' then`
93			`grant <= M1;`
94			`elsif req_2 = '1' then`
95			`grant <= M2;`
96			`end if;`
97			`when M2 =>`
98			`if req_2 = '1' then`
99			`grant <= M2;`
100			`else`
101			`grant <= M1;`
102			`end if;`
103			`end case;`
104			`end if;`
105			`end if;`
106			`end process;`
107
108
109			`end Behavioral;`
110

Browse

Tools

Subversion Repositories udp_ip_stack

[/] [udp_ip_stack/] [trunk/] [rtl/] [vhdl/] [tx_arbitrator.vhd] - Blame information for rev 2