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[/] [vhdl/] [ramedit.vhd] - Blame information for rev 2

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1 2 droggen
-- RAM editor
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-- 
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity ramedit is
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        generic(N : integer);
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        port(
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                        clk : in STD_LOGIC;
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                        rst : in STD_LOGIC;
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                        btnU : in STD_LOGIC;
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                        btnD : in STD_LOGIC;
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                        btnL : in STD_LOGIC;
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                        btnR : in STD_LOGIC;
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                        din : in STD_LOGIC_VECTOR(15 downto 0);
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                        we : out STD_LOGIC;
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                        address : out STD_LOGIC_VECTOR(N-1 downto 0);
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                        data : out STD_LOGIC_VECTOR(7 downto 0)
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                );
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end ramedit;
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architecture Behavioral of ramedit is
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        -- Register with the address we currently wish to edit
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        signal address_edit : STD_LOGIC_VECTOR(N-1 downto 0);
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begin
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        process(clk,rst)
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        begin
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                if rising_edge(clk) then
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                        if rst='1' then
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                                address_edit<=(others=>'0');
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                        else
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                                if btnU='1' and btnD='0' then
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                                        address_edit <= address_edit+1;
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                                elsif btnU='0' and btnD='1' then
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                                        address_edit <= address_edit-1;
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                                elsif btnL='1' then
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                                        address_edit <= din(8+N-1 downto 8);
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                                end if;
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                        end if;
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                end if;
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        end process;
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        we <= btnR;
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        address <= address_edit;
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        data <= din(7 downto 0);
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end Behavioral;
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