URL https://opencores.org/ocsvn/uos_processor/uos_processor/trunk

Subversion Repositories uos_processor

[/] [vhdl/] [readme.txt] - Blame information for rev 2

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University of Sussex Educational Processor
(c) Daniel Roggen, 2014-2017
 
**Files**
CPU:
- cpu.vhd: CPU itself
- cpualu.vhd: ALU
- cpuregbank.vhd: register bank
- cpusequencer.vhd: fetchh/fetchl/exec cycles
Top-level:
- labcpu.vhd: top level instantiating CPU, ram, ram editor, and interfacing to 7-segments, leds, and switches
Support:
- ram.vhd: RAM
- ramedit.vhd: RAM editor
- hexto7seg.vhd: hex to 7-seg decoder
- edgedetect.vhd: edge detector
- dffre.vhd: D flip-flop with reset and enable
- clkdiv.vhd: clock divider
- debounce.vhd: debouncer (borrowed from Altera Quartus)
- Nexys4_Master.xdc: constraint file

Line No.	Rev	Author	Line
1	2	droggen	`University of Sussex Educational Processor`
2			`(c) Daniel Roggen, 2014-2017`
3
4			`Files`
5			`CPU:`
6			`- cpu.vhd: CPU itself`
7			`- cpualu.vhd: ALU`
8			`- cpuregbank.vhd: register bank`
9			`- cpusequencer.vhd: fetchh/fetchl/exec cycles`
10			`Top-level:`
11			`- labcpu.vhd: top level instantiating CPU, ram, ram editor, and interfacing to 7-segments, leds, and switches`
12			`Support:`
13			`- ram.vhd: RAM`
14			`- ramedit.vhd: RAM editor`
15			`- hexto7seg.vhd: hex to 7-seg decoder`
16			`- edgedetect.vhd: edge detector`
17			`- dffre.vhd: D flip-flop with reset and enable`
18			`- clkdiv.vhd: clock divider`
19			`- debounce.vhd: debouncer (borrowed from Altera Quartus)`
20			`- Nexys4_Master.xdc: constraint file`

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Subversion Repositories uos_processor

[/] [vhdl/] [readme.txt] - Blame information for rev 2