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ultra_embe |
### uriscv - Another tiny RISC-V implementation
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Github: [https://github.com/ultraembedded/core_uriscv](https://github.com/ultraembedded/core_uriscv)
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Simple, small, multi-cycle 32-bit RISC-V CPU implementation.
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Most instructions take 2 cycles, apart from load/stores which take 4+ cycles (depending on memory latency), and division which can take up-to 34 cycles.
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## Features
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* 32-bit RISC-V ISA CPU core.
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* Support RISC-V’s integer (I), multiplication and division (M), and CSR instructions (Z) extensions (RV32IMZicsr).
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* Implements base ISA spec v2.1 and parts of the privileged ISA spec v1.11.
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* Supports machine mode privilege level only.
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* Configurable support for exceptions, interrupts, timers, multiplication, division and error traps.
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* Verified using random instruction sequences using cosimulation against [C++ ISA model](https://github.com/ultraembedded/exactstep).
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* Synthesizable Verilog 2001, Verilator and FPGA friendly.
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* Coremark: **1.48 CoreMark/MHz** (with HW mul/div)
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* Dhrystone: **0.58 DMIPS/MHz** ('legal compile options' / 337 instructions per iteration / with HW mul/div)
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**For my higher performance pipelined cores, see here:**
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* Coremark: **2.94CM/MHZ** - [http://github.com/ultraembedded/riscv](http://github.com/ultraembedded/riscv)
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* Coremark: **4.1CM/MHz** - [http://github.com/ultraembedded/biriscv](http://github.com/ultraembedded/biriscv)
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## Getting Started
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#### Cloning
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To clone this project and its dependencies;
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```
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git clone https://github.com/ultraembedded/core_uriscv.git
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```
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#### Running Helloworld
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To run a simple test image on the core RTL using Icarus Verilog;
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```
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# Install Icarus Verilog (Debian / Ubuntu / Linux Mint)
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sudo apt-get install iverilog
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# [or] Install Icarus Verilog (Redhat / Centos)
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#sudo yum install iverilog
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# Run a simple test image (test.elf)
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cd tb/tb_core_icarus
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make
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```
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The expected output is;
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```
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Starting bench
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VCD info: dumpfile waveform.vcd opened for output.
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Test:
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1. Initialised data
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2. Multiply
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3. Divide
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4. Shift left
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5. Shift right
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6. Shift right arithmetic
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7. Signed comparision
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8. Word access
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9. Byte access
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10. Comparision
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```
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#### Configuration
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| Param Name | Valid Range | Description |
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| ------------------------- |:------------:| ------------------------------------------------------------|
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| SUPPORT_MUL | 1/0 | Enable multiplication instructions. |
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| SUPPORT_DIV | 1/0 | Enable division instructions. |
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| SUPPORT_CSR | 1/0 | Global enable for CSR/trap/interrupt handling. |
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| SUPPORT_TRAP_LSU_ALIGN | 1/0 | Enable unaligned memory load / store exception. |
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| SUPPORT_MTVEC | 1/0 | Configurable exception entry address. |
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| SUPPORT_MTVAL | 1/0 | Support MTVAL CSR (holds bad addr / opcode). |
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| SUPPORT_MIP_MIE | 1/0 | Support MIE and MIP CSR registers. |
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| SUPPORT_MSCRATCH | 1/0 | Support MSCRATCH CSR registers (SW read/write). |
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| SUPPORT_MCYCLE | 1/0 | Support cycle counter / rdtime. |
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| SUPPORT_MTIMECMP | 1/0 | Non-std - support timer compare interrupt. |
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| SUPPORT_TRAP_INVALID_OPC | 1/0 | Fault on invalid opcodes (enable SW emulation). |
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| SUPPORT_BRAM_REGFILE | 1/0 | FPGA BlockRAM friendly reg file (inst take 1 cycle longer). |
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| ISR_VECTOR | 'h0-FFFFFFFF | ISR addr = reset_vector + ISR_VECTOR (SUPPORT_MTVEC = 0). |
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