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URL https://opencores.org/ocsvn/usb11_sim_model/usb11_sim_model/trunk

Subversion Repositories usb11_sim_model

[/] [usb11_sim_model/] [trunk/] [usb_test.do] - Blame information for rev 11

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Line No. Rev Author Line
1 2 M_artin
  ################################################################################################
2
  # This tcl-file is for usage with Model Sim, adopt this information to your simulator needs MN #
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  ################################################################################################
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  echo  "===>"
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  echo  "===> Recompiling Sources"
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  echo  "===>"
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9 11 M_artin
 #if {[file exists work]} { vdel -lib work -all }
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  vlib                      D:/Design/work
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  vmap           work       D:/Design/work
12 2 M_artin
 
13
  # Open Cores USB Phy, designed by Rudolf Usselmanns and translated to VHDL by Martin Neumann
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15 11 M_artin
  vcom -93 -work work       D:/design/completed_vhdl/usb_fs_port/usb_phy/usb_rx_phy_60MHz.vhdl
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  vcom -93 -work work       D:/design/completed_vhdl/usb_fs_port/usb_phy/usb_tx_phy.vhdl
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  vcom -93 -work work       D:/design/completed_vhdl/usb_fs_port/usb_phy/usb_phy.vhdl
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19 2 M_artin
  # Open Cores  USB Serial, designed by Joris van Rantwijk
20 11 M_artin
  vcom -93 -work work       D:/design/completed_vhdl/usb_fs_port/usb_serial/usb_pkg.vhdl
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  vcom -93 -work work       D:/design/completed_vhdl/usb_fs_port/usb_serial/usb_init.vhdl
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  vcom -93 -work work       D:/design/completed_vhdl/usb_fs_port/usb_serial/usb_control.vhdl
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  vcom -93 -work work       D:/design/completed_vhdl/usb_fs_port/usb_serial/usb_transact.vhdl
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  vcom -93 -work work       D:/design/completed_vhdl/usb_fs_port/usb_serial/usb_packet.vhdl
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  vcom -93 -work work       D:/design/completed_vhdl/usb_fs_port/usb_serial/usb_serial.vhdl
26 2 M_artin
 
27
  # The USB FS test bench files
28 11 M_artin
  vcom -93 -work work       D:/OpenCores/usb11_sim_model/trunk/usb_fs_port.vhdl
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  vcom -93 -work work       D:/OpenCores/usb11_sim_model/trunk/usb_commands.vhd
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  vcom -93 -work work       D:/OpenCores/usb11_sim_model/trunk/usb_stimuli.vhd
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  vcom -93 -work work       D:/OpenCores/usb11_sim_model/trunk/usb_fs_monitor.vhd
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  vcom -93 -work work       D:/OpenCores/usb11_sim_model/trunk/usb_fs_master.vhd
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  vcom -93 -work work       D:/OpenCores/usb11_sim_model/trunk/usb_tb.vhd
34 2 M_artin
 
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  echo  "===>"
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  echo  "===> Start Simulation"
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  echo  "===>"
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  vsim  -quiet usb_tb
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  #view source
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  view wave
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  configure wave -signalnamewidth 1
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  add wave -noupdate -divider {USB_Monitor}
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  add wave -noupdate -format Literal -radix decimal     /usb_tb/usb_fs_master/test_case/t_no
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_master/usb_fs_monitor/*
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_master/stimuli_bit
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  add wave -noupdate -divider {USB_MASTER}
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_master/*
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  add wave -noupdate -divider {USB_STIMULI}
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  add wave -noupdate -format Literal -radix decimal     /usb_tb/usb_fs_master/test_case/t_no
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_master/test_case/*
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  add wave -noupdate -divider {USB_PHY}
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  add wave -noupdate -format Literal -radix decimal     /usb_tb/usb_fs_master/test_case/t_no
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_slave_1/usb_phy_1/*
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# add wave -noupdate -divider {USB_RX_PHY}
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# add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_slave_1/usb_phy_1/i_rx_phy/*
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#
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# add wave -noupdate -divider
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# add wave -noupdate -divider {USB_TX_PHY}
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# add wave -noupdate -format Literal -radix decimal /usb_tb/usb_fs_master/test_case/t_no
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# add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_slave_1/usb_phy_1/i_tx_phy/*
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  add wave -noupdate -divider {USB_SERIAL}
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  add wave -noupdate -format Literal -radix decimal     /usb_tb/usb_fs_master/test_case/t_no
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_slave_1/usb_serial_1/*
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  add wave -noupdate -divider {USB_S-INIT}
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_slave_1/usb_serial_1/usb_init_inst/*
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  add wave -noupdate -divider {USB_S-PACKET}
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_slave_1/usb_serial_1/usb_packet_inst/*
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  add wave -noupdate -divider {USB_S-TRANSACT}
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  add wave -noupdate -format Literal -radix decimal     /usb_tb/usb_fs_master/test_case/t_no
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_slave_1/usb_serial_1/usb_transact_inst/*
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  add wave -noupdate -divider {USB_S-CONTROL}
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  add wave -noupdate -format Logic   -radix hexadecimal /usb_tb/usb_fs_slave_1/usb_serial_1/usb_control_inst/*
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  onbreak {resume}
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  run -all

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