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dinesha |
/**********************************************************************
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* Ported to USB2UART Project
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* Author: Dinesh Annayya
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* Email:- dinesha@opencores.org
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*
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* Date: 4th Feb 2013
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* Changes:
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* A. Warning Clean Up
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* B. USB1-phy is move to core level
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*
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**********************************************************************/
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// USB 1.1 function IP core ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/usb1_funct/////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: usb1_core.v,v 1.2 2002-10-11 05:48:20 rudi Exp $
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//
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// $Date: 2002-10-11 05:48:20 $
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// $Revision: 1.2 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.1 2002/09/25 06:06:49 rudi
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// - Added New Top Level
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// - Remove old top level and associated files
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// - Moved FIFOs to "Generic FIFOs" project
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//
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//
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//
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//
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//
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//
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//
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`include "usb1_defines.v"
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/*
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// USB PHY Interface
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tx_dp, tx_dn, tx_oe,
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rx_d, rx_dp, rx_dn,
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These pins are a semi-standard interface to USB 1.1 transceivers.
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Just match up the signal names with the IOs of the transceiver.
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// USB Misc
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phy_tx_mode, usb_rst,
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The PHY supports single ended and differential output to the
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transceiver Depending on which device you are using, you have
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to tie the phy_tx_mode high or low.
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usb_rst is asserted whenever the host signals reset on the USB
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bus. The USB core will internally reset itself automatically.
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This output is provided for external logic that needs to be
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reset when the USB bus is reset.
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// Interrupts
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dropped_frame, misaligned_frame,
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crc16_err,
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dropped_frame, misaligned_frame are interrupt to indicate error
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conditions in Block Frame mode.
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crc16_err, indicates when a crc 16 error was detected on the
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payload of a USB packet.
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// Vendor Features
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v_set_int, v_set_feature, wValue,
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wIndex, vendor_data,
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This signals allow to control vendor specific registers and logic
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that can be manipulated and monitored via the control endpoint
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through vendor defined commands.
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// USB Status
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usb_busy, ep_sel,
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usb_busy is asserted when the USB core is busy transferring
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data ep_sel indicated the endpoint that is currently busy.
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This information might be useful if one desires to reset/clear
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the attached FIFOs and want to do this when the endpoint is idle.
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// Endpoint Interface
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This implementation supports 8 endpoints. Endpoint 0 is the
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control endpoint and used internally. Endpoints 1-7 are available
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to the user. replace 'N' with the endpoint number.
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epN_cfg,
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This is a constant input used to configure the endpoint by ORing
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these defines together and adding the max packet size for this
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endpoint:
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`IN and `OUT select the transfer direction for this endpoint
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`ISO, `BULK and `INT determine the endpoint type
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Example: "`BULK | `IN | 14'd064" defines a BULK IN endpoint with
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max packet size of 64 bytes
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epN_din, epN_we, epN_full,
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This is the OUT FIFO interface. If this is a IN endpoint, ground
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all unused inputs and leave outputs unconnected.
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epN_dout, epN_re, epN_empty,
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this is the IN FIFO interface. If this is a OUT endpoint ground
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all unused inputs and leave outputs unconnected.
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epN_bf_en, epN_bf_size,
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These two constant configure the Block Frame feature.
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*/
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module usb1_core(clk_i, rst_i,
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// UTMI Interface
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DataOut, TxValid, TxReady, RxValid,
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RxActive, RxError, DataIn, LineState,
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// USB Misc
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phy_tx_mode, usb_rst,
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// Interrupts
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dropped_frame, misaligned_frame,
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crc16_err,
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// Vendor Features
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v_set_int, v_set_feature, wValue,
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wIndex, vendor_data,
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// USB Status
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usb_busy, ep_sel,
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// Endpoint Interface
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ep1_cfg,
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ep1_din, ep1_we, ep1_full,
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ep1_dout, ep1_re, ep1_empty,
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ep1_bf_en, ep1_bf_size,
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ep2_cfg,
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ep2_din, ep2_we, ep2_full,
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ep2_dout, ep2_re, ep2_empty,
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ep2_bf_en, ep2_bf_size,
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ep3_cfg,
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ep3_din, ep3_we, ep3_full,
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ep3_dout, ep3_re, ep3_empty,
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ep3_bf_en, ep3_bf_size,
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ep4_cfg,
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ep4_din, ep4_we, ep4_full,
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ep4_dout, ep4_re, ep4_empty,
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ep4_bf_en, ep4_bf_size,
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ep5_cfg,
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ep5_din, ep5_we, ep5_full,
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ep5_dout, ep5_re, ep5_empty,
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ep5_bf_en, ep5_bf_size,
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ep6_cfg,
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ep6_din, ep6_we, ep6_full,
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ep6_dout, ep6_re, ep6_empty,
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ep6_bf_en, ep6_bf_size,
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ep7_cfg,
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ep7_din, ep7_we, ep7_full,
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ep7_dout, ep7_re, ep7_empty,
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ep7_bf_en, ep7_bf_size,
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// Register Interface
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reg_addr,
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reg_rdwrn,
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reg_req,
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reg_wdata,
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reg_rdata,
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reg_ack
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);
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input clk_i;
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input rst_i;
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//------------------------------------
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// UTMI Interface
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// -----------------------------------
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output [7:0] DataOut;
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output TxValid;
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input TxReady;
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input [7:0] DataIn;
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input RxValid;
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input RxActive;
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input RxError;
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input [1:0] LineState;
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input phy_tx_mode;
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input usb_rst;
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output dropped_frame, misaligned_frame;
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output crc16_err;
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output v_set_int;
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output v_set_feature;
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output [15:0] wValue;
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output [15:0] wIndex;
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input [15:0] vendor_data;
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output usb_busy;
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output [3:0] ep_sel;
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//-----------------------------------
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// Register Interface
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// ----------------------------------
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output [31:0] reg_addr; // Register Address
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output reg_rdwrn; // 0 -> write, 1-> read
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output reg_req; // Register Req
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output [31:0] reg_wdata; // Register write data
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input [31:0] reg_rdata; // Register Read Data
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input reg_ack; // Register Ack
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// Endpoint Interfaces
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input [13:0] ep1_cfg;
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input [7:0] ep1_din;
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output [7:0] ep1_dout;
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output ep1_we, ep1_re;
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input ep1_empty, ep1_full;
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input ep1_bf_en;
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input [6:0] ep1_bf_size;
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input [13:0] ep2_cfg;
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input [7:0] ep2_din;
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output [7:0] ep2_dout;
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output ep2_we, ep2_re;
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input ep2_empty, ep2_full;
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input ep2_bf_en;
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input [6:0] ep2_bf_size;
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input [13:0] ep3_cfg;
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input [7:0] ep3_din;
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output [7:0] ep3_dout;
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output ep3_we, ep3_re;
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input ep3_empty, ep3_full;
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input ep3_bf_en;
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input [6:0] ep3_bf_size;
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input [13:0] ep4_cfg;
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input [7:0] ep4_din;
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output [7:0] ep4_dout;
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output ep4_we, ep4_re;
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input ep4_empty, ep4_full;
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input ep4_bf_en;
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input [6:0] ep4_bf_size;
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input [13:0] ep5_cfg;
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input [7:0] ep5_din;
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output [7:0] ep5_dout;
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output ep5_we, ep5_re;
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input ep5_empty, ep5_full;
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input ep5_bf_en;
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input [6:0] ep5_bf_size;
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input [13:0] ep6_cfg;
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input [7:0] ep6_din;
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output [7:0] ep6_dout;
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output ep6_we, ep6_re;
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input ep6_empty, ep6_full;
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input ep6_bf_en;
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input [6:0] ep6_bf_size;
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input [13:0] ep7_cfg;
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input [7:0] ep7_din;
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output [7:0] ep7_dout;
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output ep7_we, ep7_re;
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input ep7_empty, ep7_full;
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input ep7_bf_en;
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input [6:0] ep7_bf_size;
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///////////////////////////////////////////////////////////////////
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//
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// Local Wires and Registers
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//
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wire [7:0] rx_data;
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wire rx_valid, rx_active, rx_err;
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wire [7:0] tx_data;
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wire tx_valid;
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wire tx_ready;
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wire tx_first;
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wire tx_valid_last;
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// Internal Register File Interface
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wire [6:0] funct_adr; // This functions address (set by controller)
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wire [3:0] ep_sel; // Endpoint Number Input
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wire crc16_err; // Set CRC16 error interrupt
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wire int_to_set; // Set time out interrupt
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wire int_seqerr_set; // Set PID sequence error interrupt
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wire [31:0] frm_nat; // Frame Number and Time Register
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wire nse_err; // No Such Endpoint Error
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wire pid_cs_err; // PID CS error
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wire crc5_err; // CRC5 Error
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reg [7:0] tx_data_st;
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wire [7:0] rx_ctrl_data;
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wire [7:0] rx_ctrl_data_d;
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reg [13:0] cfg;
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reg ep_empty;
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reg ep_full;
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wire [7:0] rx_size;
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wire rx_done;
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wire [7:0] ep0_din;
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wire [7:0] ep0_dout;
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wire ep0_re, ep0_we;
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wire [13:0] ep0_cfg;
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wire [7:0] ep0_size;
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wire [7:0] ep0_ctrl_dout, ep0_ctrl_din;
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|
|
wire ep0_ctrl_re, ep0_ctrl_we;
|
| 345 |
|
|
wire [3:0] ep0_ctrl_stat;
|
| 346 |
|
|
|
| 347 |
|
|
wire ctrl_setup, ctrl_in, ctrl_out;
|
| 348 |
|
|
wire send_stall;
|
| 349 |
|
|
wire token_valid;
|
| 350 |
|
|
reg rst_local; // internal reset
|
| 351 |
|
|
wire dropped_frame;
|
| 352 |
|
|
wire misaligned_frame;
|
| 353 |
|
|
wire v_set_int;
|
| 354 |
|
|
wire v_set_feature;
|
| 355 |
|
|
wire [15:0] wValue;
|
| 356 |
|
|
wire [15:0] wIndex;
|
| 357 |
|
|
|
| 358 |
|
|
reg ep_bf_en;
|
| 359 |
|
|
reg [6:0] ep_bf_size;
|
| 360 |
|
|
wire [6:0] rom_adr;
|
| 361 |
|
|
wire [7:0] rom_data;
|
| 362 |
|
|
|
| 363 |
|
|
///////////////////////////////////////////////////////////////////
|
| 364 |
|
|
//
|
| 365 |
|
|
// Misc Logic
|
| 366 |
|
|
//
|
| 367 |
|
|
|
| 368 |
|
|
// Endpoint type and Max transfer size
|
| 369 |
|
|
assign ep0_cfg = `CTRL | ep0_size;
|
| 370 |
|
|
|
| 371 |
|
|
always @(posedge clk_i)
|
| 372 |
|
|
rst_local <= #1 rst_i & ~usb_rst;
|
| 373 |
|
|
|
| 374 |
|
|
///////////////////////////////////////////////////////////////////
|
| 375 |
|
|
//
|
| 376 |
|
|
// Module Instantiations
|
| 377 |
|
|
//
|
| 378 |
|
|
/******* Move to phy logic is move to core level
|
| 379 |
|
|
usb_phy phy(
|
| 380 |
|
|
.clk( clk_i ),
|
| 381 |
|
|
.rst( rst_i ), // ONLY external reset
|
| 382 |
|
|
.phy_tx_mode( phy_tx_mode ),
|
| 383 |
|
|
.usb_rst( usb_rst ),
|
| 384 |
|
|
|
| 385 |
|
|
// Transceiver Interface
|
| 386 |
|
|
.rxd( rx_d ),
|
| 387 |
|
|
.rxdp( rx_dp ),
|
| 388 |
|
|
.rxdn( rx_dn ),
|
| 389 |
|
|
.txdp( tx_dp ),
|
| 390 |
|
|
.txdn( tx_dn ),
|
| 391 |
|
|
.txoe( tx_oe ),
|
| 392 |
|
|
|
| 393 |
|
|
// UTMI Interface
|
| 394 |
|
|
.DataIn_o( DataIn ),
|
| 395 |
|
|
.RxValid_o( RxValid ),
|
| 396 |
|
|
.RxActive_o( RxActive ),
|
| 397 |
|
|
.RxError_o( RxError ),
|
| 398 |
|
|
.DataOut_i( DataOut ),
|
| 399 |
|
|
.TxValid_i( TxValid ),
|
| 400 |
|
|
.TxReady_o( TxReady ),
|
| 401 |
|
|
.LineState_o( LineState )
|
| 402 |
|
|
);
|
| 403 |
|
|
*******************************/
|
| 404 |
|
|
// UTMI Interface
|
| 405 |
|
|
usb1_utmi_if u0(
|
| 406 |
|
|
.phy_clk( clk_i ),
|
| 407 |
|
|
.rst( rst_local ),
|
| 408 |
|
|
// Interface towards Phy-Tx
|
| 409 |
|
|
.DataOut( DataOut ),
|
| 410 |
|
|
.TxValid( TxValid ),
|
| 411 |
|
|
.TxReady( TxReady ),
|
| 412 |
|
|
|
| 413 |
|
|
// Interface towards Phy-rx
|
| 414 |
|
|
.RxValid( RxValid ),
|
| 415 |
|
|
.RxActive( RxActive ),
|
| 416 |
|
|
.RxError( RxError ),
|
| 417 |
|
|
.DataIn( DataIn ),
|
| 418 |
|
|
|
| 419 |
|
|
// Interfcae towards protocol layer-rx
|
| 420 |
|
|
.rx_data( rx_data ),
|
| 421 |
|
|
.rx_valid( rx_valid ),
|
| 422 |
|
|
.rx_active( rx_active ),
|
| 423 |
|
|
.rx_err( rx_err ),
|
| 424 |
|
|
|
| 425 |
|
|
// Interfcae towards protocol layer-tx
|
| 426 |
|
|
.tx_data( tx_data ),
|
| 427 |
|
|
.tx_valid( tx_valid ),
|
| 428 |
|
|
.tx_valid_last( tx_valid_last ),
|
| 429 |
|
|
.tx_ready( tx_ready ),
|
| 430 |
|
|
.tx_first( tx_first )
|
| 431 |
|
|
);
|
| 432 |
|
|
|
| 433 |
|
|
// Protocol Layer
|
| 434 |
|
|
usb1_pl u1( .clk( clk_i ),
|
| 435 |
|
|
.rst( rst_local ),
|
| 436 |
|
|
// Interface towards utmi-rx
|
| 437 |
|
|
.rx_data( rx_data ),
|
| 438 |
|
|
.rx_valid( rx_valid ),
|
| 439 |
|
|
.rx_active( rx_active ),
|
| 440 |
|
|
.rx_err( rx_err ),
|
| 441 |
|
|
|
| 442 |
|
|
// Interface towards utmi-tx
|
| 443 |
|
|
.tx_data( tx_data ),
|
| 444 |
|
|
.tx_valid( tx_valid ),
|
| 445 |
|
|
.tx_valid_last( tx_valid_last ),
|
| 446 |
|
|
.tx_ready( tx_ready ),
|
| 447 |
|
|
.tx_first( tx_first ),
|
| 448 |
|
|
|
| 449 |
|
|
// Interface towards usb-phy-tx
|
| 450 |
|
|
.tx_valid_out( TxValid ),
|
| 451 |
|
|
|
| 452 |
|
|
// unused outputs
|
| 453 |
|
|
.token_valid( token_valid ),
|
| 454 |
|
|
.int_to_set( int_to_set ),
|
| 455 |
|
|
.int_seqerr_set( int_seqerr_set ),
|
| 456 |
|
|
.pid_cs_err( pid_cs_err ),
|
| 457 |
|
|
.nse_err( nse_err ),
|
| 458 |
|
|
.crc5_err( crc5_err ),
|
| 459 |
|
|
.rx_size( rx_size ),
|
| 460 |
|
|
.rx_done( rx_done ),
|
| 461 |
|
|
|
| 462 |
|
|
// Interface towards usb-ctrl
|
| 463 |
|
|
.fa( funct_adr ),
|
| 464 |
|
|
.frm_nat( frm_nat ),
|
| 465 |
|
|
.ctrl_setup( ctrl_setup ),
|
| 466 |
|
|
.ctrl_in( ctrl_in ),
|
| 467 |
|
|
.ctrl_out( ctrl_out ),
|
| 468 |
|
|
.send_stall( send_stall ),
|
| 469 |
|
|
|
| 470 |
|
|
// usb-status
|
| 471 |
|
|
.ep_sel( ep_sel ),
|
| 472 |
|
|
.x_busy( usb_busy ),
|
| 473 |
|
|
.int_crc16_set( crc16_err ),
|
| 474 |
|
|
.dropped_frame( dropped_frame ),
|
| 475 |
|
|
.misaligned_frame( misaligned_frame ),
|
| 476 |
|
|
|
| 477 |
|
|
.ep_bf_en( ep_bf_en ),
|
| 478 |
|
|
.ep_bf_size( ep_bf_size ),
|
| 479 |
|
|
.csr( cfg ),
|
| 480 |
|
|
.tx_data_st( tx_data_st ),
|
| 481 |
|
|
|
| 482 |
|
|
.rx_ctrl_data (rx_ctrl_data ),
|
| 483 |
|
|
.rx_ctrl_data_d (rx_ctrl_data_d ),
|
| 484 |
|
|
.rx_ctrl_dvalid (rx_ctrl_dvalid ),
|
| 485 |
|
|
.rx_ctrl_ddone (rx_ctrl_ddone ),
|
| 486 |
|
|
|
| 487 |
|
|
.idma_re( idma_re ),
|
| 488 |
|
|
.idma_we( idma_we ),
|
| 489 |
|
|
.ep_empty( ep_empty ),
|
| 490 |
|
|
.ep_full( ep_full )
|
| 491 |
|
|
);
|
| 492 |
|
|
|
| 493 |
|
|
usb1_ctrl u4( .clk( clk_i ),
|
| 494 |
|
|
.rst( rst_local ),
|
| 495 |
|
|
|
| 496 |
|
|
.rom_adr( rom_adr ),
|
| 497 |
|
|
.rom_data( rom_data ),
|
| 498 |
|
|
|
| 499 |
|
|
.ctrl_setup( ctrl_setup ),
|
| 500 |
|
|
.ctrl_in( ctrl_in ),
|
| 501 |
|
|
.ctrl_out( ctrl_out ),
|
| 502 |
|
|
|
| 503 |
|
|
.rx_ctrl_data (rx_ctrl_data ),
|
| 504 |
|
|
.rx_ctrl_dvalid (rx_ctrl_dvalid ),
|
| 505 |
|
|
.rx_ctrl_ddone (rx_ctrl_ddone ),
|
| 506 |
|
|
|
| 507 |
|
|
|
| 508 |
|
|
.ep0_din( ep0_ctrl_dout ),
|
| 509 |
|
|
.ep0_dout( ep0_ctrl_din ),
|
| 510 |
|
|
.ep0_re( ep0_ctrl_re ),
|
| 511 |
|
|
.ep0_we( ep0_ctrl_we ),
|
| 512 |
|
|
.ep0_stat( ep0_ctrl_stat ),
|
| 513 |
|
|
.ep0_size( ep0_size ),
|
| 514 |
|
|
|
| 515 |
|
|
.send_stall( send_stall ),
|
| 516 |
|
|
.frame_no( frm_nat[26:16] ),
|
| 517 |
|
|
.funct_adr( funct_adr ),
|
| 518 |
|
|
.configured( ),
|
| 519 |
|
|
.halt( ),
|
| 520 |
|
|
|
| 521 |
|
|
.v_set_int( v_set_int ),
|
| 522 |
|
|
.v_set_feature( v_set_feature ),
|
| 523 |
|
|
.wValue( wValue ),
|
| 524 |
|
|
.wIndex( wIndex ),
|
| 525 |
|
|
.vendor_data( vendor_data ),
|
| 526 |
|
|
|
| 527 |
|
|
// Register Interface
|
| 528 |
|
|
.reg_addr (reg_addr),
|
| 529 |
|
|
.reg_rdwrn (reg_rdwrn),
|
| 530 |
|
|
.reg_req (reg_req),
|
| 531 |
|
|
.reg_wdata (reg_wdata),
|
| 532 |
|
|
.reg_rdata (reg_rdata),
|
| 533 |
|
|
.reg_ack (reg_ack)
|
| 534 |
|
|
|
| 535 |
|
|
);
|
| 536 |
|
|
|
| 537 |
|
|
|
| 538 |
|
|
usb1_rom1 rom1( .clk( clk_i ),
|
| 539 |
|
|
.adr( rom_adr ),
|
| 540 |
|
|
.dout( rom_data )
|
| 541 |
|
|
);
|
| 542 |
|
|
|
| 543 |
|
|
// CTRL Endpoint FIFO
|
| 544 |
|
|
/*************
|
| 545 |
|
|
generic_fifo_sc_a #(8,6,0) u10(
|
| 546 |
|
|
.clk( clk_i ),
|
| 547 |
|
|
.rst( rst_i ),
|
| 548 |
|
|
.clr( usb_rst ),
|
| 549 |
|
|
.din( rx_ctrl_data_d ),
|
| 550 |
|
|
.we( ep0_we ),
|
| 551 |
|
|
.dout( ep0_ctrl_dout ),
|
| 552 |
|
|
.re( ep0_ctrl_re ),
|
| 553 |
|
|
.full_r( ),
|
| 554 |
|
|
.empty_r( ),
|
| 555 |
|
|
.full( ep0_full ),
|
| 556 |
|
|
.empty( ep0_ctrl_stat[1] ),
|
| 557 |
|
|
.full_n( ),
|
| 558 |
|
|
.empty_n( ),
|
| 559 |
|
|
.full_n_r( ),
|
| 560 |
|
|
.empty_n_r( ),
|
| 561 |
|
|
.level( )
|
| 562 |
|
|
);
|
| 563 |
|
|
|
| 564 |
|
|
*************/
|
| 565 |
|
|
// CTRL Endpoint FIFO
|
| 566 |
|
|
sync_fifo #(8,8) u10(
|
| 567 |
|
|
.clk (clk_i),
|
| 568 |
|
|
.reset_n (rst_i),
|
| 569 |
|
|
.clr (usb_rst),
|
| 570 |
|
|
.wr_en (ep0_we),
|
| 571 |
|
|
.wr_data (rx_ctrl_data_d),
|
| 572 |
|
|
.full (ep0_full),
|
| 573 |
|
|
.empty (ep0_ctrl_stat[1]),
|
| 574 |
|
|
.rd_en (ep0_ctrl_re),
|
| 575 |
|
|
.rd_data (ep0_ctrl_dout)
|
| 576 |
|
|
);
|
| 577 |
|
|
generic_fifo_sc_a #(8,6,0) u11(
|
| 578 |
|
|
.clk( clk_i ),
|
| 579 |
|
|
.rst( rst_i ),
|
| 580 |
|
|
.clr( usb_rst ),
|
| 581 |
|
|
.din( ep0_ctrl_din ),
|
| 582 |
|
|
.we( ep0_ctrl_we ),
|
| 583 |
|
|
.dout( ep0_dout ),
|
| 584 |
|
|
.re( ep0_re ),
|
| 585 |
|
|
.full_r( ),
|
| 586 |
|
|
.empty_r( ),
|
| 587 |
|
|
.full( ep0_ctrl_stat[2] ),
|
| 588 |
|
|
.empty( ep0_empty ),
|
| 589 |
|
|
.full_n( ),
|
| 590 |
|
|
.empty_n( ),
|
| 591 |
|
|
.full_n_r( ),
|
| 592 |
|
|
.empty_n_r( ),
|
| 593 |
|
|
.level( )
|
| 594 |
|
|
);
|
| 595 |
|
|
|
| 596 |
|
|
|
| 597 |
|
|
///////////////////////////////////////////////////////////////////
|
| 598 |
|
|
//
|
| 599 |
|
|
// Endpoint FIFO Interfaces
|
| 600 |
|
|
//
|
| 601 |
|
|
|
| 602 |
|
|
always @(ep_sel or ep0_cfg or ep1_cfg or ep2_cfg or ep3_cfg or
|
| 603 |
|
|
ep4_cfg or ep5_cfg or ep6_cfg or ep7_cfg)
|
| 604 |
|
|
case(ep_sel) // synopsys full_case parallel_case
|
| 605 |
|
|
4'h0: cfg = ep0_cfg;
|
| 606 |
|
|
4'h1: cfg = ep1_cfg;
|
| 607 |
|
|
4'h2: cfg = ep2_cfg;
|
| 608 |
|
|
4'h3: cfg = ep3_cfg;
|
| 609 |
|
|
4'h4: cfg = ep4_cfg;
|
| 610 |
|
|
4'h5: cfg = ep5_cfg;
|
| 611 |
|
|
4'h6: cfg = ep6_cfg;
|
| 612 |
|
|
4'h7: cfg = ep7_cfg;
|
| 613 |
|
|
endcase
|
| 614 |
|
|
|
| 615 |
|
|
// In endpoints only
|
| 616 |
|
|
always @(posedge clk_i)
|
| 617 |
|
|
case(ep_sel) // synopsys full_case parallel_case
|
| 618 |
|
|
4'h0: tx_data_st <= #1 ep0_dout;
|
| 619 |
|
|
4'h1: tx_data_st <= #1 ep1_din;
|
| 620 |
|
|
4'h2: tx_data_st <= #1 ep2_din;
|
| 621 |
|
|
4'h3: tx_data_st <= #1 ep3_din;
|
| 622 |
|
|
4'h4: tx_data_st <= #1 ep4_din;
|
| 623 |
|
|
4'h5: tx_data_st <= #1 ep5_din;
|
| 624 |
|
|
4'h6: tx_data_st <= #1 ep6_din;
|
| 625 |
|
|
4'h7: tx_data_st <= #1 ep7_din;
|
| 626 |
|
|
endcase
|
| 627 |
|
|
|
| 628 |
|
|
// In endpoints only
|
| 629 |
|
|
always @(posedge clk_i)
|
| 630 |
|
|
case(ep_sel) // synopsys full_case parallel_case
|
| 631 |
|
|
4'h0: ep_empty <= #1 ep0_empty;
|
| 632 |
|
|
4'h1: ep_empty <= #1 ep1_empty;
|
| 633 |
|
|
4'h2: ep_empty <= #1 ep2_empty;
|
| 634 |
|
|
4'h3: ep_empty <= #1 ep3_empty;
|
| 635 |
|
|
4'h4: ep_empty <= #1 ep4_empty;
|
| 636 |
|
|
4'h5: ep_empty <= #1 ep5_empty;
|
| 637 |
|
|
4'h6: ep_empty <= #1 ep6_empty;
|
| 638 |
|
|
4'h7: ep_empty <= #1 ep7_empty;
|
| 639 |
|
|
endcase
|
| 640 |
|
|
|
| 641 |
|
|
// OUT endpoints only
|
| 642 |
|
|
always @(ep_sel or ep0_full or ep1_full or ep2_full or ep3_full or
|
| 643 |
|
|
ep4_full or ep5_full or ep6_full or ep7_full)
|
| 644 |
|
|
case(ep_sel) // synopsys full_case parallel_case
|
| 645 |
|
|
4'h0: ep_full = ep0_full;
|
| 646 |
|
|
4'h1: ep_full = ep1_full;
|
| 647 |
|
|
4'h2: ep_full = ep2_full;
|
| 648 |
|
|
4'h3: ep_full = ep3_full;
|
| 649 |
|
|
4'h4: ep_full = ep4_full;
|
| 650 |
|
|
4'h5: ep_full = ep5_full;
|
| 651 |
|
|
4'h6: ep_full = ep6_full;
|
| 652 |
|
|
4'h7: ep_full = ep7_full;
|
| 653 |
|
|
endcase
|
| 654 |
|
|
|
| 655 |
|
|
always @(posedge clk_i)
|
| 656 |
|
|
case(ep_sel) // synopsys full_case parallel_case
|
| 657 |
|
|
4'h0: ep_bf_en = 1'b0;
|
| 658 |
|
|
4'h1: ep_bf_en = ep1_bf_en;
|
| 659 |
|
|
4'h2: ep_bf_en = ep2_bf_en;
|
| 660 |
|
|
4'h3: ep_bf_en = ep3_bf_en;
|
| 661 |
|
|
4'h4: ep_bf_en = ep4_bf_en;
|
| 662 |
|
|
4'h5: ep_bf_en = ep5_bf_en;
|
| 663 |
|
|
4'h6: ep_bf_en = ep6_bf_en;
|
| 664 |
|
|
4'h7: ep_bf_en = ep7_bf_en;
|
| 665 |
|
|
endcase
|
| 666 |
|
|
|
| 667 |
|
|
always @(posedge clk_i)
|
| 668 |
|
|
case(ep_sel) // synopsys full_case parallel_case
|
| 669 |
|
|
4'h1: ep_bf_size = ep1_bf_size;
|
| 670 |
|
|
4'h2: ep_bf_size = ep2_bf_size;
|
| 671 |
|
|
4'h3: ep_bf_size = ep3_bf_size;
|
| 672 |
|
|
4'h4: ep_bf_size = ep4_bf_size;
|
| 673 |
|
|
4'h5: ep_bf_size = ep5_bf_size;
|
| 674 |
|
|
4'h6: ep_bf_size = ep6_bf_size;
|
| 675 |
|
|
4'h7: ep_bf_size = ep7_bf_size;
|
| 676 |
|
|
endcase
|
| 677 |
|
|
|
| 678 |
|
|
assign ep1_dout = rx_ctrl_data_d;
|
| 679 |
|
|
assign ep2_dout = rx_ctrl_data_d;
|
| 680 |
|
|
assign ep3_dout = rx_ctrl_data_d;
|
| 681 |
|
|
assign ep4_dout = rx_ctrl_data_d;
|
| 682 |
|
|
assign ep5_dout = rx_ctrl_data_d;
|
| 683 |
|
|
assign ep6_dout = rx_ctrl_data_d;
|
| 684 |
|
|
assign ep7_dout = rx_ctrl_data_d;
|
| 685 |
|
|
|
| 686 |
|
|
assign ep0_re = idma_re & (ep_sel == 4'h0);
|
| 687 |
|
|
assign ep1_re = idma_re & (ep_sel == 4'h1) & !ep1_empty;
|
| 688 |
|
|
assign ep2_re = idma_re & (ep_sel == 4'h2) & !ep2_empty;
|
| 689 |
|
|
assign ep3_re = idma_re & (ep_sel == 4'h3) & !ep3_empty;
|
| 690 |
|
|
assign ep4_re = idma_re & (ep_sel == 4'h4) & !ep4_empty;
|
| 691 |
|
|
assign ep5_re = idma_re & (ep_sel == 4'h5) & !ep5_empty;
|
| 692 |
|
|
assign ep6_re = idma_re & (ep_sel == 4'h6) & !ep6_empty;
|
| 693 |
|
|
assign ep7_re = idma_re & (ep_sel == 4'h7) & !ep7_empty;
|
| 694 |
|
|
|
| 695 |
|
|
assign ep0_we = idma_we & (ep_sel == 4'h0);
|
| 696 |
|
|
assign ep1_we = idma_we & (ep_sel == 4'h1) & !ep1_full;
|
| 697 |
|
|
assign ep2_we = idma_we & (ep_sel == 4'h2) & !ep2_full;
|
| 698 |
|
|
assign ep3_we = idma_we & (ep_sel == 4'h3) & !ep3_full;
|
| 699 |
|
|
assign ep4_we = idma_we & (ep_sel == 4'h4) & !ep4_full;
|
| 700 |
|
|
assign ep5_we = idma_we & (ep_sel == 4'h5) & !ep5_full;
|
| 701 |
|
|
assign ep6_we = idma_we & (ep_sel == 4'h6) & !ep6_full;
|
| 702 |
|
|
assign ep7_we = idma_we & (ep_sel == 4'h7) & !ep7_full;
|
| 703 |
|
|
|
| 704 |
|
|
endmodule
|
