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[/] [usb2uart/] [trunk/] [verify/] [agents/] [uart/] [uart_agent.v] - Blame information for rev 3

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`timescale  1ns/1ps
 
module uart_agent (
        test_clk,
        sin,
        sout)
        ;
 
input   test_clk;
output  sin;
 
input   sout;
 
event   uart_read_done, uart_write_done;
event   error_detected,uart_parity_error, uart_stop_error1, uart_stop_error2;
event   uart_timeout_error;
event   abort;
 
reg [15:0] rx_count;
reg [15:0] tx_count;
reg [15:0] par_err_count;
reg [15:0] stop_err1_cnt;
reg [15:0] stop_err2_cnt;
reg [15:0] timeout_err_cnt;
reg [15:0] err_cnt;
 
reg        sin, read, write;
wire       test_rx_clk;
reg        test_tx_clk;
reg        stop_err_check;
reg      [15:0] cnt_16x;
 
integer timeout_count;
integer data_bit_number;
reg [2:0] clk_count;
 
reg      error_ind; // 1 indicate error
 
initial
begin
        sin = 1'b1;
        test_tx_clk = 0;
        clk_count = 0;
        stop_err_check = 0;
        error_ind = 0;
        cnt_16x = 0;
end
 
always @(posedge test_clk)
begin
        if (clk_count == 3'h0) // Divide by 16 Counter
        begin
           if(cnt_16x >= control_setup.divisor) begin
               test_tx_clk = ~test_tx_clk;
               cnt_16x = 0;
           end else begin
               cnt_16x = cnt_16x+1;
           end
        end
        clk_count = clk_count + 1;
end
assign test_rx_clk = ~test_tx_clk;
 
always @(posedge test_clk) begin
        timeout_count = timeout_count + 1;
        if (timeout_count == (control_setup.maxtime * 16))
                -> abort;
end
 
always @uart_read_done
        rx_count = rx_count + 1;
 
always @uart_write_done
        tx_count = tx_count + 1;
 
always @uart_parity_error begin
  error_ind = 1;
        par_err_count = par_err_count + 1;
end
 
always @uart_stop_error1 begin
  error_ind = 1;
        stop_err1_cnt = stop_err1_cnt + 1;
end
 
always @uart_stop_error2 begin
  error_ind = 1;
        stop_err2_cnt = stop_err2_cnt + 1;
end
 
always @uart_timeout_error begin
  error_ind = 1;
        timeout_err_cnt = timeout_err_cnt + 1;
end
 
 
always @error_detected begin
  error_ind = 1;
        err_cnt = err_cnt + 1;
end
 
 
////////////////////////////////////////////////////////////////////////////////
task uart_init;
begin
  read = 0;
  write = 0;
        tx_count = 0;
        rx_count = 0;
  stop_err_check = 0;
  par_err_count = 0;
  stop_err1_cnt = 0;
  stop_err2_cnt = 0;
  timeout_err_cnt = 0;
  err_cnt = 0;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////////
task read_char_chk;
input   expected_data;
 
integer i;
reg     [7:0] expected_data;
reg     [7:0] data;
reg     parity;
 
begin
        data <= 8'h0;
        parity <= 1;
        timeout_count = 0;
 
fork
   begin : loop_1
        @(abort)
         $display (">>>>>  Exceed time limit, uart no responce.\n");
         ->uart_timeout_error;
         disable loop_2;
   end
 
   begin : loop_2
 
// start cycle
        @(negedge sout)
         disable loop_1;
         read <= 1;
 
// data cycle
        @(posedge test_rx_clk);
         for (i = 0; i < data_bit_number; i = i + 1)
          begin
            @(posedge test_rx_clk)
            data[i] <=  sout;
            parity <= parity ^ sout;
          end
 
// parity cycle
        if(control_setup.parity_en)
        begin
          @(posedge test_rx_clk);
          if ((control_setup.even_odd_parity && (sout == parity)) ||
             (!control_setup.even_odd_parity && (sout != parity)))
// || (control_setup.stick_parity && (sout == control_setup.even_odd_parity)))
             begin
                $display (">>>>>  Parity Error");
                -> error_detected;
                -> uart_parity_error;
             end
        end
 
// stop cycle 1
        @(posedge test_rx_clk);
          if (!sout)
             begin
                $display (">>>>>  Stop signal 1 Error");
                -> error_detected;
                -> uart_stop_error1;
             end
 
// stop cycle 2
        if (control_setup.stop_bit_number)
        begin
              @(posedge test_rx_clk);   // stop cycle 2
                if (!sout)
                  begin
                    $display (">>>>>  Stop signal 2 Error");
                    -> error_detected;
                    -> uart_stop_error2;
                  end
        end
 
/*      Who Cares
// the stop bits transmitted is one and a half if it is 5-bit
        if (data_bit_number == 5)
        begin
                @(posedge test_rx_clk); // stop cycle for 5-bit/per char
                if (!sout)
                  begin
                    $display (">>>>>  Stop signal 2 Error (5-Bit)");
                    -> error_detected;
                    -> uart_stop_error2;
                  end
        end
        else
*/
 
// wait another half cycle for tx_done signal
                @(negedge test_rx_clk);
        read <= 0;
        -> uart_read_done;
 
        if (expected_data != data)
        begin
                $display ("Error! Data return is %h, expecting %h", data, expected_data);
                -> error_detected;
        end
        else
                $display ("(%m) Data match  %h", expected_data);
 
        $display ("... Read Data from UART done cnt :%d...",rx_count +1);
   end
join
 
end
 
endtask
 
 
////////////////////////////////////////////////////////////////////////////////
task write_char;
input [7:0] data;
 
integer i;
reg parity;     // 0: odd parity, 1: even parity
 
begin
        parity <=  #1 0;
 
// start cycle
        @(posedge test_tx_clk)
         begin
                sin <= #1 0;
                write <= #1 1;
         end
 
// data cycle
        begin
           for (i = 0; i < data_bit_number; i = i + 1)
           begin
                @(posedge test_tx_clk)
                    sin <= #1 data[i];
                parity <= parity ^ data[i];
           end
        end
 
// parity cycle
        if (control_setup.parity_en)
        begin
                @(posedge test_tx_clk)
                        sin <= #1
//                              control_setup.stick_parity ? ~control_setup.even_odd_parity : 
                                control_setup.even_odd_parity ? parity : !parity;
        end
 
// stop cycle 1
        @(posedge test_tx_clk)
                sin <= #1 stop_err_check ? 0 : 1;
 
// stop cycle 2
        @(posedge test_tx_clk);
                sin <= #1 1;
        if (data_bit_number == 5)
                @(negedge test_tx_clk);
        else if (control_setup.stop_bit_number)
                @(posedge test_tx_clk);
 
        write <= #1 0;
        $display ("... Write data %h to UART done cnt : %d ...\n", data,tx_count+1);
        -> uart_write_done;
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////////
task control_setup;
input     [1:0] data_bit_set;
input           stop_bit_number;
input           parity_en;
input           even_odd_parity;
input           stick_parity;
input    [15:0] maxtime;
input    [15:0] divisor;
input           fifo_enable;
 
begin
        data_bit_number = data_bit_set + 5;
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////////
task report_status;
output  [15:0] rx_nu;
output  [15:0] tx_nu;
begin
        $display ("-------------------- Reporting Configuration --------------------");
        $display ("     Data bit number setting is : %0d", data_bit_number);
        $display ("     Stop bit number setting is : %0d", control_setup.stop_bit_number + 1);
        $display ("     Divisor of Uart clock   is : %0d", control_setup.divisor);
        if (control_setup.parity_en)
        $display ("     Parity is enable");
        else
        $display ("     Parity is disable");
 
        if (control_setup.even_odd_parity)
        $display ("     Even parity setting");
        else
        $display ("     Odd parity setting");
 
/*
        if (control_setup.stick_parity)
        $display ("     Parity stick bit is on");
        else
        $display ("     Parity stick bit is off");
*/
 
        if (control_setup.fifo_enable)
        $display ("     FIFO mode is enable");
        else
        $display ("     FIFO mode is disable");
 
        $display ("-----------------------------------------------------------------");
 
        $display ("-------------------- Reporting Status --------------------\n");
        $display ("     Number of character received is : %d", rx_count);
        $display ("     Number of character sent     is : %d", tx_count);
        $display ("     Number of parity error rxd   is : %d", par_err_count);
        $display ("     Number of stop1  error rxd   is : %d", stop_err1_cnt);
        $display ("     Number of stop2  error rxd   is : %d", stop_err2_cnt);
        $display ("     Number of timeout error      is : %d", timeout_err_cnt);
        $display ("     Number of error              is : %d", err_cnt);
        $display ("-----------------------------------------------------------------");
 
        rx_nu = rx_count;
        tx_nu = tx_count;
end
endtask
 
 
////////////////////////////////////////////////////////////////////////////////
endmodule

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Subversion Repositories usb2uart

[/] [usb2uart/] [trunk/] [verify/] [agents/] [uart/] [uart_agent.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	3	dinesha
2			`timescale 1ns/1ps
3
4			`module uart_agent (`
5			`test_clk,`
6			`sin,`
7			`sout)`
8			`;`
9
10			`input test_clk;`
11			`output sin;`
12
13			`input sout;`
14
15			`event uart_read_done, uart_write_done;`
16			`event error_detected,uart_parity_error, uart_stop_error1, uart_stop_error2;`
17			`event uart_timeout_error;`
18			`event abort;`
19
20			`reg [15:0] rx_count;`
21			`reg [15:0] tx_count;`
22			`reg [15:0] par_err_count;`
23			`reg [15:0] stop_err1_cnt;`
24			`reg [15:0] stop_err2_cnt;`
25			`reg [15:0] timeout_err_cnt;`
26			`reg [15:0] err_cnt;`
27
28			`reg sin, read, write;`
29			`wire test_rx_clk;`
30			`reg test_tx_clk;`
31			`reg stop_err_check;`
32			`reg [15:0] cnt_16x;`
33
34			`integer timeout_count;`
35			`integer data_bit_number;`
36			`reg [2:0] clk_count;`
37
38			`reg error_ind; // 1 indicate error`
39
40			`initial`
41			`begin`
42			`sin = 1'b1;`
43			`test_tx_clk = 0;`
44			`clk_count = 0;`
45			`stop_err_check = 0;`
46			`error_ind = 0;`
47			`cnt_16x = 0;`
48			`end`
49
50			`always @(posedge test_clk)`
51			`begin`
52			`if (clk_count == 3'h0) // Divide by 16 Counter`
53			`begin`
54			`if(cnt_16x >= control_setup.divisor) begin`
55			`test_tx_clk = ~test_tx_clk;`
56			`cnt_16x = 0;`
57			`end else begin`
58			`cnt_16x = cnt_16x+1;`
59			`end`
60			`end`
61			`clk_count = clk_count + 1;`
62			`end`
63			`assign test_rx_clk = ~test_tx_clk;`
64
65			`always @(posedge test_clk) begin`
66			`timeout_count = timeout_count + 1;`
67			`if (timeout_count == (control_setup.maxtime * 16))`
68			`-> abort;`
69			`end`
70
71			`always @uart_read_done`
72			`rx_count = rx_count + 1;`
73
74			`always @uart_write_done`
75			`tx_count = tx_count + 1;`
76
77			`always @uart_parity_error begin`
78			`error_ind = 1;`
79			`par_err_count = par_err_count + 1;`
80			`end`
81
82			`always @uart_stop_error1 begin`
83			`error_ind = 1;`
84			`stop_err1_cnt = stop_err1_cnt + 1;`
85			`end`
86
87			`always @uart_stop_error2 begin`
88			`error_ind = 1;`
89			`stop_err2_cnt = stop_err2_cnt + 1;`
90			`end`
91
92			`always @uart_timeout_error begin`
93			`error_ind = 1;`
94			`timeout_err_cnt = timeout_err_cnt + 1;`
95			`end`
96
97
98			`always @error_detected begin`
99			`error_ind = 1;`
100			`err_cnt = err_cnt + 1;`
101			`end`
102
103
104			`////////////////////////////////////////////////////////////////////////////////`
105			`task uart_init;`
106			`begin`
107			`read = 0;`
108			`write = 0;`
109			`tx_count = 0;`
110			`rx_count = 0;`
111			`stop_err_check = 0;`
112			`par_err_count = 0;`
113			`stop_err1_cnt = 0;`
114			`stop_err2_cnt = 0;`
115			`timeout_err_cnt = 0;`
116			`err_cnt = 0;`
117
118			`end`
119			`endtask`
120
121
122			`////////////////////////////////////////////////////////////////////////////////`
123			`task read_char_chk;`
124			`input expected_data;`
125
126			`integer i;`
127			`reg [7:0] expected_data;`
128			`reg [7:0] data;`
129			`reg parity;`
130
131			`begin`
132			`data <= 8'h0;`
133			`parity <= 1;`
134			`timeout_count = 0;`
135
136			`fork`
137			`begin : loop_1`
138			`@(abort)`
139			`$display (">>>>> Exceed time limit, uart no responce.\n");`
140			`->uart_timeout_error;`
141			`disable loop_2;`
142			`end`
143
144			`begin : loop_2`
145
146			`// start cycle`
147			`@(negedge sout)`
148			`disable loop_1;`
149			`read <= 1;`
150
151			`// data cycle`
152			`@(posedge test_rx_clk);`
153			`for (i = 0; i < data_bit_number; i = i + 1)`
154			`begin`
155			`@(posedge test_rx_clk)`
156			`data[i] <= sout;`
157			`parity <= parity ^ sout;`
158			`end`
159
160			`// parity cycle`
161			`if(control_setup.parity_en)`
162			`begin`
163			`@(posedge test_rx_clk);`
164			`if ((control_setup.even_odd_parity && (sout == parity)) \|\|`
165			`(!control_setup.even_odd_parity && (sout != parity)))`
166			`// \|\| (control_setup.stick_parity && (sout == control_setup.even_odd_parity)))`
167			`begin`
168			`$display (">>>>> Parity Error");`
169			`-> error_detected;`
170			`-> uart_parity_error;`
171			`end`
172			`end`
173
174			`// stop cycle 1`
175			`@(posedge test_rx_clk);`
176			`if (!sout)`
177			`begin`
178			`$display (">>>>> Stop signal 1 Error");`
179			`-> error_detected;`
180			`-> uart_stop_error1;`
181			`end`
182
183			`// stop cycle 2`
184			`if (control_setup.stop_bit_number)`
185			`begin`
186			`@(posedge test_rx_clk); // stop cycle 2`
187			`if (!sout)`
188			`begin`
189			`$display (">>>>> Stop signal 2 Error");`
190			`-> error_detected;`
191			`-> uart_stop_error2;`
192			`end`
193			`end`
194
195			`/* Who Cares`
196			`// the stop bits transmitted is one and a half if it is 5-bit`
197			`if (data_bit_number == 5)`
198			`begin`
199			`@(posedge test_rx_clk); // stop cycle for 5-bit/per char`
200			`if (!sout)`
201			`begin`
202			`$display (">>>>> Stop signal 2 Error (5-Bit)");`
203			`-> error_detected;`
204			`-> uart_stop_error2;`
205			`end`
206			`end`
207			`else`
208			`*/`
209
210			`// wait another half cycle for tx_done signal`
211			`@(negedge test_rx_clk);`
212			`read <= 0;`
213			`-> uart_read_done;`
214
215			`if (expected_data != data)`
216			`begin`
217			`$display ("Error! Data return is %h, expecting %h", data, expected_data);`
218			`-> error_detected;`
219			`end`
220			`else`
221			`$display ("(%m) Data match %h", expected_data);`
222
223			`$display ("... Read Data from UART done cnt :%d...",rx_count +1);`
224			`end`
225			`join`
226
227			`end`
228
229			`endtask`
230
231
232			`////////////////////////////////////////////////////////////////////////////////`
233			`task write_char;`
234			`input [7:0] data;`
235
236			`integer i;`
237			`reg parity; // 0: odd parity, 1: even parity`
238
239			`begin`
240			`parity <= #1 0;`
241
242			`// start cycle`
243			`@(posedge test_tx_clk)`
244			`begin`
245			`sin <= #1 0;`
246			`write <= #1 1;`
247			`end`
248
249			`// data cycle`
250			`begin`
251			`for (i = 0; i < data_bit_number; i = i + 1)`
252			`begin`
253			`@(posedge test_tx_clk)`
254			`sin <= #1 data[i];`
255			`parity <= parity ^ data[i];`
256			`end`
257			`end`
258
259			`// parity cycle`
260			`if (control_setup.parity_en)`
261			`begin`
262			`@(posedge test_tx_clk)`
263			`sin <= #1`
264			`// control_setup.stick_parity ? ~control_setup.even_odd_parity :`
265			`control_setup.even_odd_parity ? parity : !parity;`
266			`end`
267
268			`// stop cycle 1`
269			`@(posedge test_tx_clk)`
270			`sin <= #1 stop_err_check ? 0 : 1;`
271
272			`// stop cycle 2`
273			`@(posedge test_tx_clk);`
274			`sin <= #1 1;`
275			`if (data_bit_number == 5)`
276			`@(negedge test_tx_clk);`
277			`else if (control_setup.stop_bit_number)`
278			`@(posedge test_tx_clk);`
279
280			`write <= #1 0;`
281			`$display ("... Write data %h to UART done cnt : %d ...\n", data,tx_count+1);`
282			`-> uart_write_done;`
283			`end`
284			`endtask`
285
286
287			`////////////////////////////////////////////////////////////////////////////////`
288			`task control_setup;`
289			`input [1:0] data_bit_set;`
290			`input stop_bit_number;`
291			`input parity_en;`
292			`input even_odd_parity;`
293			`input stick_parity;`
294			`input [15:0] maxtime;`
295			`input [15:0] divisor;`
296			`input fifo_enable;`
297
298			`begin`
299			`data_bit_number = data_bit_set + 5;`
300			`end`
301			`endtask`
302
303
304			`////////////////////////////////////////////////////////////////////////////////`
305			`task report_status;`
306			`output [15:0] rx_nu;`
307			`output [15:0] tx_nu;`
308			`begin`
309			`$display ("-------------------- Reporting Configuration --------------------");`
310			`$display (" Data bit number setting is : %0d", data_bit_number);`
311			`$display (" Stop bit number setting is : %0d", control_setup.stop_bit_number + 1);`
312			`$display (" Divisor of Uart clock is : %0d", control_setup.divisor);`
313			`if (control_setup.parity_en)`
314			`$display (" Parity is enable");`
315			`else`
316			`$display (" Parity is disable");`
317
318			`if (control_setup.even_odd_parity)`
319			`$display (" Even parity setting");`
320			`else`
321			`$display (" Odd parity setting");`
322
323			`/*`
324			`if (control_setup.stick_parity)`
325			`$display (" Parity stick bit is on");`
326			`else`
327			`$display (" Parity stick bit is off");`
328			`*/`
329
330			`if (control_setup.fifo_enable)`
331			`$display (" FIFO mode is enable");`
332			`else`
333			`$display (" FIFO mode is disable");`
334
335			`$display ("-----------------------------------------------------------------");`
336
337			`$display ("-------------------- Reporting Status --------------------\n");`
338			`$display (" Number of character received is : %d", rx_count);`
339			`$display (" Number of character sent is : %d", tx_count);`
340			`$display (" Number of parity error rxd is : %d", par_err_count);`
341			`$display (" Number of stop1 error rxd is : %d", stop_err1_cnt);`
342			`$display (" Number of stop2 error rxd is : %d", stop_err2_cnt);`
343			`$display (" Number of timeout error is : %d", timeout_err_cnt);`
344			`$display (" Number of error is : %d", err_cnt);`
345			`$display ("-----------------------------------------------------------------");`
346
347			`rx_nu = rx_count;`
348			`tx_nu = tx_count;`
349			`end`
350			`endtask`
351
352
353			`////////////////////////////////////////////////////////////////////////////////`
354			`endmodule`