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[/] [usb_fpga_1_2/] [trunk/] [include/] [ztex.h] - Blame information for rev 9

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/*!
   ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
   Copyright (C) 2009-2011 ZTEX GmbH.
   http://www.ztex.de
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License version 3 as
   published by the Free Software Foundation.
 
   This program is distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
   General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, see http://www.gnu.org/licenses/.
!*/
 
/*
   Puts everything together.
*/
 
#ifndef[ZTEX_H]
#define[ZTEX_H]
 
#define[INIT_CMDS;][]
 
#ifneq[PRODUCT_IS][UFM-1_15]
#define[UFM_1_15X_DETECTION_ENABLED][0]
#endif
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
__xdata BYTE is_ufm_1_15x;
#endif
 
/* *********************************************************************
   ***** include the basic functions ***********************************
   ********************************************************************* */
#include[ztex-utils.h]
 
/* *********************************************************************
   ***** EEPROM support and some I2C helper functions ******************
   ********************************************************************* */
#ifneq[EEPROM_DISABLED][1]
 
#ifneq[EEPROM_MAC_DISABLED][1]
#ifeq[PRODUCT_IS][UFM-1_15]
#define[MAC_EEPROM_ENABLED]
#endif // PRODUCT_IS=UFM-1_15
#ifeq[PRODUCT_IS][UFM-1_15Y]
#define[MAC_EEPROM_ENABLED]
#endif // PRODUCT_IS=UFM-1_15Y
#endif // EEPROM_MAC_DISABLED
 
#include[ztex-eeprom.h]
 
#endif // EEPROM_DISABLED
 
 
/* *********************************************************************
   ***** Flash memory support ******************************************
   ********************************************************************* */
#ifeq[FLASH_ENABLED][1]
 
#ifeq[PRODUCT_IS][UFM-1_1]
#define[MMC_PORT][E]
#define[MMC_BIT_CS][7]
#define[MMC_BIT_DI][6]
#define[MMC_BIT_DO][4]
#define[MMC_BIT_CLK][5]
#include[ztex-flash1.h]
 
#elifeq[PRODUCT_IS][UFM-1_2]
#define[MMC_PORT][E]
#define[MMC_BIT_CS][7]
#define[MMC_BIT_DI][6]
#define[MMC_BIT_DO][4]
#define[MMC_BIT_CLK][5]
#include[ztex-flash1.h]
 
#elifeq[PRODUCT_IS][UM-1_0]
#define[MMC_PORT][C]
#define[MMC_BIT_CS][7]
#define[MMC_BIT_DI][6]
#define[MMC_BIT_DO][4]
#define[MMC_BIT_CLK][5]
#include[ztex-flash1.h]
 
#elifeq[PRODUCT_IS][UM-1_0]
#define[MMC_PORT][C]
#define[MMC_BIT_CS][7]
#define[MMC_BIT_DI][6]
#define[MMC_BIT_DO][4]
#define[MMC_BIT_CLK][5]
#include[ztex-flash1.h]
 
#elifeq[PRODUCT_IS][UFM-1_10]
#define[MMC_PORT][A]
#define[MMC__PORT_DO][D]
#define[MMC_BIT_DO][0]
#define[MMC_BIT_CS][5]
#define[MMC_BIT_DI][6]
#define[MMC_BIT_CLK][7]
#include[ztex-flash1.h]
 
#elifeq[PRODUCT_IS][UFM-1_11]
#define[MMC_PORT][C]
#define[MMC__PORT_DO][D]
#define[MMC_BIT_DO][0]
#define[MMC_BIT_CS][5]
#define[MMC_BIT_DI][7]
#define[MMC_BIT_CLK][6]
#include[ztex-flash1.h]
 
#elifeq[PRODUCT_IS][UFM-1_15]
#define[MMC_PORT][C]
#define[MMC_BIT_DO][4]
#define[MMC_BIT_CS][5]
#define[MMC_BIT_DI][7]
#define[MMC_BIT_CLK][6]
#include[ztex-flash1.h]
 
#elifeq[PRODUCT_IS][UXM-1_0]
#define[MMC_PORT][C]
#define[MMC_BIT_CS][7]
#define[MMC_BIT_DI][6]
#define[MMC_BIT_DO][4]
#define[MMC_BIT_CLK][5]
#include[ztex-flash1.h]
 
#else
#warning[Flash memory access is not supported by this product]
#define[FLASH_ENABLED][0]
#endif
#endif
 
/* *********************************************************************
   ***** FPGA configuration support ************************************
   ********************************************************************* */
#ifeq[PRODUCT_IS][UFM-1_0]
#include[ztex-fpga1.h]
#elifeq[PRODUCT_IS][UFM-1_1]
#include[ztex-fpga1.h]
#elifeq[PRODUCT_IS][UFM-1_2]
#include[ztex-fpga1.h]
#elifeq[PRODUCT_IS][UFM-1_10]
#include[ztex-fpga2.h]
#elifeq[PRODUCT_IS][UFM-1_11]
#include[ztex-fpga3.h]
#elifeq[PRODUCT_IS][UFM-1_15]
#include[ztex-fpga4.h]
#elifeq[PRODUCT_IS][UFM-1_15Y]
#include[ztex-fpga5.h]
#endif
 
 
/* *********************************************************************
   ***** DEBUG helper functions ****************************************
   ********************************************************************* */
#ifeq[DEBUG_ENABLED][1]
#include[ztex-debug.h]
#endif
 
 
/* *********************************************************************
   ***** XMEGA support *************************************************
   ********************************************************************* */
#ifneq[XMEGA_DISABLED][1]
 
#ifeq[PRODUCT_IS][UXM-1_0]
#define[PDI_PORT][A]
#define[PDI_BIT_CLK][0]
#define[PDI_BIT_DATA][1]
#include[ztex-xmega.h]
#endif
 
#ifeq[EXP_1_10_ENABLED][1]
#ifneq[PRODUCT_IS][UFM-1_0]
#elifneq[PRODUCT_IS][UFM-1_1]
#elifneq[PRODUCT_IS][UFM-1_2]
#elifneq[PRODUCT_IS][UFM-1_10]
#elifneq[PRODUCT_IS][UFM-1_11]
#elifneq[PRODUCT_IS][UFM-1_15]
#warning[ZTEX Experimental Board 1.10 is not supported by this product.]
#endif
#define[PDI_PORT][E]
#define[PDI_BIT_CLK][5]
#define[PDI_BIT_DATA][4]
#include[ztex-xmega.h]
#endif
 
#endif
 
/* *********************************************************************
   ***** define the descriptors and the interrupt routines *************
   ********************************************************************* */
#include[ztex-descriptors.h]
#include[ztex-isr.h]
 
 
#ifdef[@CAPABILITY_MAC_EEPROM;]
/* *********************************************************************
   ***** mac_eeprom_init ***********************************************
   ********************************************************************* */
void mac_eeprom_init ( ) {
    BYTE b,c,d;
    __xdata BYTE buf[5];
    __code char hexdigits[] = "0123456789ABCDEF";
 
    for (b=0; b<10; b++) {       // abort if SN != "0000000000"
        if ( SN_STRING[b] != 48 )
            return;
    }
 
    mac_eeprom_read ( buf, 0xfb, 5 );   // read the last 5 MAC digits
 
    c=0;
    for (b=0; b<5; b++) {        // convert to MAC to SN string
        d = buf[b];
        SN_STRING[c] = hexdigits[d>>4];
        c++;
        SN_STRING[c] = hexdigits[d & 15];
        c++;
    }
}
#endif
 
 
/* *********************************************************************
   ***** init_USB ******************************************************
   ********************************************************************* */
#define[EPXCFG(][);][    EP$0CFG = 
#ifeq[EP$0_DIR][IN]
        bmBIT7 | bmBIT6
#elifeq[EP$0_DIR][OUT]
        bmBIT7
#else
 
#endif
#ifeq[EP$0_TYPE][BULK]
        | bmBIT5
#elifeq[EP$0_TYPE][ISO]
        | bmBIT4
#elifeq[EP$0_TYPE][INT]
        | bmBIT5 | bmBIT4
#endif
#ifeq[EP$0_SIZE][1024]
        | bmBIT3
#endif
#ifeq[EP$0_BUFFERS][2]
        | bmBIT1
#elifeq[EP$0_BUFFERS][3]
        | bmBIT1 | bmBIT0
#endif  
        ;
        SYNCDELAY;
]
 
#define[EP1XCFG(][);][#ifeq[EP$0_TYPE][BULK]
        EP$0CFG = bmBIT7 | bmBIT5;
#elifeq[EP$0_TYPE][ISO]
        EP$0CFG = bmBIT7 | bmBIT4;
#elifeq[EP$0_TYPE][INT]
        EP$0CFG = bmBIT7 | bmBIT5 | bmBIT4;
#else   
        EP$0CFG = 0;
#endif
        SYNCDELAY;
]
 
 
void init_USB ()
{
    USBCS |= bmBIT3;
 
    CPUCS = bmBIT4 | bmBIT1;
    wait(2);
    CKCON &= ~7;
 
#ifeq[PRODUCT_IS][UFM-1_0]
    IOA1 = 1;
    OEA |= bmBIT1;
#elifeq[PRODUCT_IS][UFM-1_1]
    IOA1 = 1;
    OEA |= bmBIT1;
#elifeq[PRODUCT_IS][UFM-1_2]
    IOA1 = 1;
    OEA |= bmBIT1;
#elifeq[PRODUCT_IS][UFM-1_10]
    IOA1 = 1;
    OEA |= bmBIT1;
#elifeq[PRODUCT_IS][UFM-1_11]
    IOA1 = 1;
    OEA |= bmBIT1;
#elifeq[PRODUCT_IS][UFM-1_15]
    IOA1 = 1;
    OEA |= bmBIT1;
#elifeq[PRODUCT_IS][UFM-1_15Y]
    init_fpga();
#endif
 
    INIT_CMDS;
 
    EA = 0;
    EUSB = 0;
 
    ENABLE_AVUSB;
 
    INIT_INTERRUPT_VECTOR(INTVEC_SUDAV, SUDAV_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_SOF, SOF_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_SUTOK, SUTOK_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_SUSPEND, SUSP_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_USBRESET, URES_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_HISPEED, HSGRANT_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_EP0ACK, EP0ACK_ISR);
 
    INIT_INTERRUPT_VECTOR(INTVEC_EP0IN, EP0IN_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_EP0OUT, EP0OUT_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_EP1IN, EP1IN_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_EP1OUT, EP1OUT_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_EP2, EP2_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_EP4, EP4_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_EP6, EP6_ISR);
    INIT_INTERRUPT_VECTOR(INTVEC_EP8, EP8_ISR);
 
    EXIF &= ~bmBIT4;
    USBIRQ = 0x7f;
    USBIE |= 0x7f;
    EPIRQ = 0xff;
    EPIE = 0xff;
 
    EUSB = 1;
    EA = 1;
 
    EP1XCFG(1IN);
    EP1XCFG(1OUT);
    EPXCFG(2);
    EPXCFG(4);
    EPXCFG(6);
    EPXCFG(8);
 
#ifeq[UFM_1_15X_DETECTION_ENABLED][1]
    OEA &= ~bmBIT3;
    if ( IOA3 ) {
        is_ufm_1_15x = 0;
    } else {
        is_ufm_1_15x = 1;
//      INTERFACE_CAPABILITIES[0] &= ~32;
    }
#endif    
 
#ifeq[FLASH_ENABLED][1]
    flash_init();
#endif
#ifeq[FLASH_BITSTREAM_ENABLED][1]
    fpga_configure_from_flash_init();
#endif
#ifeq[DEBUG_ENABLED][1]
    debug_init();
#endif
#ifeq[XMEGA_ENABLED][1]
    xmega_init();
#endif
#ifdef[@CAPABILITY_MAC_EEPROM;]
    mac_eeprom_init();
#endif
 
    USBCS |= bmBIT7 | bmBIT1;
    wait(10);
//    wait(250);
    USBCS &= ~bmBIT3;
}
 
 
#endif   /* ZTEX_H */

Line No.	Rev	Author	Line
1	2	ZTEX	`/*!`
2	8	ZTEX	`ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers`
3			`Copyright (C) 2009-2011 ZTEX GmbH.`
4	2	ZTEX	`http://www.ztex.de`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License version 3 as`
8			`published by the Free Software Foundation.`
9
10			`This program is distributed in the hope that it will be useful, but`
11			`WITHOUT ANY WARRANTY; without even the implied warranty of`
12			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU`
13			`General Public License for more details.`
14
15			`You should have received a copy of the GNU General Public License`
16			`along with this program; if not, see http://www.gnu.org/licenses/.`
17			`!*/`
18
19			`/*`
20	3	ZTEX	`Puts everything together.`
21	2	ZTEX	`*/`
22
23			`#ifndef[ZTEX_H]`
24			`#define[ZTEX_H]`
25
26	4	ZTEX	`#define[INIT_CMDS;][]`
27
28	9	ZTEX	`#ifneq[PRODUCT_IS][UFM-1_15]`
29			`#define[UFM_1_15X_DETECTION_ENABLED][0]`
30			`#endif`
31
32			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
33			`__xdata BYTE is_ufm_1_15x;`
34			`#endif`
35
36	2	ZTEX	`/* *********************************************************************`
37			`*** include the basic functions *********************************`
38			`********************************************************************* */`
39			`#include[ztex-utils.h]`
40
41			`/* *********************************************************************`
42	5	ZTEX	`*** EEPROM support and some I2C helper functions ****************`
43	3	ZTEX	`********************************************************************* */`
44			`#ifneq[EEPROM_DISABLED][1]`
45	8	ZTEX
46			`#ifneq[EEPROM_MAC_DISABLED][1]`
47			`#ifeq[PRODUCT_IS][UFM-1_15]`
48			`#define[MAC_EEPROM_ENABLED]`
49			`#endif // PRODUCT_IS=UFM-1_15`
50	9	ZTEX	`#ifeq[PRODUCT_IS][UFM-1_15Y]`
51			`#define[MAC_EEPROM_ENABLED]`
52			`#endif // PRODUCT_IS=UFM-1_15Y`
53	8	ZTEX	`#endif // EEPROM_MAC_DISABLED`
54
55	3	ZTEX	`#include[ztex-eeprom.h]`
56
57	8	ZTEX	`#endif // EEPROM_DISABLED`
58
59
60	3	ZTEX	`/* *********************************************************************`
61	2	ZTEX	`*** Flash memory support ****************************************`
62			`********************************************************************* */`
63			`#ifeq[FLASH_ENABLED][1]`
64	3	ZTEX
65	2	ZTEX	`#ifeq[PRODUCT_IS][UFM-1_1]`
66	3	ZTEX	`#define[MMC_PORT][E]`
67			`#define[MMC_BIT_CS][7]`
68			`#define[MMC_BIT_DI][6]`
69			`#define[MMC_BIT_DO][4]`
70			`#define[MMC_BIT_CLK][5]`
71	2	ZTEX	`#include[ztex-flash1.h]`
72	3	ZTEX
73	2	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_2]`
74	3	ZTEX	`#define[MMC_PORT][E]`
75			`#define[MMC_BIT_CS][7]`
76			`#define[MMC_BIT_DI][6]`
77			`#define[MMC_BIT_DO][4]`
78			`#define[MMC_BIT_CLK][5]`
79	2	ZTEX	`#include[ztex-flash1.h]`
80	3	ZTEX
81			`#elifeq[PRODUCT_IS][UM-1_0]`
82			`#define[MMC_PORT][C]`
83			`#define[MMC_BIT_CS][7]`
84			`#define[MMC_BIT_DI][6]`
85			`#define[MMC_BIT_DO][4]`
86			`#define[MMC_BIT_CLK][5]`
87			`#include[ztex-flash1.h]`
88
89	5	ZTEX	`#elifeq[PRODUCT_IS][UM-1_0]`
90			`#define[MMC_PORT][C]`
91			`#define[MMC_BIT_CS][7]`
92			`#define[MMC_BIT_DI][6]`
93			`#define[MMC_BIT_DO][4]`
94			`#define[MMC_BIT_CLK][5]`
95			`#include[ztex-flash1.h]`
96
97	4	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_10]`
98			`#define[MMC_PORT][A]`
99			`#define[MMC__PORT_DO][D]`
100			`#define[MMC_BIT_DO][0]`
101			`#define[MMC_BIT_CS][5]`
102			`#define[MMC_BIT_DI][6]`
103			`#define[MMC_BIT_CLK][7]`
104			`#include[ztex-flash1.h]`
105
106			`#elifeq[PRODUCT_IS][UFM-1_11]`
107	3	ZTEX	`#define[MMC_PORT][C]`
108	4	ZTEX	`#define[MMC__PORT_DO][D]`
109			`#define[MMC_BIT_DO][0]`
110			`#define[MMC_BIT_CS][5]`
111			`#define[MMC_BIT_DI][7]`
112	3	ZTEX	`#define[MMC_BIT_CLK][6]`
113			`#include[ztex-flash1.h]`
114
115	8	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_15]`
116			`#define[MMC_PORT][C]`
117			`#define[MMC_BIT_DO][4]`
118			`#define[MMC_BIT_CS][5]`
119			`#define[MMC_BIT_DI][7]`
120			`#define[MMC_BIT_CLK][6]`
121			`#include[ztex-flash1.h]`
122
123	5	ZTEX	`#elifeq[PRODUCT_IS][UXM-1_0]`
124			`#define[MMC_PORT][C]`
125			`#define[MMC_BIT_CS][7]`
126			`#define[MMC_BIT_DI][6]`
127			`#define[MMC_BIT_DO][4]`
128			`#define[MMC_BIT_CLK][5]`
129			`#include[ztex-flash1.h]`
130
131	2	ZTEX	`#else`
132	5	ZTEX	`#warning[Flash memory access is not supported by this product]`
133	2	ZTEX	`#define[FLASH_ENABLED][0]`
134			`#endif`
135			`#endif`
136
137			`/* *********************************************************************`
138			`*** FPGA configuration support **********************************`
139			`********************************************************************* */`
140			`#ifeq[PRODUCT_IS][UFM-1_0]`
141	4	ZTEX	`#include[ztex-fpga1.h]`
142	2	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_1]`
143	4	ZTEX	`#include[ztex-fpga1.h]`
144	2	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_2]`
145	4	ZTEX	`#include[ztex-fpga1.h]`
146			`#elifeq[PRODUCT_IS][UFM-1_10]`
147			`#include[ztex-fpga2.h]`
148			`#elifeq[PRODUCT_IS][UFM-1_11]`
149			`#include[ztex-fpga3.h]`
150	8	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_15]`
151			`#include[ztex-fpga4.h]`
152	9	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_15Y]`
153			`#include[ztex-fpga5.h]`
154	2	ZTEX	`#endif`
155
156	5	ZTEX
157	2	ZTEX	`/* *********************************************************************`
158	5	ZTEX	`*** DEBUG helper functions **************************************`
159			`********************************************************************* */`
160			`#ifeq[DEBUG_ENABLED][1]`
161			`#include[ztex-debug.h]`
162			`#endif`
163
164
165			`/* *********************************************************************`
166			`*** XMEGA support ***********************************************`
167			`********************************************************************* */`
168			`#ifneq[XMEGA_DISABLED][1]`
169	8	ZTEX
170	5	ZTEX	`#ifeq[PRODUCT_IS][UXM-1_0]`
171	8	ZTEX	`#define[PDI_PORT][A]`
172			`#define[PDI_BIT_CLK][0]`
173			`#define[PDI_BIT_DATA][1]`
174	5	ZTEX	`#include[ztex-xmega.h]`
175			`#endif`
176	8	ZTEX
177			`#ifeq[EXP_1_10_ENABLED][1]`
178			`#ifneq[PRODUCT_IS][UFM-1_0]`
179			`#elifneq[PRODUCT_IS][UFM-1_1]`
180			`#elifneq[PRODUCT_IS][UFM-1_2]`
181			`#elifneq[PRODUCT_IS][UFM-1_10]`
182			`#elifneq[PRODUCT_IS][UFM-1_11]`
183			`#elifneq[PRODUCT_IS][UFM-1_15]`
184			`#warning[ZTEX Experimental Board 1.10 is not supported by this product.]`
185	5	ZTEX	`#endif`
186	8	ZTEX	`#define[PDI_PORT][E]`
187			`#define[PDI_BIT_CLK][5]`
188			`#define[PDI_BIT_DATA][4]`
189			`#include[ztex-xmega.h]`
190			`#endif`
191	5	ZTEX
192	8	ZTEX	`#endif`
193	5	ZTEX
194			`/* *********************************************************************`
195	2	ZTEX	`*** define the descriptors and the interrupt routines ***********`
196			`********************************************************************* */`
197			`#include[ztex-descriptors.h]`
198			`#include[ztex-isr.h]`
199
200
201	8	ZTEX	`#ifdef[@CAPABILITY_MAC_EEPROM;]`
202	2	ZTEX	`/* *********************************************************************`
203	8	ZTEX	`*** mac_eeprom_init *********************************************`
204			`********************************************************************* */`
205			`void mac_eeprom_init ( ) {`
206			`BYTE b,c,d;`
207	9	ZTEX	`__xdata BYTE buf[5];`
208	8	ZTEX	`__code char hexdigits[] = "0123456789ABCDEF";`
209
210			`for (b=0; b<10; b++) { // abort if SN != "0000000000"`
211	9	ZTEX	`if ( SN_STRING[b] != 48 )`
212	8	ZTEX	`return;`
213			`}`
214
215			`mac_eeprom_read ( buf, 0xfb, 5 ); // read the last 5 MAC digits`
216
217			`c=0;`
218			`for (b=0; b<5; b++) { // convert to MAC to SN string`
219			`d = buf[b];`
220			`SN_STRING[c] = hexdigits[d>>4];`
221			`c++;`
222			`SN_STRING[c] = hexdigits[d & 15];`
223			`c++;`
224			`}`
225			`}`
226			`#endif`
227
228
229			`/* *********************************************************************`
230	2	ZTEX	`*** init_USB ****************************************************`
231			`********************************************************************* */`
232			`#define[EPXCFG(][);][ EP$0CFG =`
233			`#ifeq[EP$0_DIR][IN]`
234			`bmBIT7 \| bmBIT6`
235			`#elifeq[EP$0_DIR][OUT]`
236			`bmBIT7`
237			`#else`
238
239			`#endif`
240			`#ifeq[EP$0_TYPE][BULK]`
241			`\| bmBIT5`
242			`#elifeq[EP$0_TYPE][ISO]`
243			`\| bmBIT4`
244			`#elifeq[EP$0_TYPE][INT]`
245			`\| bmBIT5 \| bmBIT4`
246			`#endif`
247			`#ifeq[EP$0_SIZE][1024]`
248			`\| bmBIT3`
249			`#endif`
250			`#ifeq[EP$0_BUFFERS][2]`
251			`\| bmBIT1`
252			`#elifeq[EP$0_BUFFERS][3]`
253			`\| bmBIT1 \| bmBIT0`
254			`#endif`
255			`;`
256			`SYNCDELAY;`
257			`]`
258
259			`#define[EP1XCFG(][);][#ifeq[EP$0_TYPE][BULK]`
260			`EP$0CFG = bmBIT7 \| bmBIT5;`
261			`#elifeq[EP$0_TYPE][ISO]`
262			`EP$0CFG = bmBIT7 \| bmBIT4;`
263			`#elifeq[EP$0_TYPE][INT]`
264			`EP$0CFG = bmBIT7 \| bmBIT5 \| bmBIT4;`
265			`#else`
266			`EP$0CFG = 0;`
267			`#endif`
268			`SYNCDELAY;`
269			`]`
270
271	9	ZTEX
272	2	ZTEX	`void init_USB ()`
273			`{`
274	9	ZTEX	`USBCS \|= bmBIT3;`
275	3	ZTEX
276	2	ZTEX	`CPUCS = bmBIT4 \| bmBIT1;`
277	8	ZTEX	`wait(2);`
278	2	ZTEX	`CKCON &= ~7;`
279
280	3	ZTEX	`#ifeq[PRODUCT_IS][UFM-1_0]`
281	2	ZTEX	`IOA1 = 1;`
282			`OEA \|= bmBIT1;`
283	3	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_1]`
284			`IOA1 = 1;`
285			`OEA \|= bmBIT1;`
286			`#elifeq[PRODUCT_IS][UFM-1_2]`
287			`IOA1 = 1;`
288			`OEA \|= bmBIT1;`
289	4	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_10]`
290			`IOA1 = 1;`
291			`OEA \|= bmBIT1;`
292			`#elifeq[PRODUCT_IS][UFM-1_11]`
293			`IOA1 = 1;`
294			`OEA \|= bmBIT1;`
295	8	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_15]`
296			`IOA1 = 1;`
297			`OEA \|= bmBIT1;`
298	9	ZTEX	`#elifeq[PRODUCT_IS][UFM-1_15Y]`
299			`init_fpga();`
300	3	ZTEX	`#endif`
301	4	ZTEX
302			`INIT_CMDS;`
303
304	2	ZTEX	`EA = 0;`
305	3	ZTEX	`EUSB = 0;`
306	2	ZTEX
307			`ENABLE_AVUSB;`
308
309			`INIT_INTERRUPT_VECTOR(INTVEC_SUDAV, SUDAV_ISR);`
310			`INIT_INTERRUPT_VECTOR(INTVEC_SOF, SOF_ISR);`
311			`INIT_INTERRUPT_VECTOR(INTVEC_SUTOK, SUTOK_ISR);`
312			`INIT_INTERRUPT_VECTOR(INTVEC_SUSPEND, SUSP_ISR);`
313			`INIT_INTERRUPT_VECTOR(INTVEC_USBRESET, URES_ISR);`
314			`INIT_INTERRUPT_VECTOR(INTVEC_HISPEED, HSGRANT_ISR);`
315			`INIT_INTERRUPT_VECTOR(INTVEC_EP0ACK, EP0ACK_ISR);`
316
317			`INIT_INTERRUPT_VECTOR(INTVEC_EP0IN, EP0IN_ISR);`
318			`INIT_INTERRUPT_VECTOR(INTVEC_EP0OUT, EP0OUT_ISR);`
319			`INIT_INTERRUPT_VECTOR(INTVEC_EP1IN, EP1IN_ISR);`
320			`INIT_INTERRUPT_VECTOR(INTVEC_EP1OUT, EP1OUT_ISR);`
321			`INIT_INTERRUPT_VECTOR(INTVEC_EP2, EP2_ISR);`
322			`INIT_INTERRUPT_VECTOR(INTVEC_EP4, EP4_ISR);`
323			`INIT_INTERRUPT_VECTOR(INTVEC_EP6, EP6_ISR);`
324			`INIT_INTERRUPT_VECTOR(INTVEC_EP8, EP8_ISR);`
325
326			`EXIF &= ~bmBIT4;`
327			`USBIRQ = 0x7f;`
328			`USBIE \|= 0x7f;`
329			`EPIRQ = 0xff;`
330			`EPIE = 0xff;`
331
332			`EUSB = 1;`
333			`EA = 1;`
334
335			`EP1XCFG(1IN);`
336			`EP1XCFG(1OUT);`
337			`EPXCFG(2);`
338			`EPXCFG(4);`
339			`EPXCFG(6);`
340			`EPXCFG(8);`
341	9	ZTEX
342			`#ifeq[UFM_1_15X_DETECTION_ENABLED][1]`
343			`OEA &= ~bmBIT3;`
344			`if ( IOA3 ) {`
345			`is_ufm_1_15x = 0;`
346			`} else {`
347			`is_ufm_1_15x = 1;`
348			`// INTERFACE_CAPABILITIES[0] &= ~32;`
349			`}`
350			`#endif`
351	3	ZTEX
352			`#ifeq[FLASH_ENABLED][1]`
353			`flash_init();`
354			`#endif`
355			`#ifeq[FLASH_BITSTREAM_ENABLED][1]`
356			`fpga_configure_from_flash_init();`
357			`#endif`
358	5	ZTEX	`#ifeq[DEBUG_ENABLED][1]`
359			`debug_init();`
360			`#endif`
361			`#ifeq[XMEGA_ENABLED][1]`
362	8	ZTEX	`xmega_init();`
363	5	ZTEX	`#endif`
364	8	ZTEX	`#ifdef[@CAPABILITY_MAC_EEPROM;]`
365			`mac_eeprom_init();`
366			`#endif`
367	3	ZTEX
368			`USBCS \|= bmBIT7 \| bmBIT1;`
369	8	ZTEX	`wait(10);`
370			`// wait(250);`
371	9	ZTEX	`USBCS &= ~bmBIT3;`
372	2	ZTEX	`}`
373
374	3	ZTEX
375	2	ZTEX	`#endif /* ZTEX_H */`

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[/] [usb_fpga_1_2/] [trunk/] [include/] [ztex.h] - Blame information for rev 9