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[/] [usb_fpga_2_13/] [trunk/] [examples/] [usb-fpga-2.13/] [2.13c/] [memfifo/] [Readme] - Blame information for rev 2

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memfifo
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This example demonstrates:
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* High speed EZ-USB -> FPGA transfers using the Slave FIFO interface
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* High speed FPGA -> EZ-USB transfers using the Slave FIFO interface
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* Usage of the DDR3 SDRAM
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All SDRAM is used to build a large FIFO. Input of this FIFO is either
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USB Endpoint 6 through the Slave FIFO interface of EZ-USB or a test
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pattern generator with variable data rate. Data is written to PC
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using Endpoint 2.
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The host software writes the data (in EP6 input mode), reads it back
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and verifies it. Several tests are performed in order to test flow
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control, data rates, etc.
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The HDL sources contain 3 modules:
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1. ezusb_io.v: Implements the EZ-USB Slave FIFO interface for both
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    directions. It also includes an scheduler (required if both
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    directions are used at the same time) and short packets (PKTEND).
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2. dram_fifo.v: Implements a huge FIFO  from all SDRAM.
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3. memfifo.c: The top level module glues everything together.
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ezusb_io and dram_fifo are re-usable for many other projects.
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PIN PA7 is the reset input.
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Data source source is  is selected by PA1:PA0:
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PA1:PA0  Source
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----------------------
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0:0      USB Endpoint 6 (EZ-USB Slave FIFO interface)
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0:1      48 MByte/s test pattern generator
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1:0      12 MByte/s test pattern generator
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1:1      Test pattern generator, speed selected by SW8 of the debug board
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Debug Board (not required)
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--------------------------
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LED1: Debug/status output, see SW10
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LED2-3: Fill level of the DRAM FIFO
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SW8: Speed of test pattern generator in source mode 11
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     on: 12 MByte/s
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     off: 48 MByte/s
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SW10 on: status signals from dram_fifo module
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     off:status signals from top level module

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