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Subversion Repositories usb_fpga_2_13

[/] [usb_fpga_2_13/] [trunk/] [include/] [ztex-fpga2.h] - Blame information for rev 2

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1 2 ZTEX 
/*!
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   ZTEX Firmware Kit for EZ-USB FX2 Microcontrollers
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   Copyright (C) 2009-2014 ZTEX GmbH.
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   http://www.ztex.de
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   This program is free software; you can redistribute it and/or modify
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   it under the terms of the GNU General Public License version 3 as
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   published by the Free Software Foundation.
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   This program is distributed in the hope that it will be useful, but
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   WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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   General Public License for more details.
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   You should have received a copy of the GNU General Public License
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   along with this program; if not, see http://www.gnu.org/licenses/.
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!*/
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/*
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    FPGA support for ZTEX USB FPGA Modules 1.10
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*/
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#ifndef[ZTEX_FPGA_H]
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#define[ZTEX_FPGA_H]
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#define[@CAPABILITY_FPGA;]
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__xdata BYTE fpga_checksum;         // checksum
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__xdata DWORD fpga_bytes;           // transfered bytes
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__xdata BYTE fpga_init_b;           // init_b state (should be 222 after configuration)
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__xdata BYTE fpga_flash_result;     // result of automatic fpga configuarion from Flash
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/* *********************************************************************
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   ***** reset_fpga ****************************************************
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   ********************************************************************* */
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static void reset_fpga_int (BYTE mode) {                // reset FPGA
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    unsigned short k;
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    IFCONFIG = bmBIT7;
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    SYNCDELAY;
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    PORTACFG = 0;
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    PORTCCFG = 0;
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    OEA = (OEA & 0xe0) | bmBIT1 | bmBIT3 | bmBIT4;
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    IOA = (IOA & 0xe0) | bmBIT4;
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    wait(10);
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    OEC = bmBIT4 | bmBIT6 | bmBIT7;
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    IOC = mode;
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    IOA = (IOA & 0xe0) | bmBIT1;                                // ready for configuration
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    k=0;
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    while (!IOA0 && k<65535)
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        k++;
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    fpga_init_b = IOA0 ? 200 : 100;
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    fpga_bytes = 0;
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    fpga_checksum = 0;
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}
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static void reset_fpga () {
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    reset_fpga_int(bmBIT4);
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}
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static void reset_fpga_flash () {
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    reset_fpga_int(bmBIT4 | bmBIT6);
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}
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/* *********************************************************************
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   ***** init_fpga_configuration ***************************************
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   ********************************************************************* */
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static void init_fpga_configuration () {
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    {
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        PRE_FPGA_RESET
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    }
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    reset_fpga();                       // reset FPGA
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}
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/* *********************************************************************
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   ***** post_fpga_confog **********************************************
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   ********************************************************************* */
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static void post_fpga_config () {
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    POST_FPGA_CONFIG
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}
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/* *********************************************************************
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   ***** finish_fpga_configuration *************************************
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   ********************************************************************* */
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static void finish_fpga_configuration () {
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    WORD w;
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    fpga_init_b += IOA0 ? 20 : 10;
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    for ( w=0; w<65535; w++ ) {
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        IOA3 = 1; IOA3 = 0;
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    }
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    IOA3 = 1; IOA3 = 0;
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    IOA3 = 1; IOA3 = 0;
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    IOA3 = 1; IOA3 = 0;
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    IOA3 = 1; IOA3 = 0;
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    IOA4 = 1;
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    IOA3 = 1; IOA3 = 0;
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    OEC = 0;
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    IOA3 = 1; IOA3 = 0;
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    IOA3 = 1; IOA3 = 0;
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    IOA3 = 1; IOA3 = 0;
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    OEA = OEA & 0xe0;
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    fpga_init_b += IOA0 ? 2 : 1;
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    if ( IOA1 )  {
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        IOA1 = 1;
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        post_fpga_config();
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    }
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    IOA1 = 1;
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    OEA |= bmBIT1;
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}
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/* *********************************************************************
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   ***** EP0 vendor request 0x30 ***************************************
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   ********************************************************************* */
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ADD_EP0_VENDOR_REQUEST((0x30,,          // get FPGA state
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    MEM_COPY1(fpga_checksum,EP0BUF+1,7);
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    OEA &= ~bmBIT1;
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    if ( IOA1 )  {
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        EP0BUF[0] = 0;                    // FPGA configured
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        IOA1 = 1;
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        OEA |= bmBIT1;
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    }
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    else {
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        EP0BUF[0] = 1;                   // FPGA unconfigured
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        reset_fpga();                   // prepare FPGA for configuration
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    }
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    EP0BUF[8] = 1;                      // bit order for bitstream in Flash memory: swapped
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    EP0BCH = 0;
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    EP0BCL = 9;
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,,));;
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/* *********************************************************************
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   ***** EP0 vendor command 0x31 ***************************************
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   ********************************************************************* */
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ADD_EP0_VENDOR_COMMAND((0x31,,init_fpga_configuration();,,));;  // reset FPGA
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/* *********************************************************************
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   ***** EP0 vendor command 0x32 ***************************************
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   ********************************************************************* */
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void fpga_send_ep0() {
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    BYTE oOED;
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    oOED = OED;
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    OED = 255;
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    fpga_bytes += ep0_payload_transfer;
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    __asm
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        mov     dptr,#_EP0BCL
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        movx    a,@dptr
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        jz      010000$
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        mov     r2,a
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        mov     _AUTOPTRL1,#(_EP0BUF)
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        mov     _AUTOPTRH1,#(_EP0BUF >> 8)
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        mov     _AUTOPTRSETUP,#0x07
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        mov     dptr,#_fpga_checksum
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        movx    a,@dptr
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        mov     r1,a
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        mov     dptr,#_XAUTODAT1
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010001$:
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        movx    a,@dptr
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        mov     _IOD,a
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        setb    _IOA3
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        add     a,r1
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        mov     r1,a
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        clr     _IOA3
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        djnz    r2, 010001$
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        mov     dptr,#_fpga_checksum
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        mov     a,r1
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        movx    @dptr,a
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010000$:
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        __endasm;
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    OED = oOED;
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    if ( EP0BCL<64 ) {
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        finish_fpga_configuration();
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    }
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}
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ADD_EP0_VENDOR_COMMAND((0x32,,          // send FPGA configuration data
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,,
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    fpga_send_ep0();
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));;
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#ifeq[FLASH_BITSTREAM_ENABLED][1]
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#ifeq[FLASH_ENABLED][1]
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/* *********************************************************************
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   ***** fpga_send_bitstream_from_flash ********************************
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   ********************************************************************* */
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void fpga_send_bitstream_from_flash (WORD size) {
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        size;                   // this avoids stupid warnings
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__asm
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        push    _OED
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        mov     _OED,#0
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        mov     r5,dpl          // = size
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        mov     r6,dph
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        // fpga_bytes+=size
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        mov     dptr,#_fpga_bytes
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        movx    a,@dptr
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        mov     r1,a
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        inc     dptr
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        movx    a,@dptr
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        mov     r2,a
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        inc     dptr
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        movx    a,@dptr
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        mov     r3,a
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        inc     dptr
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        movx    a,@dptr
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        mov     r4,a
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        mov     dptr,#_fpga_bytes
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        mov     a,r5
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        add     a,r1
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        movx    @dptr,a
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        mov     a,r6
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        addc    a,r2
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        inc     dptr
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        movx    @dptr,a
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        mov     a,#0
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        addc    a,r3
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        inc     dptr
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        movx    @dptr,a
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        mov     a,#0
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        addc    a,r4
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        inc     dptr
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        movx    @dptr,a
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010003$:
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        cjne    r5,#0x00,010002$
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        cjne    r6,#0x00,010002$
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        pop     _OED
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        ret
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010002$:
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        mov     _IOA,#(bmBIT1 | bmBIT6 | bmBIT3 | bmBIT7)
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        mov     _IOA,#(bmBIT1 | bmBIT6)
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        mov     _IOA,#(bmBIT1 | bmBIT6 | bmBIT3 | bmBIT7)
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        mov     _IOA,#(bmBIT1 | bmBIT6)
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        mov     _IOA,#(bmBIT1 | bmBIT6 | bmBIT3 | bmBIT7)
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        mov     _IOA,#(bmBIT1 | bmBIT6)
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        mov     _IOA,#(bmBIT1 | bmBIT6 | bmBIT3 | bmBIT7)
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        mov     _IOA,#(bmBIT1 | bmBIT6)
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        mov     _IOA,#(bmBIT1 | bmBIT6 | bmBIT3 | bmBIT7)
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        mov     _IOA,#(bmBIT1 | bmBIT6)
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        mov     _IOA,#(bmBIT1 | bmBIT6 | bmBIT3 | bmBIT7)
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        mov     _IOA,#(bmBIT1 | bmBIT6)
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        mov     _IOA,#(bmBIT1 | bmBIT6 | bmBIT3 | bmBIT7)
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        mov     _IOA,#(bmBIT1 | bmBIT6)
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        mov     _IOA,#(bmBIT1 | bmBIT6 | bmBIT3 | bmBIT7)
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        mov     _IOA,#(bmBIT1 | bmBIT6)
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263 
        dec     r5
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        cjne    r5,#0xff,010003$
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        dec     r6
266 
        sjmp    010003$
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__endasm;
268 
}
269 
 
270 
#include[ztex-fpga-flash1.h]
271 
 
272 
#else
273 
#warning[Flash interface is not enabled but required for FPGA configuration using a bitstream from Flash meomory]
274 
#define[FLASH_BITSTREAM_ENABLED][0]
275 
#endif
276 
#endif
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278 
#endif  /*ZTEX_FPGA_H*/

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