URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [_xmsgs/] [cg.xmsgs] - Blame information for rev 2

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Generating IP...

 
The selected IP does not support an ASY schematic symbol.

 
Finished generation of ASY schematic symbol.

 
The chosen IP does not support an SYM schematic symbol.

 
WARNING: de_DE.ISO-8859-1 is not supported as a language.  Using usenglish.
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/infrastructure.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
   mp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v" into library
   work

 
Finished FLIST file generation.

 

 

Line No.	Rev	Author	Line
1	2	ZTEX
2
7
8			`Generating IP...`
9
10
11			`The selected IP does not support an ASY schematic symbol.`
12
13
14			`Finished generation of ASY schematic symbol.`
15
16
17			`The chosen IP does not support an SYM schematic symbol.`
18
19
20			`WARNING: de_DE.ISO-8859-1 is not supported as a language. Using usenglish.`
21			`INFO:HDLCompiler:1845 - Analyzing Verilog file`
22			`"/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t`
23			`mp/_cg/mem0/user_design/rtl/infrastructure.v" into library work`
24			`INFO:ProjectMgmt - Parsing design hierarchy completed successfully.`
25			`Adding /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v -view all -origin_type created`
26			`INFO:HDLCompiler:1845 - Analyzing Verilog file`
27			`"/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t`
28			`mp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v" into library`
29			`work`
30
31
32			`Finished FLIST file generation.`
33
34
35
36

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Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [_xmsgs/] [cg.xmsgs] - Blame information for rev 2