URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [coregen.cgp] - Blame information for rev 2

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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx16
SET devicefamily = spartan6
SET flowvendor = Other
SET package = ftg256
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false

Line No.	Rev	Author	Line
1	2	ZTEX	`SET busformat = BusFormatAngleBracketNotRipped`
2			`SET designentry = Verilog`
3			`SET device = xc6slx16`
4			`SET devicefamily = spartan6`
5			`SET flowvendor = Other`
6			`SET package = ftg256`
7			`SET speedgrade = -2`
8			`SET verilogsim = true`
9			`SET vhdlsim = false`

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Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [coregen.cgp] - Blame information for rev 2