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URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [coregen.log] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ZTEX 
INFO:sim:172 - Generating IP...
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Applying current project options...
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Finished applying current project options.
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Customizing IP...
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Finished Customizing.
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Resolving generic values...
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Finished resolving generic values.
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INFO:sim:993 - The selected IP does not support an ASY schematic symbol.
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INFO:sim:949 - Finished generation of ASY schematic symbol.
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WARNING:sim - The chosen IP does not support an SYM schematic symbol.
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Generating metadata file...
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Generating ISE project...
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XCO file found: mem0.xco
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XMDF file found: mem0_xmdf.tcl
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Adding
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/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
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cg/mem0/user_design/rtl/infrastructure.v -view all -origin_type created
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WARNING:coreutil - WARNING: de_DE.ISO-8859-1 is not supported as a language.
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   Using usenglish.
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   INFO:HDLCompiler:1845 - Analyzing Verilog file
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   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
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      mp/_cg/mem0/user_design/rtl/infrastructure.v" into library work
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   INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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   Adding
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   /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tm
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   p/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v -view all
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   -origin_type created
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   INFO:HDLCompiler:1845 - Analyzing Verilog file
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   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
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      mp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_controller.v" into
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   library
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      work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
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cg/mem0/user_design/rtl/mcb_controller/iodrp_mcb_controller.v -view all
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-origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
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   mp/_cg/mem0/user_design/rtl/mcb_controller/iodrp_mcb_controller.v" into
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   library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
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cg/mem0/user_design/rtl/mcb_controller/mcb_raw_wrapper.v -view all -origin_type
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created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
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   mp/_cg/mem0/user_design/rtl/mcb_controller/mcb_raw_wrapper.v" into library
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   work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
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cg/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration.v -view all
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-origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
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   mp/_cg/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration.v" into
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   library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
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cg/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v -view all
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-origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
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   mp/_cg/mem0/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v" into
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   library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
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cg/mem0/user_design/rtl/mcb_controller/mcb_ui_top.v -view all -origin_type
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created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
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   mp/_cg/mem0/user_design/rtl/mcb_controller/mcb_ui_top.v" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
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cg/mem0/user_design/rtl/mem0.v -view all -origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
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   mp/_cg/mem0/user_design/rtl/mem0.v" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
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cg/mem0/user_design/rtl/memc_wrapper.v -view all -origin_type created
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INFO:HDLCompiler:1845 - Analyzing Verilog file
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   "/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/t
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   mp/_cg/mem0/user_design/rtl/memc_wrapper.v" into library work
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INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
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Adding
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/drv_s2/usb-fpga/ztex/examples/usb-fpga-2.04/2.04b/memfifo/fpga/ipcore_dir/tmp/_
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cg/mem0/user_design/par/mem0.ucf -view all -origin_type created
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INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
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   Please set the new top explicitly by running the "project set top" command.
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   To re-calculate the new top automatically, set the "Auto Implementation Top"
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   property to true.
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Top level has been set to "/mem0"
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Generating FLIST file...
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INFO:sim:948 - Finished FLIST file generation.
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Generating README file...
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Launching README viewer...
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Moving files to output directory...
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Finished moving files to output directory
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Wrote CGP file for project 'mem0'.

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