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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [edit_mem0.tcl] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ZTEX 
##
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## Core Generator Run Script, generator for Project Navigator edit command
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##
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proc findRtfPath { relativePath } {
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   set xilenv ""
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   if { [info exists ::env(XILINX) ] } {
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      if { [info exists ::env(MYXILINX)] } {
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         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
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      } else {
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         set xilenv $::env(XILINX)
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      }
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   }
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   foreach path [ split $xilenv $::xilinx::path_sep ] {
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      set fullPath [ file join $path $relativePath ]
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      if { [ file exists $fullPath ] } {
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         return $fullPath
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      }
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   }
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   return ""
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}
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source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
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set result [ run_cg_edit "mem0" xc6slx16-2ftg256 Verilog ]
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if { $result == 0 } {
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   puts "Core Generator edit command completed successfully."
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} elseif { $result == 1 } {
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   puts "Core Generator edit command failed."
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} elseif { $result == 3 || $result == 4 } {
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   # convert 'version check' result to real return range, bypassing any messages.
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   set result [ expr $result - 3 ]
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} else {
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   puts "Core Generator edit cancelled."
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}
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exit $result

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