Subversion Repositories usb_fpga_2_14

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#

# Xilinx Core Generator version 11.2

# Date: Fri Jun 12 05:42:56 2009

#

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#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

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#

# BEGIN Project Options

SET addpads = False

SET asysymbol = False

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = False

SET designentry = verilog

SET device = xc6slx16

SET devicefamily = spartan6

SET flowvendor = Foundation_ISE

SET formalverification = False

SET foundationsym = False

SET implementationfiletype = Ngc

SET package = ftg256

SET removerpms = False

SET simulationfiles = Structural

SET speedgrade = -2

SET verilogsim = False

SET vhdlsim = False

# END Project Options

# BEGIN Select

SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.03.a

# END Select

# BEGIN Parameters

CSET asynchronous_input_port_width=8

CSET asynchronous_output_port_width=7

CSET component_name=vio

CSET enable_asynchronous_input_port=false

CSET enable_asynchronous_output_port=true

CSET enable_synchronous_input_port=false

CSET enable_synchronous_output_port=false

CSET invert_clock_input=false

CSET synchronous_input_port_width=8

CSET synchronous_output_port_width=8

# END Parameters

GENERATE

# CRC: 66fe39ed