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//*****************************************************************************
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// (c) Copyright 2009-10 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Application : MIG
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// \ \ Filename : memc_tb_top.v
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// / / Date Last Modified : $Date: 2011/06/02 07:17:10 $
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// /___/ /\ Date Created : Fri Mar 26 2010
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// \ \ / \
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// \___\/\___\
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//
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//Device : Spartan-6
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//Design Name : DDR/DDR2/DDR3/LPDDR
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//Purpose : This is top level module for test bench, which instantiates
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// init_mem_pattern_ctr and mcb_traffic_gen modules for each user
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// logical port.
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//Reference :
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//Revision History :
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//*****************************************************************************
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`timescale 1ps/1ps
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module memc_tb_top #(
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parameter C_SIMULATION = "FALSE",
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parameter C_NUM_DQ_PINS = 4,
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parameter C_MEM_BURST_LEN = 8,
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parameter C_MEM_NUM_COL_BITS = 11,
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parameter C_SMALL_DEVICE = "FALSE",
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parameter C_PORT_ENABLE = 6'b111111,
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parameter C_P0_MASK_SIZE = 4,
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parameter C_P0_DATA_PORT_SIZE = 32,
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parameter C_P1_MASK_SIZE = 4,
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parameter C_P1_DATA_PORT_SIZE = 32,
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parameter C_P0_PORT_MODE = "BI_MODE",
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parameter C_P1_PORT_MODE = "BI_MODE",
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parameter C_P2_PORT_MODE = "RD_MODE",
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parameter C_P3_PORT_MODE = "RD_MODE",
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parameter C_P4_PORT_MODE = "RD_MODE",
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parameter C_P5_PORT_MODE = "RD_MODE",
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parameter C_p0_BEGIN_ADDRESS = 32'h00000100,
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parameter C_p0_DATA_MODE = 4'b0010,
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parameter C_p0_END_ADDRESS = 32'h000002ff,
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parameter C_p0_PRBS_EADDR_MASK_POS = 32'hfffffc00,
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parameter C_p0_PRBS_SADDR_MASK_POS = 32'h00000100,
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parameter C_p1_BEGIN_ADDRESS = 32'h00000300,
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parameter C_p1_DATA_MODE = 4'b0010,
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parameter C_p1_END_ADDRESS = 32'h000004ff,
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parameter C_p1_PRBS_EADDR_MASK_POS = 32'hfffff800,
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parameter C_p1_PRBS_SADDR_MASK_POS = 32'h00000300,
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parameter C_p2_BEGIN_ADDRESS = 32'h00000100,
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parameter C_p2_DATA_MODE = 4'b0010,
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parameter C_p2_END_ADDRESS = 32'h000002ff,
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parameter C_p2_PRBS_EADDR_MASK_POS = 32'hfffffc00,
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parameter C_p2_PRBS_SADDR_MASK_POS = 32'h00000100,
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parameter C_p3_BEGIN_ADDRESS = 32'h00000100,
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parameter C_p3_DATA_MODE = 4'b0010,
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parameter C_p3_END_ADDRESS = 32'h000002ff,
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parameter C_p3_PRBS_EADDR_MASK_POS = 32'hfffffc00,
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parameter C_p3_PRBS_SADDR_MASK_POS = 32'h00000100,
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parameter C_p4_BEGIN_ADDRESS = 32'h00000100,
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parameter C_p4_DATA_MODE = 4'b0010,
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parameter C_p4_END_ADDRESS = 32'h000002ff,
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parameter C_p4_PRBS_EADDR_MASK_POS = 32'hfffffc00,
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parameter C_p4_PRBS_SADDR_MASK_POS = 32'h00000100,
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parameter C_p5_BEGIN_ADDRESS = 32'h00000100,
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parameter C_p5_DATA_MODE = 4'b0010,
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parameter C_p5_END_ADDRESS = 32'h000002ff,
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parameter C_p5_PRBS_EADDR_MASK_POS = 32'hfffffc00,
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parameter C_p5_PRBS_SADDR_MASK_POS = 32'h00000100
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)
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(
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input clk0,
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input rst0,
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input calib_done,
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/////////////////////////////////////////////////////////////////////////////
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// MCB INTERFACE
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/////////////////////////////////////////////////////////////////////////////
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// The following port declarations depicts that all the memory controller ports
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// are connected to the test bench top. However, a traffic generator can be
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// connected to the corresponding port only if the port is enabled, whose
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// information can be obtained from the parameter C_PORT_ENABLE. The following
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// list describes the active ports in each port configuration.
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//
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// Config 1: "B32_B32_X32_X32_X32_X32"
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// User port 0 --> 32 bit, User port 1 --> 32 bit
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// User port 2 --> 32 bit, User port 3 --> 32 bit
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// User port 4 --> 32 bit, User port 5 --> 32 bit
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// Config 2: "B32_B32_B32_B32"
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// User port 0 --> 32 bit
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// User port 1 --> 32 bit
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// User port 2 --> 32 bit
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// User port 3 --> 32 bit
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// Config 3: "B64_B32_B3"
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// User port 0 --> 64 bit
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// User port 1 --> 32 bit
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// User port 2 --> 32 bit
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// Config 4: "B64_B64"
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// User port 0 --> 64 bit
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// User port 1 --> 64 bit
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// Config 5 "B128"
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// User port 0 --> 128 bit
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// User Port-0 command interface will be active only when the port is enabled in
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// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
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output p0_mcb_cmd_en,
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output [2:0] p0_mcb_cmd_instr,
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output [5:0] p0_mcb_cmd_bl,
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output [29:0] p0_mcb_cmd_addr,
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input p0_mcb_cmd_full,
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// User Port-0 data write interface will be active only when the port is enabled in
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// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
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output p0_mcb_wr_en,
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output [C_P0_MASK_SIZE - 1:0] p0_mcb_wr_mask,
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output [C_P0_DATA_PORT_SIZE - 1:0] p0_mcb_wr_data,
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input p0_mcb_wr_full,
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input [6:0] p0_mcb_wr_fifo_counts,
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// User Port-0 data read interface will be active only when the port is enabled in
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// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
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output p0_mcb_rd_en,
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input [C_P0_DATA_PORT_SIZE - 1:0] p0_mcb_rd_data,
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input p0_mcb_rd_empty,
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input [6:0] p0_mcb_rd_fifo_counts,
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// User Port-1 command interface will be active only when the port is enabled in
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// the port configurations Config-1, Config-2, Config-3 and Config-4
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output p1_mcb_cmd_en,
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output [2:0] p1_mcb_cmd_instr,
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output [5:0] p1_mcb_cmd_bl,
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output [29:0] p1_mcb_cmd_addr,
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input p1_mcb_cmd_full,
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// User Port-1 data write interface will be active only when the port is enabled in
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// the port configurations Config-1, Config-2, Config-3 and Config-4
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output p1_mcb_wr_en,
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output [C_P1_MASK_SIZE - 1:0] p1_mcb_wr_mask,
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output [C_P1_DATA_PORT_SIZE - 1:0] p1_mcb_wr_data,
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input p1_mcb_wr_full,
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input [6:0] p1_mcb_wr_fifo_counts,
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// User Port-1 data read interface will be active only when the port is enabled in
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// the port configurations Config-1, Config-2, Config-3 and Config-4
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output p1_mcb_rd_en,
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input [C_P1_DATA_PORT_SIZE - 1:0] p1_mcb_rd_data,
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input p1_mcb_rd_empty,
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input [6:0] p1_mcb_rd_fifo_counts,
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// User Port-2 command interface will be active only when the port is enabled in
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// the port configurations Config-1, Config-2 and Config-3
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output p2_mcb_cmd_en,
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output [2:0] p2_mcb_cmd_instr,
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output [5:0] p2_mcb_cmd_bl,
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output [29:0] p2_mcb_cmd_addr,
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input p2_mcb_cmd_full,
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// User Port-2 data write interface will be active only when the port is enabled in
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// the port configurations Config-1 write direction, Config-2 and Config-3
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output p2_mcb_wr_en,
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output [3:0] p2_mcb_wr_mask,
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output [31:0] p2_mcb_wr_data,
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input p2_mcb_wr_full,
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input [6:0] p2_mcb_wr_fifo_counts,
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// User Port-2 data read interface will be active only when the port is enabled in
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// the port configurations Config-1 read direction, Config-2 and Config-3
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output p2_mcb_rd_en,
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input [31:0] p2_mcb_rd_data,
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input p2_mcb_rd_empty,
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input [6:0] p2_mcb_rd_fifo_counts,
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// User Port-3 command interface will be active only when the port is enabled in
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// the port configurations Config-1 and Config-2
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output p3_mcb_cmd_en,
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output [2:0] p3_mcb_cmd_instr,
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output [5:0] p3_mcb_cmd_bl,
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output [29:0] p3_mcb_cmd_addr,
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input p3_mcb_cmd_full,
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// User Port-3 data write interface will be active only when the port is enabled in
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// the port configurations Config-1 write direction and Config-2
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output p3_mcb_wr_en,
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output [3:0] p3_mcb_wr_mask,
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output [31:0] p3_mcb_wr_data,
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input p3_mcb_wr_full,
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input [6:0] p3_mcb_wr_fifo_counts,
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// User Port-3 data read interface will be active only when the port is enabled in
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// the port configurations Config-1 read direction and Config-2
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output p3_mcb_rd_en,
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input [31:0] p3_mcb_rd_data,
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input p3_mcb_rd_empty,
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input [6:0] p3_mcb_rd_fifo_counts,
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// User Port-4 command interface will be active only when the port is enabled in
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// the port configuration Config-1
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output p4_mcb_cmd_en,
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output [2:0] p4_mcb_cmd_instr,
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output [5:0] p4_mcb_cmd_bl,
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output [29:0] p4_mcb_cmd_addr,
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input p4_mcb_cmd_full,
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// User Port-4 data write interface will be active only when the port is enabled in
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// the port configuration Config-1 write direction
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output p4_mcb_wr_en,
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output [3:0] p4_mcb_wr_mask,
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output [31:0] p4_mcb_wr_data,
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input p4_mcb_wr_full,
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input [6:0] p4_mcb_wr_fifo_counts,
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// User Port-4 data read interface will be active only when the port is enabled in
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// the port configuration Config-1 read direction
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output p4_mcb_rd_en,
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input [31:0] p4_mcb_rd_data,
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input p4_mcb_rd_empty,
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input [6:0] p4_mcb_rd_fifo_counts,
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// User Port-5 command interface will be active only when the port is enabled in
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// the port configuration Config-1
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output p5_mcb_cmd_en,
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output [2:0] p5_mcb_cmd_instr,
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output [5:0] p5_mcb_cmd_bl,
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output [29:0] p5_mcb_cmd_addr,
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input p5_mcb_cmd_full,
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// User Port-5 data write interface will be active only when the port is enabled in
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// the port configuration Config-1 write direction
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output p5_mcb_wr_en,
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output [3:0] p5_mcb_wr_mask,
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output [31:0] p5_mcb_wr_data,
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input p5_mcb_wr_full,
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input [6:0] p5_mcb_wr_fifo_counts,
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// User Port-5 data read interface will be active only when the port is enabled in
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// the port configuration Config-1 read direction
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output p5_mcb_rd_en,
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input [31:0] p5_mcb_rd_data,
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input p5_mcb_rd_empty,
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input [6:0] p5_mcb_rd_fifo_counts,
|
| 292 |
|
|
|
| 293 |
|
|
// Signal declarations that can be connected to vio module
|
| 294 |
|
|
input vio_modify_enable,
|
| 295 |
|
|
input [2:0] vio_data_mode_value,
|
| 296 |
|
|
input [2:0] vio_addr_mode_value,
|
| 297 |
|
|
|
| 298 |
|
|
// status feedback
|
| 299 |
|
|
output [31:0] cmp_data,
|
| 300 |
|
|
output cmp_data_valid,
|
| 301 |
|
|
output cmp_error,
|
| 302 |
|
|
output error, // asserted whenever the read back data is not correct.
|
| 303 |
|
|
output [64 + (2*C_P0_DATA_PORT_SIZE - 1):0] p0_error_status,
|
| 304 |
|
|
output [64 + (2*C_P1_DATA_PORT_SIZE - 1):0] p1_error_status,
|
| 305 |
|
|
output [127 : 0] p2_error_status,
|
| 306 |
|
|
output [127 : 0] p3_error_status,
|
| 307 |
|
|
output [127 : 0] p4_error_status,
|
| 308 |
|
|
output [127 : 0] p5_error_status
|
| 309 |
|
|
);
|
| 310 |
|
|
|
| 311 |
|
|
|
| 312 |
|
|
localparam P2_DWIDTH = 32;
|
| 313 |
|
|
localparam P3_DWIDTH = 32;
|
| 314 |
|
|
localparam P4_DWIDTH = 32;
|
| 315 |
|
|
localparam P5_DWIDTH = 32;
|
| 316 |
|
|
localparam FAMILY = "SPARTAN6";
|
| 317 |
|
|
localparam CMP_DATA_PIPE_STAGES = 0;
|
| 318 |
|
|
localparam DQ_ERROR_WIDTH = (C_NUM_DQ_PINS==4)? 1 : (C_NUM_DQ_PINS/8);
|
| 319 |
|
|
localparam TG_DATA_PATTERN = (C_SMALL_DEVICE == "FALSE") ? "DGEN_ALL" : "DGEN_ADDR";
|
| 320 |
|
|
|
| 321 |
|
|
localparam P2_PRBS_SADDR_MASK_POS = (C_P2_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_PRBS_SADDR_MASK_POS :
|
| 322 |
|
|
C_PORT_ENABLE[1] ? C_p1_PRBS_SADDR_MASK_POS :
|
| 323 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_PRBS_SADDR_MASK_POS :
|
| 324 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_PRBS_SADDR_MASK_POS :
|
| 325 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_PRBS_SADDR_MASK_POS :
|
| 326 |
|
|
C_p2_PRBS_SADDR_MASK_POS
|
| 327 |
|
|
: C_p2_PRBS_SADDR_MASK_POS;
|
| 328 |
|
|
localparam P2_PRBS_EADDR_MASK_POS = (C_P2_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_PRBS_EADDR_MASK_POS :
|
| 329 |
|
|
C_PORT_ENABLE[1] ? C_p1_PRBS_EADDR_MASK_POS :
|
| 330 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_PRBS_EADDR_MASK_POS :
|
| 331 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_PRBS_EADDR_MASK_POS :
|
| 332 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_PRBS_EADDR_MASK_POS :
|
| 333 |
|
|
C_p2_PRBS_EADDR_MASK_POS
|
| 334 |
|
|
: C_p2_PRBS_EADDR_MASK_POS;
|
| 335 |
|
|
localparam P2_BEGIN_ADDRESS = (C_P2_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_BEGIN_ADDRESS:
|
| 336 |
|
|
C_PORT_ENABLE[1] ? C_p1_BEGIN_ADDRESS:
|
| 337 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_BEGIN_ADDRESS :
|
| 338 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_BEGIN_ADDRESS :
|
| 339 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_BEGIN_ADDRESS :
|
| 340 |
|
|
C_p2_BEGIN_ADDRESS
|
| 341 |
|
|
: C_p2_BEGIN_ADDRESS;
|
| 342 |
|
|
localparam P2_END_ADDRESS = (C_P2_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_END_ADDRESS:
|
| 343 |
|
|
C_PORT_ENABLE[1] ? C_p1_END_ADDRESS:
|
| 344 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_END_ADDRESS :
|
| 345 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_END_ADDRESS :
|
| 346 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_END_ADDRESS :
|
| 347 |
|
|
C_p2_END_ADDRESS
|
| 348 |
|
|
: C_p2_END_ADDRESS;
|
| 349 |
|
|
localparam P2_DATA_MODE = (C_P2_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_DATA_MODE:
|
| 350 |
|
|
C_PORT_ENABLE[1] ? C_p1_DATA_MODE:
|
| 351 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_DATA_MODE :
|
| 352 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_DATA_MODE :
|
| 353 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_DATA_MODE :
|
| 354 |
|
|
C_p2_DATA_MODE
|
| 355 |
|
|
: C_p2_DATA_MODE;
|
| 356 |
|
|
|
| 357 |
|
|
|
| 358 |
|
|
localparam P3_PRBS_SADDR_MASK_POS = (C_P3_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_PRBS_SADDR_MASK_POS :
|
| 359 |
|
|
C_PORT_ENABLE[1] ? C_p1_PRBS_SADDR_MASK_POS :
|
| 360 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_PRBS_SADDR_MASK_POS :
|
| 361 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_PRBS_SADDR_MASK_POS :
|
| 362 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_PRBS_SADDR_MASK_POS :
|
| 363 |
|
|
C_p3_PRBS_SADDR_MASK_POS
|
| 364 |
|
|
: C_p3_PRBS_SADDR_MASK_POS;
|
| 365 |
|
|
localparam P3_PRBS_EADDR_MASK_POS = (C_P3_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_PRBS_EADDR_MASK_POS :
|
| 366 |
|
|
C_PORT_ENABLE[1] ? C_p1_PRBS_EADDR_MASK_POS :
|
| 367 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_PRBS_EADDR_MASK_POS :
|
| 368 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_PRBS_EADDR_MASK_POS :
|
| 369 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_PRBS_EADDR_MASK_POS :
|
| 370 |
|
|
C_p3_PRBS_EADDR_MASK_POS
|
| 371 |
|
|
: C_p3_PRBS_EADDR_MASK_POS;
|
| 372 |
|
|
localparam P3_BEGIN_ADDRESS = (C_P3_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_BEGIN_ADDRESS:
|
| 373 |
|
|
C_PORT_ENABLE[1] ? C_p1_BEGIN_ADDRESS:
|
| 374 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_BEGIN_ADDRESS :
|
| 375 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_BEGIN_ADDRESS :
|
| 376 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_BEGIN_ADDRESS :
|
| 377 |
|
|
C_p3_BEGIN_ADDRESS
|
| 378 |
|
|
: C_p3_BEGIN_ADDRESS;
|
| 379 |
|
|
localparam P3_END_ADDRESS = (C_P3_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_END_ADDRESS:
|
| 380 |
|
|
C_PORT_ENABLE[1] ? C_p1_END_ADDRESS:
|
| 381 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_END_ADDRESS :
|
| 382 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_END_ADDRESS :
|
| 383 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_END_ADDRESS :
|
| 384 |
|
|
C_p3_END_ADDRESS
|
| 385 |
|
|
: C_p3_END_ADDRESS;
|
| 386 |
|
|
localparam P3_DATA_MODE = (C_P3_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_DATA_MODE:
|
| 387 |
|
|
C_PORT_ENABLE[1] ? C_p1_DATA_MODE:
|
| 388 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_DATA_MODE :
|
| 389 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_DATA_MODE :
|
| 390 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_DATA_MODE :
|
| 391 |
|
|
C_p3_DATA_MODE
|
| 392 |
|
|
: C_p3_DATA_MODE;
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
localparam P4_PRBS_SADDR_MASK_POS = (C_P4_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_PRBS_SADDR_MASK_POS :
|
| 396 |
|
|
C_PORT_ENABLE[1] ? C_p1_PRBS_SADDR_MASK_POS :
|
| 397 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_PRBS_SADDR_MASK_POS :
|
| 398 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_PRBS_SADDR_MASK_POS :
|
| 399 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_PRBS_SADDR_MASK_POS :
|
| 400 |
|
|
C_p4_PRBS_SADDR_MASK_POS
|
| 401 |
|
|
: C_p4_PRBS_SADDR_MASK_POS;
|
| 402 |
|
|
localparam P4_PRBS_EADDR_MASK_POS = (C_P4_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_PRBS_EADDR_MASK_POS :
|
| 403 |
|
|
C_PORT_ENABLE[1] ? C_p1_PRBS_EADDR_MASK_POS :
|
| 404 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_PRBS_EADDR_MASK_POS :
|
| 405 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_PRBS_EADDR_MASK_POS :
|
| 406 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_PRBS_EADDR_MASK_POS :
|
| 407 |
|
|
C_p4_PRBS_EADDR_MASK_POS
|
| 408 |
|
|
: C_p4_PRBS_EADDR_MASK_POS;
|
| 409 |
|
|
localparam P4_BEGIN_ADDRESS = (C_P4_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_BEGIN_ADDRESS:
|
| 410 |
|
|
C_PORT_ENABLE[1] ? C_p1_BEGIN_ADDRESS:
|
| 411 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_BEGIN_ADDRESS :
|
| 412 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_BEGIN_ADDRESS :
|
| 413 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_BEGIN_ADDRESS :
|
| 414 |
|
|
C_p4_BEGIN_ADDRESS
|
| 415 |
|
|
: C_p4_BEGIN_ADDRESS;
|
| 416 |
|
|
localparam P4_END_ADDRESS = (C_P4_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_END_ADDRESS:
|
| 417 |
|
|
C_PORT_ENABLE[1] ? C_p1_END_ADDRESS:
|
| 418 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_END_ADDRESS :
|
| 419 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_END_ADDRESS :
|
| 420 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_END_ADDRESS :
|
| 421 |
|
|
C_p4_END_ADDRESS
|
| 422 |
|
|
: C_p4_END_ADDRESS;
|
| 423 |
|
|
localparam P4_DATA_MODE = (C_P4_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_DATA_MODE:
|
| 424 |
|
|
C_PORT_ENABLE[1] ? C_p1_DATA_MODE:
|
| 425 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_DATA_MODE :
|
| 426 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_DATA_MODE :
|
| 427 |
|
|
(C_PORT_ENABLE[5] && (C_P5_PORT_MODE == "WR_MODE")) ? C_p5_DATA_MODE :
|
| 428 |
|
|
C_p4_DATA_MODE
|
| 429 |
|
|
: C_p4_DATA_MODE;
|
| 430 |
|
|
|
| 431 |
|
|
|
| 432 |
|
|
localparam P5_PRBS_SADDR_MASK_POS = (C_P5_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_PRBS_SADDR_MASK_POS :
|
| 433 |
|
|
C_PORT_ENABLE[1] ? C_p1_PRBS_SADDR_MASK_POS :
|
| 434 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_PRBS_SADDR_MASK_POS :
|
| 435 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_PRBS_SADDR_MASK_POS :
|
| 436 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_PRBS_SADDR_MASK_POS :
|
| 437 |
|
|
C_p5_PRBS_SADDR_MASK_POS
|
| 438 |
|
|
: C_p5_PRBS_SADDR_MASK_POS;
|
| 439 |
|
|
localparam P5_PRBS_EADDR_MASK_POS = (C_P5_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_PRBS_EADDR_MASK_POS :
|
| 440 |
|
|
C_PORT_ENABLE[1] ? C_p1_PRBS_EADDR_MASK_POS :
|
| 441 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_PRBS_EADDR_MASK_POS :
|
| 442 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_PRBS_EADDR_MASK_POS :
|
| 443 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_PRBS_EADDR_MASK_POS :
|
| 444 |
|
|
C_p5_PRBS_EADDR_MASK_POS
|
| 445 |
|
|
: C_p5_PRBS_EADDR_MASK_POS;
|
| 446 |
|
|
localparam P5_BEGIN_ADDRESS = (C_P5_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_BEGIN_ADDRESS:
|
| 447 |
|
|
C_PORT_ENABLE[1] ? C_p1_BEGIN_ADDRESS:
|
| 448 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_BEGIN_ADDRESS :
|
| 449 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_BEGIN_ADDRESS :
|
| 450 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_BEGIN_ADDRESS :
|
| 451 |
|
|
C_p5_BEGIN_ADDRESS
|
| 452 |
|
|
: C_p5_BEGIN_ADDRESS;
|
| 453 |
|
|
localparam P5_END_ADDRESS = (C_P5_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_END_ADDRESS:
|
| 454 |
|
|
C_PORT_ENABLE[1] ? C_p1_END_ADDRESS:
|
| 455 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_END_ADDRESS :
|
| 456 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_END_ADDRESS :
|
| 457 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_END_ADDRESS :
|
| 458 |
|
|
C_p5_END_ADDRESS
|
| 459 |
|
|
: C_p5_END_ADDRESS;
|
| 460 |
|
|
localparam P5_DATA_MODE = (C_P5_PORT_MODE == "RD_MODE") ? C_PORT_ENABLE[0] ? C_p0_DATA_MODE:
|
| 461 |
|
|
C_PORT_ENABLE[1] ? C_p1_DATA_MODE:
|
| 462 |
|
|
(C_PORT_ENABLE[2] && (C_P2_PORT_MODE == "WR_MODE")) ? C_p2_DATA_MODE :
|
| 463 |
|
|
(C_PORT_ENABLE[3] && (C_P3_PORT_MODE == "WR_MODE")) ? C_p3_DATA_MODE :
|
| 464 |
|
|
(C_PORT_ENABLE[4] && (C_P4_PORT_MODE == "WR_MODE")) ? C_p4_DATA_MODE :
|
| 465 |
|
|
C_p5_DATA_MODE
|
| 466 |
|
|
: C_p5_DATA_MODE;
|
| 467 |
|
|
|
| 468 |
|
|
|
| 469 |
|
|
//p0 wire declarations
|
| 470 |
|
|
wire p0_tg_run_traffic;
|
| 471 |
|
|
wire [31:0] p0_tg_start_addr;
|
| 472 |
|
|
wire [31:0] p0_tg_end_addr;
|
| 473 |
|
|
wire [31:0] p0_tg_cmd_seed;
|
| 474 |
|
|
wire [31:0] p0_tg_data_seed;
|
| 475 |
|
|
wire p0_tg_load_seed;
|
| 476 |
|
|
wire [2:0] p0_tg_addr_mode;
|
| 477 |
|
|
wire [3:0] p0_tg_instr_mode;
|
| 478 |
|
|
wire [1:0] p0_tg_bl_mode;
|
| 479 |
|
|
wire [3:0] p0_tg_data_mode;
|
| 480 |
|
|
wire p0_tg_mode_load;
|
| 481 |
|
|
wire [5:0] p0_tg_fixed_bl;
|
| 482 |
|
|
wire [2:0] p0_tg_fixed_instr;
|
| 483 |
|
|
wire [31:0] p0_tg_fixed_addr;
|
| 484 |
|
|
wire p0_error;
|
| 485 |
|
|
wire p0_cmp_error;
|
| 486 |
|
|
wire [C_P0_DATA_PORT_SIZE-1 :0] p0_cmp_data;
|
| 487 |
|
|
wire p0_cmp_data_valid;
|
| 488 |
|
|
|
| 489 |
|
|
//p1 wire declarations
|
| 490 |
|
|
wire p1_tg_run_traffic;
|
| 491 |
|
|
wire [31:0] p1_tg_start_addr;
|
| 492 |
|
|
wire [31:0] p1_tg_end_addr;
|
| 493 |
|
|
wire [31:0] p1_tg_cmd_seed;
|
| 494 |
|
|
wire [31:0] p1_tg_data_seed;
|
| 495 |
|
|
wire p1_tg_load_seed;
|
| 496 |
|
|
wire [2:0] p1_tg_addr_mode;
|
| 497 |
|
|
wire [3:0] p1_tg_instr_mode;
|
| 498 |
|
|
wire [1:0] p1_tg_bl_mode;
|
| 499 |
|
|
wire [3:0] p1_tg_data_mode;
|
| 500 |
|
|
wire p1_tg_mode_load;
|
| 501 |
|
|
wire [5:0] p1_tg_fixed_bl;
|
| 502 |
|
|
wire [2:0] p1_tg_fixed_instr;
|
| 503 |
|
|
wire [31:0] p1_tg_fixed_addr;
|
| 504 |
|
|
wire p1_error;
|
| 505 |
|
|
wire p1_cmp_error;
|
| 506 |
|
|
wire [C_P1_DATA_PORT_SIZE-1 :0] p1_cmp_data;
|
| 507 |
|
|
wire p1_cmp_data_valid;
|
| 508 |
|
|
|
| 509 |
|
|
//p2 wire declarations
|
| 510 |
|
|
wire p2_tg_run_traffic;
|
| 511 |
|
|
wire [31:0] p2_tg_start_addr;
|
| 512 |
|
|
wire [31:0] p2_tg_end_addr;
|
| 513 |
|
|
wire [31:0] p2_tg_cmd_seed;
|
| 514 |
|
|
wire [31:0] p2_tg_data_seed;
|
| 515 |
|
|
wire p2_tg_load_seed;
|
| 516 |
|
|
wire [2:0] p2_tg_addr_mode;
|
| 517 |
|
|
wire [3:0] p2_tg_instr_mode;
|
| 518 |
|
|
wire [1:0] p2_tg_bl_mode;
|
| 519 |
|
|
wire [3:0] p2_tg_data_mode;
|
| 520 |
|
|
wire p2_tg_mode_load;
|
| 521 |
|
|
wire [5:0] p2_tg_fixed_bl;
|
| 522 |
|
|
wire [2:0] p2_tg_fixed_instr;
|
| 523 |
|
|
wire [31:0] p2_tg_fixed_addr;
|
| 524 |
|
|
wire p2_error;
|
| 525 |
|
|
wire p2_cmp_error;
|
| 526 |
|
|
wire [P2_DWIDTH-1 :0] p2_cmp_data;
|
| 527 |
|
|
wire p2_cmp_data_valid;
|
| 528 |
|
|
|
| 529 |
|
|
//p3 wire declarations
|
| 530 |
|
|
wire p3_tg_run_traffic;
|
| 531 |
|
|
wire [31:0] p3_tg_start_addr;
|
| 532 |
|
|
wire [31:0] p3_tg_end_addr;
|
| 533 |
|
|
wire [31:0] p3_tg_cmd_seed;
|
| 534 |
|
|
wire [31:0] p3_tg_data_seed;
|
| 535 |
|
|
wire p3_tg_load_seed;
|
| 536 |
|
|
wire [2:0] p3_tg_addr_mode;
|
| 537 |
|
|
wire [3:0] p3_tg_instr_mode;
|
| 538 |
|
|
wire [1:0] p3_tg_bl_mode;
|
| 539 |
|
|
wire [3:0] p3_tg_data_mode;
|
| 540 |
|
|
wire p3_tg_mode_load;
|
| 541 |
|
|
wire [5:0] p3_tg_fixed_bl;
|
| 542 |
|
|
wire [2:0] p3_tg_fixed_instr;
|
| 543 |
|
|
wire [31:0] p3_tg_fixed_addr;
|
| 544 |
|
|
wire p3_error;
|
| 545 |
|
|
wire p3_cmp_error;
|
| 546 |
|
|
wire [P3_DWIDTH-1 :0] p3_cmp_data;
|
| 547 |
|
|
wire p3_cmp_data_valid;
|
| 548 |
|
|
|
| 549 |
|
|
//p4 wire declarations
|
| 550 |
|
|
wire p4_tg_run_traffic;
|
| 551 |
|
|
wire [31:0] p4_tg_start_addr;
|
| 552 |
|
|
wire [31:0] p4_tg_end_addr;
|
| 553 |
|
|
wire [31:0] p4_tg_cmd_seed;
|
| 554 |
|
|
wire [31:0] p4_tg_data_seed;
|
| 555 |
|
|
wire p4_tg_load_seed;
|
| 556 |
|
|
wire [2:0] p4_tg_addr_mode;
|
| 557 |
|
|
wire [3:0] p4_tg_instr_mode;
|
| 558 |
|
|
wire [1:0] p4_tg_bl_mode;
|
| 559 |
|
|
wire [3:0] p4_tg_data_mode;
|
| 560 |
|
|
wire p4_tg_mode_load;
|
| 561 |
|
|
wire [5:0] p4_tg_fixed_bl;
|
| 562 |
|
|
wire [2:0] p4_tg_fixed_instr;
|
| 563 |
|
|
wire [31:0] p4_tg_fixed_addr;
|
| 564 |
|
|
wire p4_error;
|
| 565 |
|
|
wire p4_cmp_error;
|
| 566 |
|
|
wire [P4_DWIDTH-1 :0] p4_cmp_data;
|
| 567 |
|
|
wire p4_cmp_data_valid;
|
| 568 |
|
|
|
| 569 |
|
|
//p5 wire declarations
|
| 570 |
|
|
wire p5_tg_run_traffic;
|
| 571 |
|
|
wire [31:0] p5_tg_start_addr;
|
| 572 |
|
|
wire [31:0] p5_tg_end_addr;
|
| 573 |
|
|
wire [31:0] p5_tg_cmd_seed;
|
| 574 |
|
|
wire [31:0] p5_tg_data_seed;
|
| 575 |
|
|
wire p5_tg_load_seed;
|
| 576 |
|
|
wire [2:0] p5_tg_addr_mode;
|
| 577 |
|
|
wire [3:0] p5_tg_instr_mode;
|
| 578 |
|
|
wire [1:0] p5_tg_bl_mode;
|
| 579 |
|
|
wire [3:0] p5_tg_data_mode;
|
| 580 |
|
|
wire p5_tg_mode_load;
|
| 581 |
|
|
wire [5:0] p5_tg_fixed_bl;
|
| 582 |
|
|
wire [2:0] p5_tg_fixed_instr;
|
| 583 |
|
|
wire [31:0] p5_tg_fixed_addr;
|
| 584 |
|
|
wire p5_error;
|
| 585 |
|
|
wire p5_cmp_error;
|
| 586 |
|
|
wire [P5_DWIDTH-1 :0] p5_cmp_data;
|
| 587 |
|
|
wire p5_cmp_data_valid;
|
| 588 |
|
|
|
| 589 |
|
|
wire p2_mcb_cmd_en_sig;
|
| 590 |
|
|
wire [2:0] p2_mcb_cmd_instr_sig;
|
| 591 |
|
|
wire [5:0] p2_mcb_cmd_bl_sig;
|
| 592 |
|
|
wire [29:0] p2_mcb_cmd_addr_sig;
|
| 593 |
|
|
wire p2_mcb_wr_en_sig;
|
| 594 |
|
|
wire p3_mcb_cmd_en_sig;
|
| 595 |
|
|
wire [2:0] p3_mcb_cmd_instr_sig;
|
| 596 |
|
|
wire [5:0] p3_mcb_cmd_bl_sig;
|
| 597 |
|
|
wire [29:0] p3_mcb_cmd_addr_sig;
|
| 598 |
|
|
wire p3_mcb_wr_en_sig;
|
| 599 |
|
|
wire p4_mcb_cmd_en_sig;
|
| 600 |
|
|
wire [2:0] p4_mcb_cmd_instr_sig;
|
| 601 |
|
|
wire [5:0] p4_mcb_cmd_bl_sig;
|
| 602 |
|
|
wire [29:0] p4_mcb_cmd_addr_sig;
|
| 603 |
|
|
wire p4_mcb_wr_en_sig;
|
| 604 |
|
|
wire p5_mcb_cmd_en_sig;
|
| 605 |
|
|
wire [2:0] p5_mcb_cmd_instr_sig;
|
| 606 |
|
|
wire [5:0] p5_mcb_cmd_bl_sig;
|
| 607 |
|
|
wire [29:0] p5_mcb_cmd_addr_sig;
|
| 608 |
|
|
wire p5_mcb_wr_en_sig;
|
| 609 |
|
|
|
| 610 |
|
|
|
| 611 |
|
|
assign cmp_error = p0_cmp_error | p1_cmp_error | p2_cmp_error | p3_cmp_error | p4_cmp_error | p5_cmp_error;
|
| 612 |
|
|
assign error = p0_error | p1_error | p2_error | p3_error | p4_error | p5_error;
|
| 613 |
|
|
|
| 614 |
|
|
|
| 615 |
|
|
// The following 'generate' statement captures data for cmp_data and cmp_data_valid
|
| 616 |
|
|
// ports from the corresponding signals of the first enabled traffic generator.
|
| 617 |
|
|
generate
|
| 618 |
|
|
if (C_PORT_ENABLE[0] == 1) begin: port0_status
|
| 619 |
|
|
assign cmp_data = p0_cmp_data[31:0];
|
| 620 |
|
|
assign cmp_data_valid = p0_cmp_data_valid;
|
| 621 |
|
|
end
|
| 622 |
|
|
else if (C_PORT_ENABLE[1] == 1) begin: port1_status
|
| 623 |
|
|
assign cmp_data = p1_cmp_data[31:0];
|
| 624 |
|
|
assign cmp_data_valid = p1_cmp_data_valid;
|
| 625 |
|
|
end
|
| 626 |
|
|
else if (C_PORT_ENABLE[2] == 1) begin: port2_status
|
| 627 |
|
|
assign cmp_data = p2_cmp_data[31:0];
|
| 628 |
|
|
assign cmp_data_valid = p2_cmp_data_valid;
|
| 629 |
|
|
end
|
| 630 |
|
|
else if (C_PORT_ENABLE[3] == 1) begin: port3_status
|
| 631 |
|
|
assign cmp_data = p3_cmp_data[31:0];
|
| 632 |
|
|
assign cmp_data_valid = p3_cmp_data_valid;
|
| 633 |
|
|
end
|
| 634 |
|
|
else if (C_PORT_ENABLE[4] == 1) begin: port4_status
|
| 635 |
|
|
assign cmp_data = p4_cmp_data[31:0];
|
| 636 |
|
|
assign cmp_data_valid = p4_cmp_data_valid;
|
| 637 |
|
|
end
|
| 638 |
|
|
else if (C_PORT_ENABLE[5] == 1) begin: port5_status
|
| 639 |
|
|
assign cmp_data = p5_cmp_data[31:0];
|
| 640 |
|
|
assign cmp_data_valid = p5_cmp_data_valid;
|
| 641 |
|
|
end
|
| 642 |
|
|
endgenerate
|
| 643 |
|
|
|
| 644 |
|
|
|
| 645 |
|
|
// The following 'generate' statement activates the traffic generator for
|
| 646 |
|
|
// Port-0 if it is enabled
|
| 647 |
|
|
generate
|
| 648 |
|
|
if (C_PORT_ENABLE[0] == 1'b1)
|
| 649 |
|
|
begin : PORT0_TG
|
| 650 |
|
|
// init_mem_pattern_ctr module instantiation for Port-0
|
| 651 |
|
|
init_mem_pattern_ctr #
|
| 652 |
|
|
(
|
| 653 |
|
|
.DWIDTH (C_P0_DATA_PORT_SIZE),
|
| 654 |
|
|
.FAMILY (FAMILY),
|
| 655 |
|
|
.BEGIN_ADDRESS (C_p0_BEGIN_ADDRESS),
|
| 656 |
|
|
.END_ADDRESS (C_p0_END_ADDRESS),
|
| 657 |
|
|
.CMD_SEED_VALUE (32'h56456783),
|
| 658 |
|
|
.DATA_SEED_VALUE (32'h12345678),
|
| 659 |
|
|
.DATA_MODE (C_p0_DATA_MODE),
|
| 660 |
|
|
.PORT_MODE (C_P0_PORT_MODE)
|
| 661 |
|
|
)
|
| 662 |
|
|
init_mem_pattern_ctr_p0
|
| 663 |
|
|
(
|
| 664 |
|
|
.clk_i (clk0),
|
| 665 |
|
|
.rst_i (rst0),
|
| 666 |
|
|
|
| 667 |
|
|
.mcb_cmd_en_i (p0_mcb_cmd_en),
|
| 668 |
|
|
.mcb_cmd_instr_i (p0_mcb_cmd_instr),
|
| 669 |
|
|
.mcb_cmd_addr_i (p0_mcb_cmd_addr),
|
| 670 |
|
|
.mcb_cmd_bl_i (p0_mcb_cmd_bl),
|
| 671 |
|
|
.mcb_wr_en_i (p0_mcb_wr_en),
|
| 672 |
|
|
|
| 673 |
|
|
.vio_modify_enable (vio_modify_enable),
|
| 674 |
|
|
.vio_data_mode_value (vio_data_mode_value),
|
| 675 |
|
|
.vio_addr_mode_value (vio_addr_mode_value),
|
| 676 |
|
|
.vio_bl_mode_value (2'b10), // always set to PRBS_BL mode
|
| 677 |
|
|
.vio_fixed_bl_value (6'd64), // always set to 64 in order to run PRBS data pattern
|
| 678 |
|
|
.mcb_init_done_i (calib_done),
|
| 679 |
|
|
.cmp_error (p0_error),
|
| 680 |
|
|
.run_traffic_o (p0_tg_run_traffic),
|
| 681 |
|
|
.start_addr_o (p0_tg_start_addr),
|
| 682 |
|
|
.end_addr_o (p0_tg_end_addr),
|
| 683 |
|
|
.cmd_seed_o (p0_tg_cmd_seed),
|
| 684 |
|
|
.data_seed_o (p0_tg_data_seed),
|
| 685 |
|
|
.load_seed_o (p0_tg_load_seed),
|
| 686 |
|
|
.addr_mode_o (p0_tg_addr_mode),
|
| 687 |
|
|
.instr_mode_o (p0_tg_instr_mode),
|
| 688 |
|
|
.bl_mode_o (p0_tg_bl_mode),
|
| 689 |
|
|
.data_mode_o (p0_tg_data_mode),
|
| 690 |
|
|
.mode_load_o (p0_tg_mode_load),
|
| 691 |
|
|
.fixed_bl_o (p0_tg_fixed_bl),
|
| 692 |
|
|
.fixed_instr_o (p0_tg_fixed_instr),
|
| 693 |
|
|
.fixed_addr_o (p0_tg_fixed_addr)
|
| 694 |
|
|
);
|
| 695 |
|
|
|
| 696 |
|
|
// traffic generator instantiation for Port-0
|
| 697 |
|
|
mcb_traffic_gen #
|
| 698 |
|
|
(
|
| 699 |
|
|
.MEM_BURST_LEN (C_MEM_BURST_LEN),
|
| 700 |
|
|
.MEM_COL_WIDTH (C_MEM_NUM_COL_BITS),
|
| 701 |
|
|
.NUM_DQ_PINS (C_NUM_DQ_PINS),
|
| 702 |
|
|
.DQ_ERROR_WIDTH (DQ_ERROR_WIDTH),
|
| 703 |
|
|
.PORT_MODE (C_P0_PORT_MODE),
|
| 704 |
|
|
.DWIDTH (C_P0_DATA_PORT_SIZE),
|
| 705 |
|
|
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
|
| 706 |
|
|
.FAMILY (FAMILY),
|
| 707 |
|
|
.SIMULATION ("FALSE"),
|
| 708 |
|
|
.DATA_PATTERN (TG_DATA_PATTERN),
|
| 709 |
|
|
.CMD_PATTERN ("CGEN_ALL"),
|
| 710 |
|
|
.ADDR_WIDTH (30),
|
| 711 |
|
|
.PRBS_SADDR_MASK_POS (C_p0_PRBS_SADDR_MASK_POS),
|
| 712 |
|
|
.PRBS_EADDR_MASK_POS (C_p0_PRBS_EADDR_MASK_POS),
|
| 713 |
|
|
.PRBS_SADDR (C_p0_BEGIN_ADDRESS),
|
| 714 |
|
|
.PRBS_EADDR (C_p0_END_ADDRESS)
|
| 715 |
|
|
)
|
| 716 |
|
|
m_traffic_gen_p0
|
| 717 |
|
|
(
|
| 718 |
|
|
.clk_i (clk0),
|
| 719 |
|
|
.rst_i (rst0),
|
| 720 |
|
|
.run_traffic_i (p0_tg_run_traffic),
|
| 721 |
|
|
.manual_clear_error (rst0),
|
| 722 |
|
|
// runtime parameter
|
| 723 |
|
|
.start_addr_i (p0_tg_start_addr),
|
| 724 |
|
|
.end_addr_i (p0_tg_end_addr),
|
| 725 |
|
|
.cmd_seed_i (p0_tg_cmd_seed),
|
| 726 |
|
|
.data_seed_i (p0_tg_data_seed),
|
| 727 |
|
|
.load_seed_i (p0_tg_load_seed),
|
| 728 |
|
|
.addr_mode_i (p0_tg_addr_mode),
|
| 729 |
|
|
.instr_mode_i (p0_tg_instr_mode),
|
| 730 |
|
|
.bl_mode_i (p0_tg_bl_mode),
|
| 731 |
|
|
.data_mode_i (p0_tg_data_mode),
|
| 732 |
|
|
.mode_load_i (p0_tg_mode_load),
|
| 733 |
|
|
// fixed pattern inputs interface
|
| 734 |
|
|
.fixed_bl_i (p0_tg_fixed_bl),
|
| 735 |
|
|
.fixed_instr_i (p0_tg_fixed_instr),
|
| 736 |
|
|
.fixed_addr_i (p0_tg_fixed_addr),
|
| 737 |
|
|
.fixed_data_i (),
|
| 738 |
|
|
// BRAM interface.
|
| 739 |
|
|
.bram_cmd_i (),
|
| 740 |
|
|
.bram_valid_i (),
|
| 741 |
|
|
.bram_rdy_o (),
|
| 742 |
|
|
|
| 743 |
|
|
// MCB INTERFACE
|
| 744 |
|
|
.mcb_cmd_en_o (p0_mcb_cmd_en),
|
| 745 |
|
|
.mcb_cmd_instr_o (p0_mcb_cmd_instr),
|
| 746 |
|
|
.mcb_cmd_bl_o (p0_mcb_cmd_bl),
|
| 747 |
|
|
.mcb_cmd_addr_o (p0_mcb_cmd_addr),
|
| 748 |
|
|
.mcb_cmd_full_i (p0_mcb_cmd_full),
|
| 749 |
|
|
|
| 750 |
|
|
.mcb_wr_en_o (p0_mcb_wr_en),
|
| 751 |
|
|
.mcb_wr_mask_o (p0_mcb_wr_mask),
|
| 752 |
|
|
.mcb_wr_data_o (p0_mcb_wr_data),
|
| 753 |
|
|
.mcb_wr_data_end_o (),
|
| 754 |
|
|
.mcb_wr_full_i (p0_mcb_wr_full),
|
| 755 |
|
|
.mcb_wr_fifo_counts (p0_mcb_wr_fifo_counts),
|
| 756 |
|
|
|
| 757 |
|
|
.mcb_rd_en_o (p0_mcb_rd_en),
|
| 758 |
|
|
.mcb_rd_data_i (p0_mcb_rd_data),
|
| 759 |
|
|
.mcb_rd_empty_i (p0_mcb_rd_empty),
|
| 760 |
|
|
.mcb_rd_fifo_counts (p0_mcb_rd_fifo_counts),
|
| 761 |
|
|
|
| 762 |
|
|
// status feedback
|
| 763 |
|
|
.counts_rst (rst0),
|
| 764 |
|
|
.wr_data_counts (),
|
| 765 |
|
|
.rd_data_counts (),
|
| 766 |
|
|
.error (p0_error), // asserted whenever the read back data is not correct.
|
| 767 |
|
|
.error_status (p0_error_status), // TBD how signals mapped
|
| 768 |
|
|
.cmp_data (p0_cmp_data),
|
| 769 |
|
|
.cmp_data_valid (p0_cmp_data_valid),
|
| 770 |
|
|
.cmp_error (p0_cmp_error),
|
| 771 |
|
|
.mem_rd_data (),
|
| 772 |
|
|
.dq_error_bytelane_cmp (),
|
| 773 |
|
|
.cumlative_dq_lane_error ()
|
| 774 |
|
|
);
|
| 775 |
|
|
end
|
| 776 |
|
|
else begin: PORT0_NO_TG
|
| 777 |
|
|
assign p0_error = 'b0;
|
| 778 |
|
|
assign p0_error_status = 'b0;
|
| 779 |
|
|
assign p0_cmp_data = 'b0;
|
| 780 |
|
|
assign p0_cmp_data_valid = 'b0;
|
| 781 |
|
|
assign p0_cmp_error = 'b0;
|
| 782 |
|
|
end
|
| 783 |
|
|
endgenerate
|
| 784 |
|
|
|
| 785 |
|
|
|
| 786 |
|
|
// The following 'generate' statement activates the traffic generator for
|
| 787 |
|
|
// Port-1 if it is enabled
|
| 788 |
|
|
generate
|
| 789 |
|
|
if (C_PORT_ENABLE[1] == 1'b1)
|
| 790 |
|
|
begin : PORT1_TG
|
| 791 |
|
|
// init_mem_pattern_ctr module instantiation for Port-1
|
| 792 |
|
|
init_mem_pattern_ctr #
|
| 793 |
|
|
(
|
| 794 |
|
|
.DWIDTH (C_P1_DATA_PORT_SIZE),
|
| 795 |
|
|
.FAMILY (FAMILY),
|
| 796 |
|
|
.BEGIN_ADDRESS (C_p1_BEGIN_ADDRESS),
|
| 797 |
|
|
.END_ADDRESS (C_p1_END_ADDRESS),
|
| 798 |
|
|
.CMD_SEED_VALUE (32'h56456783),
|
| 799 |
|
|
.DATA_SEED_VALUE (32'h12345678),
|
| 800 |
|
|
.DATA_MODE (C_p1_DATA_MODE),
|
| 801 |
|
|
.PORT_MODE (C_P1_PORT_MODE)
|
| 802 |
|
|
)
|
| 803 |
|
|
init_mem_pattern_ctr_p1
|
| 804 |
|
|
(
|
| 805 |
|
|
.clk_i (clk0),
|
| 806 |
|
|
.rst_i (rst0),
|
| 807 |
|
|
|
| 808 |
|
|
.mcb_cmd_en_i (p1_mcb_cmd_en),
|
| 809 |
|
|
.mcb_cmd_instr_i (p1_mcb_cmd_instr),
|
| 810 |
|
|
.mcb_cmd_addr_i (p1_mcb_cmd_addr),
|
| 811 |
|
|
.mcb_cmd_bl_i (p1_mcb_cmd_bl),
|
| 812 |
|
|
.mcb_wr_en_i (p1_mcb_wr_en),
|
| 813 |
|
|
|
| 814 |
|
|
.vio_modify_enable (vio_modify_enable),
|
| 815 |
|
|
.vio_data_mode_value (vio_data_mode_value),
|
| 816 |
|
|
.vio_addr_mode_value (vio_addr_mode_value),
|
| 817 |
|
|
.vio_bl_mode_value (2'b10),
|
| 818 |
|
|
.vio_fixed_bl_value (6'd64),
|
| 819 |
|
|
.mcb_init_done_i (calib_done),
|
| 820 |
|
|
.cmp_error (p1_error),
|
| 821 |
|
|
.run_traffic_o (p1_tg_run_traffic),
|
| 822 |
|
|
.start_addr_o (p1_tg_start_addr),
|
| 823 |
|
|
.end_addr_o (p1_tg_end_addr),
|
| 824 |
|
|
.cmd_seed_o (p1_tg_cmd_seed),
|
| 825 |
|
|
.data_seed_o (p1_tg_data_seed),
|
| 826 |
|
|
.load_seed_o (p1_tg_load_seed),
|
| 827 |
|
|
.addr_mode_o (p1_tg_addr_mode),
|
| 828 |
|
|
.instr_mode_o (p1_tg_instr_mode),
|
| 829 |
|
|
.bl_mode_o (p1_tg_bl_mode),
|
| 830 |
|
|
.data_mode_o (p1_tg_data_mode),
|
| 831 |
|
|
.mode_load_o (p1_tg_mode_load),
|
| 832 |
|
|
.fixed_bl_o (p1_tg_fixed_bl),
|
| 833 |
|
|
.fixed_instr_o (p1_tg_fixed_instr),
|
| 834 |
|
|
.fixed_addr_o (p1_tg_fixed_addr)
|
| 835 |
|
|
);
|
| 836 |
|
|
|
| 837 |
|
|
// traffic generator instantiation for Port-1
|
| 838 |
|
|
mcb_traffic_gen #
|
| 839 |
|
|
(
|
| 840 |
|
|
.MEM_BURST_LEN (C_MEM_BURST_LEN),
|
| 841 |
|
|
.MEM_COL_WIDTH (C_MEM_NUM_COL_BITS),
|
| 842 |
|
|
.NUM_DQ_PINS (C_NUM_DQ_PINS),
|
| 843 |
|
|
.DQ_ERROR_WIDTH (DQ_ERROR_WIDTH),
|
| 844 |
|
|
.PORT_MODE (C_P1_PORT_MODE),
|
| 845 |
|
|
.DWIDTH (C_P1_DATA_PORT_SIZE),
|
| 846 |
|
|
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
|
| 847 |
|
|
.FAMILY (FAMILY),
|
| 848 |
|
|
.SIMULATION ("FALSE"),
|
| 849 |
|
|
.DATA_PATTERN (TG_DATA_PATTERN),
|
| 850 |
|
|
.CMD_PATTERN ("CGEN_ALL"),
|
| 851 |
|
|
.ADDR_WIDTH (30),
|
| 852 |
|
|
.PRBS_SADDR_MASK_POS (C_p1_PRBS_SADDR_MASK_POS),
|
| 853 |
|
|
.PRBS_EADDR_MASK_POS (C_p1_PRBS_EADDR_MASK_POS),
|
| 854 |
|
|
.PRBS_SADDR (C_p1_BEGIN_ADDRESS),
|
| 855 |
|
|
.PRBS_EADDR (C_p1_END_ADDRESS)
|
| 856 |
|
|
)
|
| 857 |
|
|
m_traffic_gen_p1
|
| 858 |
|
|
(
|
| 859 |
|
|
.clk_i (clk0),
|
| 860 |
|
|
.rst_i (rst0),
|
| 861 |
|
|
.run_traffic_i (p1_tg_run_traffic),
|
| 862 |
|
|
.manual_clear_error (rst0),
|
| 863 |
|
|
// runtime parameter
|
| 864 |
|
|
.start_addr_i (p1_tg_start_addr),
|
| 865 |
|
|
.end_addr_i (p1_tg_end_addr),
|
| 866 |
|
|
.cmd_seed_i (p1_tg_cmd_seed),
|
| 867 |
|
|
.data_seed_i (p1_tg_data_seed),
|
| 868 |
|
|
.load_seed_i (p1_tg_load_seed),
|
| 869 |
|
|
.addr_mode_i (p1_tg_addr_mode),
|
| 870 |
|
|
.instr_mode_i (p1_tg_instr_mode),
|
| 871 |
|
|
.bl_mode_i (p1_tg_bl_mode),
|
| 872 |
|
|
.data_mode_i (p1_tg_data_mode),
|
| 873 |
|
|
.mode_load_i (p1_tg_mode_load),
|
| 874 |
|
|
// fixed pattern inputs interface
|
| 875 |
|
|
.fixed_bl_i (p1_tg_fixed_bl),
|
| 876 |
|
|
.fixed_instr_i (p1_tg_fixed_instr),
|
| 877 |
|
|
.fixed_addr_i (p1_tg_fixed_addr),
|
| 878 |
|
|
.fixed_data_i (),
|
| 879 |
|
|
// BRAM interface.
|
| 880 |
|
|
.bram_cmd_i (),
|
| 881 |
|
|
.bram_valid_i (),
|
| 882 |
|
|
.bram_rdy_o (),
|
| 883 |
|
|
|
| 884 |
|
|
// MCB INTERFACE
|
| 885 |
|
|
.mcb_cmd_en_o (p1_mcb_cmd_en),
|
| 886 |
|
|
.mcb_cmd_instr_o (p1_mcb_cmd_instr),
|
| 887 |
|
|
.mcb_cmd_bl_o (p1_mcb_cmd_bl),
|
| 888 |
|
|
.mcb_cmd_addr_o (p1_mcb_cmd_addr),
|
| 889 |
|
|
.mcb_cmd_full_i (p1_mcb_cmd_full),
|
| 890 |
|
|
|
| 891 |
|
|
.mcb_wr_en_o (p1_mcb_wr_en),
|
| 892 |
|
|
.mcb_wr_mask_o (p1_mcb_wr_mask),
|
| 893 |
|
|
.mcb_wr_data_o (p1_mcb_wr_data),
|
| 894 |
|
|
.mcb_wr_data_end_o (),
|
| 895 |
|
|
.mcb_wr_full_i (p1_mcb_wr_full),
|
| 896 |
|
|
.mcb_wr_fifo_counts (p1_mcb_wr_fifo_counts),
|
| 897 |
|
|
|
| 898 |
|
|
.mcb_rd_en_o (p1_mcb_rd_en),
|
| 899 |
|
|
.mcb_rd_data_i (p1_mcb_rd_data),
|
| 900 |
|
|
.mcb_rd_empty_i (p1_mcb_rd_empty),
|
| 901 |
|
|
.mcb_rd_fifo_counts (p1_mcb_rd_fifo_counts),
|
| 902 |
|
|
|
| 903 |
|
|
// status feedback
|
| 904 |
|
|
.counts_rst (rst0),
|
| 905 |
|
|
.wr_data_counts (),
|
| 906 |
|
|
.rd_data_counts (),
|
| 907 |
|
|
.error (p1_error),
|
| 908 |
|
|
.error_status (p1_error_status),
|
| 909 |
|
|
.cmp_data (p1_cmp_data),
|
| 910 |
|
|
.cmp_data_valid (p1_cmp_data_valid),
|
| 911 |
|
|
.cmp_error (p1_cmp_error),
|
| 912 |
|
|
.mem_rd_data (),
|
| 913 |
|
|
.dq_error_bytelane_cmp (),
|
| 914 |
|
|
.cumlative_dq_lane_error ()
|
| 915 |
|
|
);
|
| 916 |
|
|
end
|
| 917 |
|
|
else begin: PORT1_NO_TG
|
| 918 |
|
|
assign p1_error = 'b0;
|
| 919 |
|
|
assign p1_error_status = 'b0;
|
| 920 |
|
|
assign p1_cmp_data = 'b0;
|
| 921 |
|
|
assign p1_cmp_data_valid = 'b0;
|
| 922 |
|
|
assign p1_cmp_error = 'b0;
|
| 923 |
|
|
end
|
| 924 |
|
|
endgenerate
|
| 925 |
|
|
|
| 926 |
|
|
|
| 927 |
|
|
// The following 'generate' statement activates the traffic generator for
|
| 928 |
|
|
// Port-2 if it is enabled
|
| 929 |
|
|
generate
|
| 930 |
|
|
if (C_PORT_ENABLE[2] == 1'b1)
|
| 931 |
|
|
begin : PORT2_TG
|
| 932 |
|
|
// init_mem_pattern_ctr module instantiation for Port-2
|
| 933 |
|
|
init_mem_pattern_ctr #
|
| 934 |
|
|
(
|
| 935 |
|
|
.DWIDTH (P2_DWIDTH),
|
| 936 |
|
|
.FAMILY (FAMILY),
|
| 937 |
|
|
.BEGIN_ADDRESS (P2_BEGIN_ADDRESS),
|
| 938 |
|
|
.END_ADDRESS (P2_END_ADDRESS),
|
| 939 |
|
|
.CMD_SEED_VALUE (32'h56456783),
|
| 940 |
|
|
.DATA_SEED_VALUE (32'h12345678),
|
| 941 |
|
|
.DATA_MODE (P2_DATA_MODE),
|
| 942 |
|
|
.PORT_MODE (C_P2_PORT_MODE)
|
| 943 |
|
|
)
|
| 944 |
|
|
init_mem_pattern_ctr_p2
|
| 945 |
|
|
(
|
| 946 |
|
|
.clk_i (clk0),
|
| 947 |
|
|
.rst_i (rst0),
|
| 948 |
|
|
|
| 949 |
|
|
.mcb_cmd_en_i (p2_mcb_cmd_en_sig),
|
| 950 |
|
|
.mcb_cmd_instr_i (p2_mcb_cmd_instr_sig),
|
| 951 |
|
|
.mcb_cmd_addr_i (p2_mcb_cmd_addr_sig),
|
| 952 |
|
|
.mcb_cmd_bl_i (p2_mcb_cmd_bl_sig),
|
| 953 |
|
|
.mcb_wr_en_i (p2_mcb_wr_en_sig),
|
| 954 |
|
|
|
| 955 |
|
|
.vio_modify_enable (vio_modify_enable),
|
| 956 |
|
|
.vio_data_mode_value (vio_data_mode_value),
|
| 957 |
|
|
.vio_addr_mode_value (vio_addr_mode_value),
|
| 958 |
|
|
.vio_bl_mode_value (2'b10),
|
| 959 |
|
|
.vio_fixed_bl_value (6'd64),
|
| 960 |
|
|
.mcb_init_done_i (calib_done),
|
| 961 |
|
|
.cmp_error (p2_error),
|
| 962 |
|
|
.run_traffic_o (p2_tg_run_traffic),
|
| 963 |
|
|
.start_addr_o (p2_tg_start_addr),
|
| 964 |
|
|
.end_addr_o (p2_tg_end_addr),
|
| 965 |
|
|
.cmd_seed_o (p2_tg_cmd_seed),
|
| 966 |
|
|
.data_seed_o (p2_tg_data_seed),
|
| 967 |
|
|
.load_seed_o (p2_tg_load_seed),
|
| 968 |
|
|
.addr_mode_o (p2_tg_addr_mode),
|
| 969 |
|
|
.instr_mode_o (p2_tg_instr_mode),
|
| 970 |
|
|
.bl_mode_o (p2_tg_bl_mode),
|
| 971 |
|
|
.data_mode_o (p2_tg_data_mode),
|
| 972 |
|
|
.mode_load_o (p2_tg_mode_load),
|
| 973 |
|
|
.fixed_bl_o (p2_tg_fixed_bl),
|
| 974 |
|
|
.fixed_instr_o (p2_tg_fixed_instr),
|
| 975 |
|
|
.fixed_addr_o (p2_tg_fixed_addr)
|
| 976 |
|
|
);
|
| 977 |
|
|
|
| 978 |
|
|
// traffic generator instantiation for Port-1
|
| 979 |
|
|
mcb_traffic_gen #
|
| 980 |
|
|
(
|
| 981 |
|
|
.MEM_BURST_LEN (C_MEM_BURST_LEN),
|
| 982 |
|
|
.MEM_COL_WIDTH (C_MEM_NUM_COL_BITS),
|
| 983 |
|
|
.NUM_DQ_PINS (C_NUM_DQ_PINS),
|
| 984 |
|
|
.DQ_ERROR_WIDTH (DQ_ERROR_WIDTH),
|
| 985 |
|
|
.PORT_MODE (C_P2_PORT_MODE),
|
| 986 |
|
|
.DWIDTH (P2_DWIDTH),
|
| 987 |
|
|
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
|
| 988 |
|
|
.FAMILY (FAMILY),
|
| 989 |
|
|
.SIMULATION ("FALSE"),
|
| 990 |
|
|
.DATA_PATTERN (TG_DATA_PATTERN),
|
| 991 |
|
|
.CMD_PATTERN ("CGEN_ALL"),
|
| 992 |
|
|
.ADDR_WIDTH (30),
|
| 993 |
|
|
.PRBS_SADDR_MASK_POS (P2_PRBS_SADDR_MASK_POS),
|
| 994 |
|
|
.PRBS_EADDR_MASK_POS (P2_PRBS_EADDR_MASK_POS),
|
| 995 |
|
|
.PRBS_SADDR (P2_BEGIN_ADDRESS),
|
| 996 |
|
|
.PRBS_EADDR (P2_END_ADDRESS)
|
| 997 |
|
|
)
|
| 998 |
|
|
m_traffic_gen_p2
|
| 999 |
|
|
(
|
| 1000 |
|
|
.clk_i (clk0),
|
| 1001 |
|
|
.rst_i (rst0),
|
| 1002 |
|
|
.run_traffic_i (p2_tg_run_traffic),
|
| 1003 |
|
|
.manual_clear_error (rst0),
|
| 1004 |
|
|
// runtime parameter
|
| 1005 |
|
|
.start_addr_i (p2_tg_start_addr),
|
| 1006 |
|
|
.end_addr_i (p2_tg_end_addr),
|
| 1007 |
|
|
.cmd_seed_i (p2_tg_cmd_seed),
|
| 1008 |
|
|
.data_seed_i (p2_tg_data_seed),
|
| 1009 |
|
|
.load_seed_i (p2_tg_load_seed),
|
| 1010 |
|
|
.addr_mode_i (p2_tg_addr_mode),
|
| 1011 |
|
|
.instr_mode_i (p2_tg_instr_mode),
|
| 1012 |
|
|
.bl_mode_i (p2_tg_bl_mode),
|
| 1013 |
|
|
.data_mode_i (p2_tg_data_mode),
|
| 1014 |
|
|
.mode_load_i (p2_tg_mode_load),
|
| 1015 |
|
|
// fixed pattern inputs interface
|
| 1016 |
|
|
.fixed_bl_i (p2_tg_fixed_bl),
|
| 1017 |
|
|
.fixed_instr_i (p2_tg_fixed_instr),
|
| 1018 |
|
|
.fixed_addr_i (p2_tg_fixed_addr),
|
| 1019 |
|
|
.fixed_data_i (),
|
| 1020 |
|
|
// BRAM interface.
|
| 1021 |
|
|
.bram_cmd_i (),
|
| 1022 |
|
|
.bram_valid_i (),
|
| 1023 |
|
|
.bram_rdy_o (),
|
| 1024 |
|
|
|
| 1025 |
|
|
// MCB INTERFACE
|
| 1026 |
|
|
.mcb_cmd_en_o (p2_mcb_cmd_en),
|
| 1027 |
|
|
.mcb_cmd_instr_o (p2_mcb_cmd_instr),
|
| 1028 |
|
|
.mcb_cmd_bl_o (p2_mcb_cmd_bl),
|
| 1029 |
|
|
.mcb_cmd_addr_o (p2_mcb_cmd_addr),
|
| 1030 |
|
|
.mcb_cmd_full_i (p2_mcb_cmd_full),
|
| 1031 |
|
|
|
| 1032 |
|
|
.mcb_wr_en_o (p2_mcb_wr_en),
|
| 1033 |
|
|
.mcb_wr_mask_o (p2_mcb_wr_mask),
|
| 1034 |
|
|
.mcb_wr_data_o (p2_mcb_wr_data),
|
| 1035 |
|
|
.mcb_wr_data_end_o (),
|
| 1036 |
|
|
.mcb_wr_full_i (p2_mcb_wr_full),
|
| 1037 |
|
|
.mcb_wr_fifo_counts (p2_mcb_wr_fifo_counts),
|
| 1038 |
|
|
|
| 1039 |
|
|
.mcb_rd_en_o (p2_mcb_rd_en),
|
| 1040 |
|
|
.mcb_rd_data_i (p2_mcb_rd_data),
|
| 1041 |
|
|
.mcb_rd_empty_i (p2_mcb_rd_empty),
|
| 1042 |
|
|
.mcb_rd_fifo_counts (p2_mcb_rd_fifo_counts),
|
| 1043 |
|
|
|
| 1044 |
|
|
// status feedback
|
| 1045 |
|
|
.counts_rst (rst0),
|
| 1046 |
|
|
.wr_data_counts (),
|
| 1047 |
|
|
.rd_data_counts (),
|
| 1048 |
|
|
.error (p2_error),
|
| 1049 |
|
|
.error_status (p2_error_status),
|
| 1050 |
|
|
.cmp_data (p2_cmp_data),
|
| 1051 |
|
|
.cmp_data_valid (p2_cmp_data_valid),
|
| 1052 |
|
|
.cmp_error (p2_cmp_error),
|
| 1053 |
|
|
.mem_rd_data (),
|
| 1054 |
|
|
.dq_error_bytelane_cmp (),
|
| 1055 |
|
|
.cumlative_dq_lane_error ()
|
| 1056 |
|
|
);
|
| 1057 |
|
|
end
|
| 1058 |
|
|
else begin: PORT2_NO_TG
|
| 1059 |
|
|
assign p2_error = 'b0;
|
| 1060 |
|
|
assign p2_error_status = 'b0;
|
| 1061 |
|
|
assign p2_cmp_data = 'b0;
|
| 1062 |
|
|
assign p2_cmp_data_valid = 'b0;
|
| 1063 |
|
|
assign p2_cmp_error = 'b0;
|
| 1064 |
|
|
end
|
| 1065 |
|
|
endgenerate
|
| 1066 |
|
|
|
| 1067 |
|
|
|
| 1068 |
|
|
// The following 'generate' statement activates the traffic generator for
|
| 1069 |
|
|
// Port-3 if it is enabled
|
| 1070 |
|
|
generate
|
| 1071 |
|
|
if (C_PORT_ENABLE[3] == 1'b1)
|
| 1072 |
|
|
begin : PORT3_TG
|
| 1073 |
|
|
// init_mem_pattern_ctr module instantiation for Port-3
|
| 1074 |
|
|
init_mem_pattern_ctr #
|
| 1075 |
|
|
(
|
| 1076 |
|
|
.DWIDTH (P3_DWIDTH),
|
| 1077 |
|
|
.FAMILY (FAMILY),
|
| 1078 |
|
|
.BEGIN_ADDRESS (P3_BEGIN_ADDRESS),
|
| 1079 |
|
|
.END_ADDRESS (P3_END_ADDRESS),
|
| 1080 |
|
|
.CMD_SEED_VALUE (32'h56456783),
|
| 1081 |
|
|
.DATA_SEED_VALUE (32'h12345678),
|
| 1082 |
|
|
.DATA_MODE (P3_DATA_MODE),
|
| 1083 |
|
|
.PORT_MODE (C_P3_PORT_MODE)
|
| 1084 |
|
|
)
|
| 1085 |
|
|
init_mem_pattern_ctr_p3
|
| 1086 |
|
|
(
|
| 1087 |
|
|
.clk_i (clk0),
|
| 1088 |
|
|
.rst_i (rst0),
|
| 1089 |
|
|
|
| 1090 |
|
|
.mcb_cmd_en_i (p3_mcb_cmd_en_sig),
|
| 1091 |
|
|
.mcb_cmd_instr_i (p3_mcb_cmd_instr_sig),
|
| 1092 |
|
|
.mcb_cmd_addr_i (p3_mcb_cmd_addr_sig),
|
| 1093 |
|
|
.mcb_cmd_bl_i (p3_mcb_cmd_bl_sig),
|
| 1094 |
|
|
.mcb_wr_en_i (p3_mcb_wr_en_sig),
|
| 1095 |
|
|
|
| 1096 |
|
|
.vio_modify_enable (vio_modify_enable),
|
| 1097 |
|
|
.vio_data_mode_value (vio_data_mode_value),
|
| 1098 |
|
|
.vio_addr_mode_value (vio_addr_mode_value),
|
| 1099 |
|
|
.vio_bl_mode_value (2'b10),
|
| 1100 |
|
|
.vio_fixed_bl_value (6'd64),
|
| 1101 |
|
|
.mcb_init_done_i (calib_done),
|
| 1102 |
|
|
.cmp_error (p3_error),
|
| 1103 |
|
|
.run_traffic_o (p3_tg_run_traffic),
|
| 1104 |
|
|
.start_addr_o (p3_tg_start_addr),
|
| 1105 |
|
|
.end_addr_o (p3_tg_end_addr),
|
| 1106 |
|
|
.cmd_seed_o (p3_tg_cmd_seed),
|
| 1107 |
|
|
.data_seed_o (p3_tg_data_seed),
|
| 1108 |
|
|
.load_seed_o (p3_tg_load_seed),
|
| 1109 |
|
|
.addr_mode_o (p3_tg_addr_mode),
|
| 1110 |
|
|
.instr_mode_o (p3_tg_instr_mode),
|
| 1111 |
|
|
.bl_mode_o (p3_tg_bl_mode),
|
| 1112 |
|
|
.data_mode_o (p3_tg_data_mode),
|
| 1113 |
|
|
.mode_load_o (p3_tg_mode_load),
|
| 1114 |
|
|
.fixed_bl_o (p3_tg_fixed_bl),
|
| 1115 |
|
|
.fixed_instr_o (p3_tg_fixed_instr),
|
| 1116 |
|
|
.fixed_addr_o (p3_tg_fixed_addr)
|
| 1117 |
|
|
);
|
| 1118 |
|
|
|
| 1119 |
|
|
// traffic generator instantiation for Port-1
|
| 1120 |
|
|
mcb_traffic_gen #
|
| 1121 |
|
|
(
|
| 1122 |
|
|
.MEM_BURST_LEN (C_MEM_BURST_LEN),
|
| 1123 |
|
|
.MEM_COL_WIDTH (C_MEM_NUM_COL_BITS),
|
| 1124 |
|
|
.NUM_DQ_PINS (C_NUM_DQ_PINS),
|
| 1125 |
|
|
.DQ_ERROR_WIDTH (DQ_ERROR_WIDTH),
|
| 1126 |
|
|
.PORT_MODE (C_P3_PORT_MODE),
|
| 1127 |
|
|
.DWIDTH (P3_DWIDTH),
|
| 1128 |
|
|
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
|
| 1129 |
|
|
.FAMILY (FAMILY),
|
| 1130 |
|
|
.SIMULATION ("FALSE"),
|
| 1131 |
|
|
.DATA_PATTERN (TG_DATA_PATTERN),
|
| 1132 |
|
|
.CMD_PATTERN ("CGEN_ALL"),
|
| 1133 |
|
|
.ADDR_WIDTH (30),
|
| 1134 |
|
|
.PRBS_SADDR_MASK_POS (P3_PRBS_SADDR_MASK_POS),
|
| 1135 |
|
|
.PRBS_EADDR_MASK_POS (P3_PRBS_EADDR_MASK_POS),
|
| 1136 |
|
|
.PRBS_SADDR (P3_BEGIN_ADDRESS),
|
| 1137 |
|
|
.PRBS_EADDR (P3_END_ADDRESS)
|
| 1138 |
|
|
)
|
| 1139 |
|
|
m_traffic_gen_p3
|
| 1140 |
|
|
(
|
| 1141 |
|
|
.clk_i (clk0),
|
| 1142 |
|
|
.rst_i (rst0),
|
| 1143 |
|
|
.run_traffic_i (p3_tg_run_traffic),
|
| 1144 |
|
|
.manual_clear_error (rst0),
|
| 1145 |
|
|
// runtime parameter
|
| 1146 |
|
|
.start_addr_i (p3_tg_start_addr),
|
| 1147 |
|
|
.end_addr_i (p3_tg_end_addr),
|
| 1148 |
|
|
.cmd_seed_i (p3_tg_cmd_seed),
|
| 1149 |
|
|
.data_seed_i (p3_tg_data_seed),
|
| 1150 |
|
|
.load_seed_i (p3_tg_load_seed),
|
| 1151 |
|
|
.addr_mode_i (p3_tg_addr_mode),
|
| 1152 |
|
|
.instr_mode_i (p3_tg_instr_mode),
|
| 1153 |
|
|
.bl_mode_i (p3_tg_bl_mode),
|
| 1154 |
|
|
.data_mode_i (p3_tg_data_mode),
|
| 1155 |
|
|
.mode_load_i (p3_tg_mode_load),
|
| 1156 |
|
|
// fixed pattern inputs interface
|
| 1157 |
|
|
.fixed_bl_i (p3_tg_fixed_bl),
|
| 1158 |
|
|
.fixed_instr_i (p3_tg_fixed_instr),
|
| 1159 |
|
|
.fixed_addr_i (p3_tg_fixed_addr),
|
| 1160 |
|
|
.fixed_data_i (),
|
| 1161 |
|
|
// BRAM interface.
|
| 1162 |
|
|
.bram_cmd_i (),
|
| 1163 |
|
|
.bram_valid_i (),
|
| 1164 |
|
|
.bram_rdy_o (),
|
| 1165 |
|
|
|
| 1166 |
|
|
// MCB INTERFACE
|
| 1167 |
|
|
.mcb_cmd_en_o (p3_mcb_cmd_en),
|
| 1168 |
|
|
.mcb_cmd_instr_o (p3_mcb_cmd_instr),
|
| 1169 |
|
|
.mcb_cmd_bl_o (p3_mcb_cmd_bl),
|
| 1170 |
|
|
.mcb_cmd_addr_o (p3_mcb_cmd_addr),
|
| 1171 |
|
|
.mcb_cmd_full_i (p3_mcb_cmd_full),
|
| 1172 |
|
|
|
| 1173 |
|
|
.mcb_wr_en_o (p3_mcb_wr_en),
|
| 1174 |
|
|
.mcb_wr_mask_o (p3_mcb_wr_mask),
|
| 1175 |
|
|
.mcb_wr_data_o (p3_mcb_wr_data),
|
| 1176 |
|
|
.mcb_wr_data_end_o (),
|
| 1177 |
|
|
.mcb_wr_full_i (p3_mcb_wr_full),
|
| 1178 |
|
|
.mcb_wr_fifo_counts (p3_mcb_wr_fifo_counts),
|
| 1179 |
|
|
|
| 1180 |
|
|
.mcb_rd_en_o (p3_mcb_rd_en),
|
| 1181 |
|
|
.mcb_rd_data_i (p3_mcb_rd_data),
|
| 1182 |
|
|
.mcb_rd_empty_i (p3_mcb_rd_empty),
|
| 1183 |
|
|
.mcb_rd_fifo_counts (p3_mcb_rd_fifo_counts),
|
| 1184 |
|
|
|
| 1185 |
|
|
// status feedback
|
| 1186 |
|
|
.counts_rst (rst0),
|
| 1187 |
|
|
.wr_data_counts (),
|
| 1188 |
|
|
.rd_data_counts (),
|
| 1189 |
|
|
.error (p3_error),
|
| 1190 |
|
|
.error_status (p3_error_status),
|
| 1191 |
|
|
.cmp_data (p3_cmp_data),
|
| 1192 |
|
|
.cmp_data_valid (p3_cmp_data_valid),
|
| 1193 |
|
|
.cmp_error (p3_cmp_error),
|
| 1194 |
|
|
.mem_rd_data (),
|
| 1195 |
|
|
.dq_error_bytelane_cmp (),
|
| 1196 |
|
|
.cumlative_dq_lane_error ()
|
| 1197 |
|
|
);
|
| 1198 |
|
|
end
|
| 1199 |
|
|
else begin: PORT3_NO_TG
|
| 1200 |
|
|
assign p3_error = 'b0;
|
| 1201 |
|
|
assign p3_error_status = 'b0;
|
| 1202 |
|
|
assign p3_cmp_data = 'b0;
|
| 1203 |
|
|
assign p3_cmp_data_valid = 'b0;
|
| 1204 |
|
|
assign p3_cmp_error = 'b0;
|
| 1205 |
|
|
end
|
| 1206 |
|
|
endgenerate
|
| 1207 |
|
|
|
| 1208 |
|
|
|
| 1209 |
|
|
// The following 'generate' statement activates the traffic generator for
|
| 1210 |
|
|
// Port-4 if it is enabled
|
| 1211 |
|
|
generate
|
| 1212 |
|
|
if (C_PORT_ENABLE[4] == 1'b1)
|
| 1213 |
|
|
begin : PORT4_TG
|
| 1214 |
|
|
// init_mem_pattern_ctr module instantiation for Port-4
|
| 1215 |
|
|
init_mem_pattern_ctr #
|
| 1216 |
|
|
(
|
| 1217 |
|
|
.DWIDTH (P4_DWIDTH),
|
| 1218 |
|
|
.FAMILY (FAMILY),
|
| 1219 |
|
|
.BEGIN_ADDRESS (P4_BEGIN_ADDRESS),
|
| 1220 |
|
|
.END_ADDRESS (P4_END_ADDRESS),
|
| 1221 |
|
|
.CMD_SEED_VALUE (32'h56456783),
|
| 1222 |
|
|
.DATA_SEED_VALUE (32'h12345678),
|
| 1223 |
|
|
.DATA_MODE (P4_DATA_MODE),
|
| 1224 |
|
|
.PORT_MODE (C_P4_PORT_MODE)
|
| 1225 |
|
|
)
|
| 1226 |
|
|
init_mem_pattern_ctr_p4
|
| 1227 |
|
|
(
|
| 1228 |
|
|
.clk_i (clk0),
|
| 1229 |
|
|
.rst_i (rst0),
|
| 1230 |
|
|
|
| 1231 |
|
|
.mcb_cmd_en_i (p4_mcb_cmd_en_sig),
|
| 1232 |
|
|
.mcb_cmd_instr_i (p4_mcb_cmd_instr_sig),
|
| 1233 |
|
|
.mcb_cmd_addr_i (p4_mcb_cmd_addr_sig),
|
| 1234 |
|
|
.mcb_cmd_bl_i (p4_mcb_cmd_bl_sig),
|
| 1235 |
|
|
.mcb_wr_en_i (p4_mcb_wr_en_sig),
|
| 1236 |
|
|
|
| 1237 |
|
|
.vio_modify_enable (vio_modify_enable),
|
| 1238 |
|
|
.vio_data_mode_value (vio_data_mode_value),
|
| 1239 |
|
|
.vio_addr_mode_value (vio_addr_mode_value),
|
| 1240 |
|
|
.vio_bl_mode_value (2'b10),
|
| 1241 |
|
|
.vio_fixed_bl_value (6'd64),
|
| 1242 |
|
|
.mcb_init_done_i (calib_done),
|
| 1243 |
|
|
.cmp_error (p4_error),
|
| 1244 |
|
|
.run_traffic_o (p4_tg_run_traffic),
|
| 1245 |
|
|
.start_addr_o (p4_tg_start_addr),
|
| 1246 |
|
|
.end_addr_o (p4_tg_end_addr),
|
| 1247 |
|
|
.cmd_seed_o (p4_tg_cmd_seed),
|
| 1248 |
|
|
.data_seed_o (p4_tg_data_seed),
|
| 1249 |
|
|
.load_seed_o (p4_tg_load_seed),
|
| 1250 |
|
|
.addr_mode_o (p4_tg_addr_mode),
|
| 1251 |
|
|
.instr_mode_o (p4_tg_instr_mode),
|
| 1252 |
|
|
.bl_mode_o (p4_tg_bl_mode),
|
| 1253 |
|
|
.data_mode_o (p4_tg_data_mode),
|
| 1254 |
|
|
.mode_load_o (p4_tg_mode_load),
|
| 1255 |
|
|
.fixed_bl_o (p4_tg_fixed_bl),
|
| 1256 |
|
|
.fixed_instr_o (p4_tg_fixed_instr),
|
| 1257 |
|
|
.fixed_addr_o (p4_tg_fixed_addr)
|
| 1258 |
|
|
);
|
| 1259 |
|
|
|
| 1260 |
|
|
// traffic generator instantiation for Port-1
|
| 1261 |
|
|
mcb_traffic_gen #
|
| 1262 |
|
|
(
|
| 1263 |
|
|
.MEM_BURST_LEN (C_MEM_BURST_LEN),
|
| 1264 |
|
|
.MEM_COL_WIDTH (C_MEM_NUM_COL_BITS),
|
| 1265 |
|
|
.NUM_DQ_PINS (C_NUM_DQ_PINS),
|
| 1266 |
|
|
.DQ_ERROR_WIDTH (DQ_ERROR_WIDTH),
|
| 1267 |
|
|
.PORT_MODE (C_P4_PORT_MODE),
|
| 1268 |
|
|
.DWIDTH (P4_DWIDTH),
|
| 1269 |
|
|
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
|
| 1270 |
|
|
.FAMILY (FAMILY),
|
| 1271 |
|
|
.SIMULATION ("FALSE"),
|
| 1272 |
|
|
.DATA_PATTERN (TG_DATA_PATTERN),
|
| 1273 |
|
|
.CMD_PATTERN ("CGEN_ALL"),
|
| 1274 |
|
|
.ADDR_WIDTH (30),
|
| 1275 |
|
|
.PRBS_SADDR_MASK_POS (P4_PRBS_SADDR_MASK_POS),
|
| 1276 |
|
|
.PRBS_EADDR_MASK_POS (P4_PRBS_EADDR_MASK_POS),
|
| 1277 |
|
|
.PRBS_SADDR (P4_BEGIN_ADDRESS),
|
| 1278 |
|
|
.PRBS_EADDR (P4_END_ADDRESS)
|
| 1279 |
|
|
)
|
| 1280 |
|
|
m_traffic_gen_p4
|
| 1281 |
|
|
(
|
| 1282 |
|
|
.clk_i (clk0),
|
| 1283 |
|
|
.rst_i (rst0),
|
| 1284 |
|
|
.run_traffic_i (p4_tg_run_traffic),
|
| 1285 |
|
|
.manual_clear_error (rst0),
|
| 1286 |
|
|
// runtime parameter
|
| 1287 |
|
|
.start_addr_i (p4_tg_start_addr),
|
| 1288 |
|
|
.end_addr_i (p4_tg_end_addr),
|
| 1289 |
|
|
.cmd_seed_i (p4_tg_cmd_seed),
|
| 1290 |
|
|
.data_seed_i (p4_tg_data_seed),
|
| 1291 |
|
|
.load_seed_i (p4_tg_load_seed),
|
| 1292 |
|
|
.addr_mode_i (p4_tg_addr_mode),
|
| 1293 |
|
|
.instr_mode_i (p4_tg_instr_mode),
|
| 1294 |
|
|
.bl_mode_i (p4_tg_bl_mode),
|
| 1295 |
|
|
.data_mode_i (p4_tg_data_mode),
|
| 1296 |
|
|
.mode_load_i (p4_tg_mode_load),
|
| 1297 |
|
|
// fixed pattern inputs interface
|
| 1298 |
|
|
.fixed_bl_i (p4_tg_fixed_bl),
|
| 1299 |
|
|
.fixed_instr_i (p4_tg_fixed_instr),
|
| 1300 |
|
|
.fixed_addr_i (p4_tg_fixed_addr),
|
| 1301 |
|
|
.fixed_data_i (),
|
| 1302 |
|
|
// BRAM interface.
|
| 1303 |
|
|
.bram_cmd_i (),
|
| 1304 |
|
|
.bram_valid_i (),
|
| 1305 |
|
|
.bram_rdy_o (),
|
| 1306 |
|
|
|
| 1307 |
|
|
// MCB INTERFACE
|
| 1308 |
|
|
.mcb_cmd_en_o (p4_mcb_cmd_en),
|
| 1309 |
|
|
.mcb_cmd_instr_o (p4_mcb_cmd_instr),
|
| 1310 |
|
|
.mcb_cmd_bl_o (p4_mcb_cmd_bl),
|
| 1311 |
|
|
.mcb_cmd_addr_o (p4_mcb_cmd_addr),
|
| 1312 |
|
|
.mcb_cmd_full_i (p4_mcb_cmd_full),
|
| 1313 |
|
|
|
| 1314 |
|
|
.mcb_wr_en_o (p4_mcb_wr_en),
|
| 1315 |
|
|
.mcb_wr_mask_o (p4_mcb_wr_mask),
|
| 1316 |
|
|
.mcb_wr_data_o (p4_mcb_wr_data),
|
| 1317 |
|
|
.mcb_wr_data_end_o (),
|
| 1318 |
|
|
.mcb_wr_full_i (p4_mcb_wr_full),
|
| 1319 |
|
|
.mcb_wr_fifo_counts (p4_mcb_wr_fifo_counts),
|
| 1320 |
|
|
|
| 1321 |
|
|
.mcb_rd_en_o (p4_mcb_rd_en),
|
| 1322 |
|
|
.mcb_rd_data_i (p4_mcb_rd_data),
|
| 1323 |
|
|
.mcb_rd_empty_i (p4_mcb_rd_empty),
|
| 1324 |
|
|
.mcb_rd_fifo_counts (p4_mcb_rd_fifo_counts),
|
| 1325 |
|
|
|
| 1326 |
|
|
// status feedback
|
| 1327 |
|
|
.counts_rst (rst0),
|
| 1328 |
|
|
.wr_data_counts (),
|
| 1329 |
|
|
.rd_data_counts (),
|
| 1330 |
|
|
.error (p4_error),
|
| 1331 |
|
|
.error_status (p4_error_status),
|
| 1332 |
|
|
.cmp_data (p4_cmp_data),
|
| 1333 |
|
|
.cmp_data_valid (p4_cmp_data_valid),
|
| 1334 |
|
|
.cmp_error (p4_cmp_error),
|
| 1335 |
|
|
.mem_rd_data (),
|
| 1336 |
|
|
.dq_error_bytelane_cmp (),
|
| 1337 |
|
|
.cumlative_dq_lane_error ()
|
| 1338 |
|
|
);
|
| 1339 |
|
|
end
|
| 1340 |
|
|
else begin: PORT4_NO_TG
|
| 1341 |
|
|
assign p4_error = 'b0;
|
| 1342 |
|
|
assign p4_error_status = 'b0;
|
| 1343 |
|
|
assign p4_cmp_data = 'b0;
|
| 1344 |
|
|
assign p4_cmp_data_valid = 'b0;
|
| 1345 |
|
|
assign p4_cmp_error = 'b0;
|
| 1346 |
|
|
end
|
| 1347 |
|
|
endgenerate
|
| 1348 |
|
|
|
| 1349 |
|
|
|
| 1350 |
|
|
// The following 'generate' statement activates the traffic generator for
|
| 1351 |
|
|
// Port-5 if it is enabled
|
| 1352 |
|
|
generate
|
| 1353 |
|
|
if (C_PORT_ENABLE[5] == 1'b1)
|
| 1354 |
|
|
begin : PORT5_TG
|
| 1355 |
|
|
// init_mem_pattern_ctr module instantiation for Port-5
|
| 1356 |
|
|
init_mem_pattern_ctr #
|
| 1357 |
|
|
(
|
| 1358 |
|
|
.DWIDTH (P5_DWIDTH),
|
| 1359 |
|
|
.FAMILY (FAMILY),
|
| 1360 |
|
|
.BEGIN_ADDRESS (P5_BEGIN_ADDRESS),
|
| 1361 |
|
|
.END_ADDRESS (P5_END_ADDRESS),
|
| 1362 |
|
|
.CMD_SEED_VALUE (32'h56456783),
|
| 1363 |
|
|
.DATA_SEED_VALUE (32'h12345678),
|
| 1364 |
|
|
.DATA_MODE (P5_DATA_MODE),
|
| 1365 |
|
|
.PORT_MODE (C_P5_PORT_MODE)
|
| 1366 |
|
|
)
|
| 1367 |
|
|
init_mem_pattern_ctr_p5
|
| 1368 |
|
|
(
|
| 1369 |
|
|
.clk_i (clk0),
|
| 1370 |
|
|
.rst_i (rst0),
|
| 1371 |
|
|
|
| 1372 |
|
|
.mcb_cmd_en_i (p5_mcb_cmd_en_sig),
|
| 1373 |
|
|
.mcb_cmd_instr_i (p5_mcb_cmd_instr_sig),
|
| 1374 |
|
|
.mcb_cmd_addr_i (p5_mcb_cmd_addr_sig),
|
| 1375 |
|
|
.mcb_cmd_bl_i (p5_mcb_cmd_bl_sig),
|
| 1376 |
|
|
.mcb_wr_en_i (p5_mcb_wr_en_sig),
|
| 1377 |
|
|
|
| 1378 |
|
|
.vio_modify_enable (vio_modify_enable),
|
| 1379 |
|
|
.vio_data_mode_value (vio_data_mode_value),
|
| 1380 |
|
|
.vio_addr_mode_value (vio_addr_mode_value),
|
| 1381 |
|
|
.vio_bl_mode_value (2'b10),
|
| 1382 |
|
|
.vio_fixed_bl_value (6'd64),
|
| 1383 |
|
|
.mcb_init_done_i (calib_done),
|
| 1384 |
|
|
.cmp_error (p5_error),
|
| 1385 |
|
|
.run_traffic_o (p5_tg_run_traffic),
|
| 1386 |
|
|
.start_addr_o (p5_tg_start_addr),
|
| 1387 |
|
|
.end_addr_o (p5_tg_end_addr),
|
| 1388 |
|
|
.cmd_seed_o (p5_tg_cmd_seed),
|
| 1389 |
|
|
.data_seed_o (p5_tg_data_seed),
|
| 1390 |
|
|
.load_seed_o (p5_tg_load_seed),
|
| 1391 |
|
|
.addr_mode_o (p5_tg_addr_mode),
|
| 1392 |
|
|
.instr_mode_o (p5_tg_instr_mode),
|
| 1393 |
|
|
.bl_mode_o (p5_tg_bl_mode),
|
| 1394 |
|
|
.data_mode_o (p5_tg_data_mode),
|
| 1395 |
|
|
.mode_load_o (p5_tg_mode_load),
|
| 1396 |
|
|
.fixed_bl_o (p5_tg_fixed_bl),
|
| 1397 |
|
|
.fixed_instr_o (p5_tg_fixed_instr),
|
| 1398 |
|
|
.fixed_addr_o (p5_tg_fixed_addr)
|
| 1399 |
|
|
);
|
| 1400 |
|
|
|
| 1401 |
|
|
// traffic generator instantiation for Port-1
|
| 1402 |
|
|
mcb_traffic_gen #
|
| 1403 |
|
|
(
|
| 1404 |
|
|
.MEM_BURST_LEN (C_MEM_BURST_LEN),
|
| 1405 |
|
|
.MEM_COL_WIDTH (C_MEM_NUM_COL_BITS),
|
| 1406 |
|
|
.NUM_DQ_PINS (C_NUM_DQ_PINS),
|
| 1407 |
|
|
.DQ_ERROR_WIDTH (DQ_ERROR_WIDTH),
|
| 1408 |
|
|
.PORT_MODE (C_P5_PORT_MODE),
|
| 1409 |
|
|
.DWIDTH (P5_DWIDTH),
|
| 1410 |
|
|
.CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
|
| 1411 |
|
|
.FAMILY (FAMILY),
|
| 1412 |
|
|
.SIMULATION ("FALSE"),
|
| 1413 |
|
|
.DATA_PATTERN (TG_DATA_PATTERN),
|
| 1414 |
|
|
.CMD_PATTERN ("CGEN_ALL"),
|
| 1415 |
|
|
.ADDR_WIDTH (30),
|
| 1416 |
|
|
.PRBS_SADDR_MASK_POS (P5_PRBS_SADDR_MASK_POS),
|
| 1417 |
|
|
.PRBS_EADDR_MASK_POS (P5_PRBS_EADDR_MASK_POS),
|
| 1418 |
|
|
.PRBS_SADDR (P5_BEGIN_ADDRESS),
|
| 1419 |
|
|
.PRBS_EADDR (P5_END_ADDRESS)
|
| 1420 |
|
|
)
|
| 1421 |
|
|
m_traffic_gen_p5
|
| 1422 |
|
|
(
|
| 1423 |
|
|
.clk_i (clk0),
|
| 1424 |
|
|
.rst_i (rst0),
|
| 1425 |
|
|
.run_traffic_i (p5_tg_run_traffic),
|
| 1426 |
|
|
.manual_clear_error (rst0),
|
| 1427 |
|
|
// runtime parameter
|
| 1428 |
|
|
.start_addr_i (p5_tg_start_addr),
|
| 1429 |
|
|
.end_addr_i (p5_tg_end_addr),
|
| 1430 |
|
|
.cmd_seed_i (p5_tg_cmd_seed),
|
| 1431 |
|
|
.data_seed_i (p5_tg_data_seed),
|
| 1432 |
|
|
.load_seed_i (p5_tg_load_seed),
|
| 1433 |
|
|
.addr_mode_i (p5_tg_addr_mode),
|
| 1434 |
|
|
.instr_mode_i (p5_tg_instr_mode),
|
| 1435 |
|
|
.bl_mode_i (p5_tg_bl_mode),
|
| 1436 |
|
|
.data_mode_i (p5_tg_data_mode),
|
| 1437 |
|
|
.mode_load_i (p5_tg_mode_load),
|
| 1438 |
|
|
// fixed pattern inputs interface
|
| 1439 |
|
|
.fixed_bl_i (p5_tg_fixed_bl),
|
| 1440 |
|
|
.fixed_instr_i (p5_tg_fixed_instr),
|
| 1441 |
|
|
.fixed_addr_i (p5_tg_fixed_addr),
|
| 1442 |
|
|
.fixed_data_i (),
|
| 1443 |
|
|
// BRAM interface.
|
| 1444 |
|
|
.bram_cmd_i (),
|
| 1445 |
|
|
.bram_valid_i (),
|
| 1446 |
|
|
.bram_rdy_o (),
|
| 1447 |
|
|
|
| 1448 |
|
|
// MCB INTERFACE
|
| 1449 |
|
|
.mcb_cmd_en_o (p5_mcb_cmd_en),
|
| 1450 |
|
|
.mcb_cmd_instr_o (p5_mcb_cmd_instr),
|
| 1451 |
|
|
.mcb_cmd_bl_o (p5_mcb_cmd_bl),
|
| 1452 |
|
|
.mcb_cmd_addr_o (p5_mcb_cmd_addr),
|
| 1453 |
|
|
.mcb_cmd_full_i (p5_mcb_cmd_full),
|
| 1454 |
|
|
|
| 1455 |
|
|
.mcb_wr_en_o (p5_mcb_wr_en),
|
| 1456 |
|
|
.mcb_wr_mask_o (p5_mcb_wr_mask),
|
| 1457 |
|
|
.mcb_wr_data_o (p5_mcb_wr_data),
|
| 1458 |
|
|
.mcb_wr_data_end_o (),
|
| 1459 |
|
|
.mcb_wr_full_i (p5_mcb_wr_full),
|
| 1460 |
|
|
.mcb_wr_fifo_counts (p5_mcb_wr_fifo_counts),
|
| 1461 |
|
|
|
| 1462 |
|
|
.mcb_rd_en_o (p5_mcb_rd_en),
|
| 1463 |
|
|
.mcb_rd_data_i (p5_mcb_rd_data),
|
| 1464 |
|
|
.mcb_rd_empty_i (p5_mcb_rd_empty),
|
| 1465 |
|
|
.mcb_rd_fifo_counts (p5_mcb_rd_fifo_counts),
|
| 1466 |
|
|
|
| 1467 |
|
|
// status feedback
|
| 1468 |
|
|
.counts_rst (rst0),
|
| 1469 |
|
|
.wr_data_counts (),
|
| 1470 |
|
|
.rd_data_counts (),
|
| 1471 |
|
|
.error (p5_error),
|
| 1472 |
|
|
.error_status (p5_error_status),
|
| 1473 |
|
|
.cmp_data (p5_cmp_data),
|
| 1474 |
|
|
.cmp_data_valid (p5_cmp_data_valid),
|
| 1475 |
|
|
.cmp_error (p5_cmp_error),
|
| 1476 |
|
|
.mem_rd_data (),
|
| 1477 |
|
|
.dq_error_bytelane_cmp (),
|
| 1478 |
|
|
.cumlative_dq_lane_error ()
|
| 1479 |
|
|
);
|
| 1480 |
|
|
end
|
| 1481 |
|
|
else begin: PORT5_NO_TG
|
| 1482 |
|
|
assign p5_error = 'b0;
|
| 1483 |
|
|
assign p5_error_status = 'b0;
|
| 1484 |
|
|
assign p5_cmp_data = 'b0;
|
| 1485 |
|
|
assign p5_cmp_data_valid = 'b0;
|
| 1486 |
|
|
assign p5_cmp_error = 'b0;
|
| 1487 |
|
|
end
|
| 1488 |
|
|
endgenerate
|
| 1489 |
|
|
|
| 1490 |
|
|
|
| 1491 |
|
|
// The following 'generate' statement captures data for the command field signals
|
| 1492 |
|
|
// which should be fedback to init_mem_pattern_ctr module from mcb_traffic_gen module
|
| 1493 |
|
|
generate
|
| 1494 |
|
|
if (C_PORT_ENABLE[2] == 1'b1) begin: P2_cmd_field_mapping
|
| 1495 |
|
|
|
| 1496 |
|
|
if (C_P2_PORT_MODE == "RD_MODE") begin: RD_P2_cmd_field_mapping
|
| 1497 |
|
|
if (C_PORT_ENABLE[0] == 1'b1) begin: RD_P2_equal_P0_cmd_field
|
| 1498 |
|
|
assign p2_mcb_cmd_en_sig = p0_mcb_cmd_en;
|
| 1499 |
|
|
assign p2_mcb_cmd_instr_sig = p0_mcb_cmd_instr;
|
| 1500 |
|
|
assign p2_mcb_cmd_addr_sig = p0_mcb_cmd_addr;
|
| 1501 |
|
|
assign p2_mcb_cmd_bl_sig = p0_mcb_cmd_bl;
|
| 1502 |
|
|
assign p2_mcb_wr_en_sig = p0_mcb_wr_en;
|
| 1503 |
|
|
end
|
| 1504 |
|
|
else if (C_PORT_ENABLE[1] == 1'b1) begin: RD_P2_equal_P1_cmd_field
|
| 1505 |
|
|
assign p2_mcb_cmd_en_sig = p1_mcb_cmd_en;
|
| 1506 |
|
|
assign p2_mcb_cmd_instr_sig = p1_mcb_cmd_instr;
|
| 1507 |
|
|
assign p2_mcb_cmd_addr_sig = p1_mcb_cmd_addr;
|
| 1508 |
|
|
assign p2_mcb_cmd_bl_sig = p1_mcb_cmd_bl;
|
| 1509 |
|
|
assign p2_mcb_wr_en_sig = p1_mcb_wr_en;
|
| 1510 |
|
|
end
|
| 1511 |
|
|
else if ((C_PORT_ENABLE[3] == 1'b1) && (C_P3_PORT_MODE == "WR_MODE")) begin: RD_P2_equal_P3_cmd_field
|
| 1512 |
|
|
assign p2_mcb_cmd_en_sig = p3_mcb_cmd_en;
|
| 1513 |
|
|
assign p2_mcb_cmd_instr_sig = p3_mcb_cmd_instr;
|
| 1514 |
|
|
assign p2_mcb_cmd_addr_sig = p3_mcb_cmd_addr;
|
| 1515 |
|
|
assign p2_mcb_cmd_bl_sig = p3_mcb_cmd_bl;
|
| 1516 |
|
|
assign p2_mcb_wr_en_sig = p3_mcb_wr_en;
|
| 1517 |
|
|
end
|
| 1518 |
|
|
else if ((C_PORT_ENABLE[4] == 1'b1) && (C_P4_PORT_MODE == "WR_MODE")) begin: RD_P2_equal_P4_cmd_field
|
| 1519 |
|
|
assign p2_mcb_cmd_en_sig = p4_mcb_cmd_en;
|
| 1520 |
|
|
assign p2_mcb_cmd_instr_sig = p4_mcb_cmd_instr;
|
| 1521 |
|
|
assign p2_mcb_cmd_addr_sig = p4_mcb_cmd_addr;
|
| 1522 |
|
|
assign p2_mcb_cmd_bl_sig = p4_mcb_cmd_bl;
|
| 1523 |
|
|
assign p2_mcb_wr_en_sig = p4_mcb_wr_en;
|
| 1524 |
|
|
end
|
| 1525 |
|
|
else if ((C_PORT_ENABLE[5] == 1'b1) && (C_P5_PORT_MODE == "WR_MODE")) begin: RD_P2_equal_P5_cmd_field
|
| 1526 |
|
|
assign p2_mcb_cmd_en_sig = p5_mcb_cmd_en;
|
| 1527 |
|
|
assign p2_mcb_cmd_instr_sig = p5_mcb_cmd_instr;
|
| 1528 |
|
|
assign p2_mcb_cmd_addr_sig = p5_mcb_cmd_addr;
|
| 1529 |
|
|
assign p2_mcb_cmd_bl_sig = p5_mcb_cmd_bl;
|
| 1530 |
|
|
assign p2_mcb_wr_en_sig = p5_mcb_wr_en;
|
| 1531 |
|
|
end
|
| 1532 |
|
|
else begin: RD_P2_equal_P2_cmd_field
|
| 1533 |
|
|
assign p2_mcb_cmd_en_sig = p2_mcb_cmd_en;
|
| 1534 |
|
|
assign p2_mcb_cmd_instr_sig = p2_mcb_cmd_instr;
|
| 1535 |
|
|
assign p2_mcb_cmd_addr_sig = p2_mcb_cmd_addr;
|
| 1536 |
|
|
assign p2_mcb_cmd_bl_sig = p2_mcb_cmd_bl;
|
| 1537 |
|
|
assign p2_mcb_wr_en_sig = p2_mcb_wr_en;
|
| 1538 |
|
|
end
|
| 1539 |
|
|
end
|
| 1540 |
|
|
else begin: WR_P2_cmd_field_mapping
|
| 1541 |
|
|
assign p2_mcb_cmd_en_sig = p2_mcb_cmd_en;
|
| 1542 |
|
|
assign p2_mcb_cmd_instr_sig = p2_mcb_cmd_instr;
|
| 1543 |
|
|
assign p2_mcb_cmd_addr_sig = p2_mcb_cmd_addr;
|
| 1544 |
|
|
assign p2_mcb_cmd_bl_sig = p2_mcb_cmd_bl;
|
| 1545 |
|
|
assign p2_mcb_wr_en_sig = p2_mcb_wr_en;
|
| 1546 |
|
|
end
|
| 1547 |
|
|
end
|
| 1548 |
|
|
|
| 1549 |
|
|
if (C_PORT_ENABLE[3] == 1'b1) begin: P3_cmd_field_mapping
|
| 1550 |
|
|
|
| 1551 |
|
|
if (C_P3_PORT_MODE == "RD_MODE") begin: RD_P3_cmd_field_mapping
|
| 1552 |
|
|
if (C_PORT_ENABLE[0] == 1'b1) begin: RD_P3_equal_P0_cmd_field
|
| 1553 |
|
|
assign p3_mcb_cmd_en_sig = p0_mcb_cmd_en;
|
| 1554 |
|
|
assign p3_mcb_cmd_instr_sig = p0_mcb_cmd_instr;
|
| 1555 |
|
|
assign p3_mcb_cmd_addr_sig = p0_mcb_cmd_addr;
|
| 1556 |
|
|
assign p3_mcb_cmd_bl_sig = p0_mcb_cmd_bl;
|
| 1557 |
|
|
assign p3_mcb_wr_en_sig = p0_mcb_wr_en;
|
| 1558 |
|
|
end
|
| 1559 |
|
|
else if (C_PORT_ENABLE[1] == 1'b1) begin: RD_P3_equal_P1_cmd_field
|
| 1560 |
|
|
assign p3_mcb_cmd_en_sig = p1_mcb_cmd_en;
|
| 1561 |
|
|
assign p3_mcb_cmd_instr_sig = p1_mcb_cmd_instr;
|
| 1562 |
|
|
assign p3_mcb_cmd_addr_sig = p1_mcb_cmd_addr;
|
| 1563 |
|
|
assign p3_mcb_cmd_bl_sig = p1_mcb_cmd_bl;
|
| 1564 |
|
|
assign p3_mcb_wr_en_sig = p1_mcb_wr_en;
|
| 1565 |
|
|
end
|
| 1566 |
|
|
else if ((C_PORT_ENABLE[2] == 1'b1) && (C_P2_PORT_MODE == "WR_MODE")) begin: RD_P3_equal_P2_cmd_field
|
| 1567 |
|
|
assign p3_mcb_cmd_en_sig = p2_mcb_cmd_en;
|
| 1568 |
|
|
assign p3_mcb_cmd_instr_sig = p2_mcb_cmd_instr;
|
| 1569 |
|
|
assign p3_mcb_cmd_addr_sig = p2_mcb_cmd_addr;
|
| 1570 |
|
|
assign p3_mcb_cmd_bl_sig = p2_mcb_cmd_bl;
|
| 1571 |
|
|
assign p3_mcb_wr_en_sig = p2_mcb_wr_en;
|
| 1572 |
|
|
end
|
| 1573 |
|
|
else if ((C_PORT_ENABLE[4] == 1'b1) && (C_P4_PORT_MODE == "WR_MODE")) begin: RD_P3_equal_P4_cmd_field
|
| 1574 |
|
|
assign p3_mcb_cmd_en_sig = p4_mcb_cmd_en;
|
| 1575 |
|
|
assign p3_mcb_cmd_instr_sig = p4_mcb_cmd_instr;
|
| 1576 |
|
|
assign p3_mcb_cmd_addr_sig = p4_mcb_cmd_addr;
|
| 1577 |
|
|
assign p3_mcb_cmd_bl_sig = p4_mcb_cmd_bl;
|
| 1578 |
|
|
assign p3_mcb_wr_en_sig = p4_mcb_wr_en;
|
| 1579 |
|
|
end
|
| 1580 |
|
|
else if ((C_PORT_ENABLE[5] == 1'b1) && (C_P5_PORT_MODE == "WR_MODE")) begin: RD_P3_equal_P5_cmd_field
|
| 1581 |
|
|
assign p3_mcb_cmd_en_sig = p5_mcb_cmd_en;
|
| 1582 |
|
|
assign p3_mcb_cmd_instr_sig = p5_mcb_cmd_instr;
|
| 1583 |
|
|
assign p3_mcb_cmd_addr_sig = p5_mcb_cmd_addr;
|
| 1584 |
|
|
assign p3_mcb_cmd_bl_sig = p5_mcb_cmd_bl;
|
| 1585 |
|
|
assign p3_mcb_wr_en_sig = p5_mcb_wr_en;
|
| 1586 |
|
|
end
|
| 1587 |
|
|
else begin: RD_P3_equal_P3_cmd_field
|
| 1588 |
|
|
assign p3_mcb_cmd_en_sig = p3_mcb_cmd_en;
|
| 1589 |
|
|
assign p3_mcb_cmd_instr_sig = p3_mcb_cmd_instr;
|
| 1590 |
|
|
assign p3_mcb_cmd_addr_sig = p3_mcb_cmd_addr;
|
| 1591 |
|
|
assign p3_mcb_cmd_bl_sig = p3_mcb_cmd_bl;
|
| 1592 |
|
|
assign p3_mcb_wr_en_sig = p3_mcb_wr_en;
|
| 1593 |
|
|
end
|
| 1594 |
|
|
end
|
| 1595 |
|
|
else begin: WR_P3_cmd_field_mapping
|
| 1596 |
|
|
assign p3_mcb_cmd_en_sig = p3_mcb_cmd_en;
|
| 1597 |
|
|
assign p3_mcb_cmd_instr_sig = p3_mcb_cmd_instr;
|
| 1598 |
|
|
assign p3_mcb_cmd_addr_sig = p3_mcb_cmd_addr;
|
| 1599 |
|
|
assign p3_mcb_cmd_bl_sig = p3_mcb_cmd_bl;
|
| 1600 |
|
|
assign p3_mcb_wr_en_sig = p3_mcb_wr_en;
|
| 1601 |
|
|
end
|
| 1602 |
|
|
end
|
| 1603 |
|
|
|
| 1604 |
|
|
if (C_PORT_ENABLE[4] == 1'b1) begin: P4_cmd_field_mapping
|
| 1605 |
|
|
|
| 1606 |
|
|
if (C_P4_PORT_MODE == "RD_MODE") begin: RD_P4_cmd_field_mapping
|
| 1607 |
|
|
if (C_PORT_ENABLE[0] == 1'b1) begin: RD_P4_equal_P0_cmd_field
|
| 1608 |
|
|
assign p4_mcb_cmd_en_sig = p0_mcb_cmd_en;
|
| 1609 |
|
|
assign p4_mcb_cmd_instr_sig = p0_mcb_cmd_instr;
|
| 1610 |
|
|
assign p4_mcb_cmd_addr_sig = p0_mcb_cmd_addr;
|
| 1611 |
|
|
assign p4_mcb_cmd_bl_sig = p0_mcb_cmd_bl;
|
| 1612 |
|
|
assign p4_mcb_wr_en_sig = p0_mcb_wr_en;
|
| 1613 |
|
|
end
|
| 1614 |
|
|
else if (C_PORT_ENABLE[1] == 1'b1) begin: RD_P4_equal_P1_cmd_field
|
| 1615 |
|
|
assign p4_mcb_cmd_en_sig = p1_mcb_cmd_en;
|
| 1616 |
|
|
assign p4_mcb_cmd_instr_sig = p1_mcb_cmd_instr;
|
| 1617 |
|
|
assign p4_mcb_cmd_addr_sig = p1_mcb_cmd_addr;
|
| 1618 |
|
|
assign p4_mcb_cmd_bl_sig = p1_mcb_cmd_bl;
|
| 1619 |
|
|
assign p4_mcb_wr_en_sig = p1_mcb_wr_en;
|
| 1620 |
|
|
end
|
| 1621 |
|
|
else if ((C_PORT_ENABLE[2] == 1'b1) && (C_P2_PORT_MODE == "WR_MODE")) begin: RD_P4_equal_P2_cmd_field
|
| 1622 |
|
|
assign p4_mcb_cmd_en_sig = p2_mcb_cmd_en;
|
| 1623 |
|
|
assign p4_mcb_cmd_instr_sig = p2_mcb_cmd_instr;
|
| 1624 |
|
|
assign p4_mcb_cmd_addr_sig = p2_mcb_cmd_addr;
|
| 1625 |
|
|
assign p4_mcb_cmd_bl_sig = p2_mcb_cmd_bl;
|
| 1626 |
|
|
assign p4_mcb_wr_en_sig = p2_mcb_wr_en;
|
| 1627 |
|
|
end
|
| 1628 |
|
|
else if ((C_PORT_ENABLE[3] == 1'b1) && (C_P3_PORT_MODE == "WR_MODE")) begin: RD_P4_equal_P3_cmd_field
|
| 1629 |
|
|
assign p4_mcb_cmd_en_sig = p3_mcb_cmd_en;
|
| 1630 |
|
|
assign p4_mcb_cmd_instr_sig = p3_mcb_cmd_instr;
|
| 1631 |
|
|
assign p4_mcb_cmd_addr_sig = p3_mcb_cmd_addr;
|
| 1632 |
|
|
assign p4_mcb_cmd_bl_sig = p3_mcb_cmd_bl;
|
| 1633 |
|
|
assign p4_mcb_wr_en_sig = p3_mcb_wr_en;
|
| 1634 |
|
|
end
|
| 1635 |
|
|
else if ((C_PORT_ENABLE[5] == 1'b1) && (C_P5_PORT_MODE == "WR_MODE")) begin: RD_P4_equal_P5_cmd_field
|
| 1636 |
|
|
assign p4_mcb_cmd_en_sig = p5_mcb_cmd_en;
|
| 1637 |
|
|
assign p4_mcb_cmd_instr_sig = p5_mcb_cmd_instr;
|
| 1638 |
|
|
assign p4_mcb_cmd_addr_sig = p5_mcb_cmd_addr;
|
| 1639 |
|
|
assign p4_mcb_cmd_bl_sig = p5_mcb_cmd_bl;
|
| 1640 |
|
|
assign p4_mcb_wr_en_sig = p5_mcb_wr_en;
|
| 1641 |
|
|
end
|
| 1642 |
|
|
else begin: RD_P4_equal_P4_cmd_field
|
| 1643 |
|
|
assign p4_mcb_cmd_en_sig = p4_mcb_cmd_en;
|
| 1644 |
|
|
assign p4_mcb_cmd_instr_sig = p4_mcb_cmd_instr;
|
| 1645 |
|
|
assign p4_mcb_cmd_addr_sig = p4_mcb_cmd_addr;
|
| 1646 |
|
|
assign p4_mcb_cmd_bl_sig = p4_mcb_cmd_bl;
|
| 1647 |
|
|
assign p4_mcb_wr_en_sig = p4_mcb_wr_en;
|
| 1648 |
|
|
end
|
| 1649 |
|
|
end
|
| 1650 |
|
|
else begin: WR_P4_cmd_field_mapping
|
| 1651 |
|
|
assign p4_mcb_cmd_en_sig = p4_mcb_cmd_en;
|
| 1652 |
|
|
assign p4_mcb_cmd_instr_sig = p4_mcb_cmd_instr;
|
| 1653 |
|
|
assign p4_mcb_cmd_addr_sig = p4_mcb_cmd_addr;
|
| 1654 |
|
|
assign p4_mcb_cmd_bl_sig = p4_mcb_cmd_bl;
|
| 1655 |
|
|
assign p4_mcb_wr_en_sig = p4_mcb_wr_en;
|
| 1656 |
|
|
end
|
| 1657 |
|
|
end
|
| 1658 |
|
|
|
| 1659 |
|
|
if (C_PORT_ENABLE[5] == 1'b1) begin: P5_cmd_field_mapping
|
| 1660 |
|
|
|
| 1661 |
|
|
if (C_P5_PORT_MODE == "RD_MODE") begin: RD_P5_cmd_field_mapping
|
| 1662 |
|
|
if (C_PORT_ENABLE[0] == 1'b1) begin: RD_P5_equal_P0_cmd_field
|
| 1663 |
|
|
assign p5_mcb_cmd_en_sig = p0_mcb_cmd_en;
|
| 1664 |
|
|
assign p5_mcb_cmd_instr_sig = p0_mcb_cmd_instr;
|
| 1665 |
|
|
assign p5_mcb_cmd_addr_sig = p0_mcb_cmd_addr;
|
| 1666 |
|
|
assign p5_mcb_cmd_bl_sig = p0_mcb_cmd_bl;
|
| 1667 |
|
|
assign p5_mcb_wr_en_sig = p0_mcb_wr_en;
|
| 1668 |
|
|
end
|
| 1669 |
|
|
else if (C_PORT_ENABLE[1] == 1'b1) begin: RD_P5_equal_P1_cmd_field
|
| 1670 |
|
|
assign p5_mcb_cmd_en_sig = p1_mcb_cmd_en;
|
| 1671 |
|
|
assign p5_mcb_cmd_instr_sig = p1_mcb_cmd_instr;
|
| 1672 |
|
|
assign p5_mcb_cmd_addr_sig = p1_mcb_cmd_addr;
|
| 1673 |
|
|
assign p5_mcb_cmd_bl_sig = p1_mcb_cmd_bl;
|
| 1674 |
|
|
assign p5_mcb_wr_en_sig = p1_mcb_wr_en;
|
| 1675 |
|
|
end
|
| 1676 |
|
|
else if ((C_PORT_ENABLE[2] == 1'b1) && (C_P2_PORT_MODE == "WR_MODE")) begin: RD_P5_equal_P2_cmd_field
|
| 1677 |
|
|
assign p5_mcb_cmd_en_sig = p2_mcb_cmd_en;
|
| 1678 |
|
|
assign p5_mcb_cmd_instr_sig = p2_mcb_cmd_instr;
|
| 1679 |
|
|
assign p5_mcb_cmd_addr_sig = p2_mcb_cmd_addr;
|
| 1680 |
|
|
assign p5_mcb_cmd_bl_sig = p2_mcb_cmd_bl;
|
| 1681 |
|
|
assign p5_mcb_wr_en_sig = p2_mcb_wr_en;
|
| 1682 |
|
|
end
|
| 1683 |
|
|
else if ((C_PORT_ENABLE[3] == 1'b1) && (C_P3_PORT_MODE == "WR_MODE")) begin: RD_P5_equal_P3_cmd_field
|
| 1684 |
|
|
assign p5_mcb_cmd_en_sig = p3_mcb_cmd_en;
|
| 1685 |
|
|
assign p5_mcb_cmd_instr_sig = p3_mcb_cmd_instr;
|
| 1686 |
|
|
assign p5_mcb_cmd_addr_sig = p3_mcb_cmd_addr;
|
| 1687 |
|
|
assign p5_mcb_cmd_bl_sig = p3_mcb_cmd_bl;
|
| 1688 |
|
|
assign p5_mcb_wr_en_sig = p3_mcb_wr_en;
|
| 1689 |
|
|
end
|
| 1690 |
|
|
else if ((C_PORT_ENABLE[4] == 1'b1) && (C_P4_PORT_MODE == "WR_MODE")) begin: RD_P5_equal_P4_cmd_field
|
| 1691 |
|
|
assign p5_mcb_cmd_en_sig = p4_mcb_cmd_en;
|
| 1692 |
|
|
assign p5_mcb_cmd_instr_sig = p4_mcb_cmd_instr;
|
| 1693 |
|
|
assign p5_mcb_cmd_addr_sig = p4_mcb_cmd_addr;
|
| 1694 |
|
|
assign p5_mcb_cmd_bl_sig = p4_mcb_cmd_bl;
|
| 1695 |
|
|
assign p5_mcb_wr_en_sig = p4_mcb_wr_en;
|
| 1696 |
|
|
end
|
| 1697 |
|
|
else begin: RD_P5_equal_P5_cmd_field
|
| 1698 |
|
|
assign p5_mcb_cmd_en_sig = p5_mcb_cmd_en;
|
| 1699 |
|
|
assign p5_mcb_cmd_instr_sig = p5_mcb_cmd_instr;
|
| 1700 |
|
|
assign p5_mcb_cmd_addr_sig = p5_mcb_cmd_addr;
|
| 1701 |
|
|
assign p5_mcb_cmd_bl_sig = p5_mcb_cmd_bl;
|
| 1702 |
|
|
assign p5_mcb_wr_en_sig = p5_mcb_wr_en;
|
| 1703 |
|
|
end
|
| 1704 |
|
|
end
|
| 1705 |
|
|
else begin: WR_P5_cmd_field_mapping
|
| 1706 |
|
|
assign p5_mcb_cmd_en_sig = p5_mcb_cmd_en;
|
| 1707 |
|
|
assign p5_mcb_cmd_instr_sig = p5_mcb_cmd_instr;
|
| 1708 |
|
|
assign p5_mcb_cmd_addr_sig = p5_mcb_cmd_addr;
|
| 1709 |
|
|
assign p5_mcb_cmd_bl_sig = p5_mcb_cmd_bl;
|
| 1710 |
|
|
assign p5_mcb_wr_en_sig = p5_mcb_wr_en;
|
| 1711 |
|
|
end
|
| 1712 |
|
|
end
|
| 1713 |
|
|
endgenerate
|
| 1714 |
|
|
|
| 1715 |
|
|
endmodule
|
