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//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: %version
//  \   \         Application: MIG
//  /   /         Filename: rd_data_gen.v
// /___/   /\     Date Last Modified: 
// \   \  /  \    Date Created: 
//  \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR 
//Purpose: This module has all the timing control for generating "compare data" 
//         to compare the read data from memory.
//Reference:
//Revision History:
//*****************************************************************************
 
`timescale 1ps/1ps
 
module rd_data_gen #
   (
   parameter TCQ           = 100,
   parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6"
   parameter MEM_BURST_LEN = 8,
 
   parameter ADDR_WIDTH = 32,
   parameter BL_WIDTH = 6,
   parameter DWIDTH = 32,
   parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
   parameter NUM_DQ_PINS   = 8,
   parameter SEL_VICTIM_LINE = 3,  // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
 
   parameter COLUMN_WIDTH = 10
 
 )
 (
   input   clk_i,                 //
   input [4:0]  rst_i,
   input [31:0] prbs_fseed_i,
   input [3:0]  data_mode_i,   // "00" = bram; 
 
   output  cmd_rdy_o,             // ready to receive command. It should assert when data_port is ready at the                                        // beginning and will be deasserted once see the cmd_valid_i is asserted. 
                                  // And then it should reasserted when 
                                  // it is generating the last_word.
   input   cmd_valid_i,           // when both cmd_valid_i and cmd_rdy_o is high, the command  is valid.
   output  last_word_o,
 
//   input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
   input [DWIDTH-1:0] fixed_data_i,
   input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
   input [BL_WIDTH-1:0]   bl_i,   // generated burst length for control the burst data
   output                 user_bl_cnt_is_1_o,
   input   data_rdy_i,           // connect from mcb_wr_full when used as wr_data_gen in sp6
                                 // connect from mcb_rd_empty when used as rd_data_gen in sp6
                                 // connect from rd_data_valid in v6
                                 // When both data_rdy and data_valid is asserted, the ouput data is valid.
   output   reg data_valid_o,       // connect to wr_en or rd_en and is asserted whenever the 
                                 // pattern is available.
   output  [DWIDTH-1:0] data_o, // generated data pattern   
   input  rd_mdata_en
);
// 
 
 
 
wire [31:0]       prbs_data;
reg              cmd_start;
reg [31:0]        adata;
reg [31:0]        hdata;
reg [31:0]        ndata;
reg [31:0]        w1data;
reg [NUM_DQ_PINS*4-1:0]        v6_w1data;
 
reg [31:0]        w0data;
reg [DWIDTH-1:0] data;
reg               cmd_rdy;
reg               data_valid;
reg [6:0]user_burst_cnt;
reg       data_rdy_r1,data_rdy_r2;
reg       next_count_is_one;
reg       cmd_valid_r1;
reg [31:0] w3data;
 
assign data_port_fifo_rdy = data_rdy_i;
 
//assign cmd_start = cmd_valid_i & cmd_rdy ;
always @ (posedge clk_i)
begin
      data_rdy_r1 <= #TCQ data_rdy_i;
      data_rdy_r2 <= #TCQ data_rdy_r1;
      cmd_valid_r1 <= #TCQ cmd_valid_i;
end
 
always @ (posedge clk_i)
begin
if (user_burst_cnt == 2 && data_rdy_i)
     next_count_is_one <= #TCQ 1'b1;
else
     next_count_is_one <= #TCQ 1'b0;
end
 
reg user_bl_cnt_is_1;
assign user_bl_cnt_is_1_o = user_bl_cnt_is_1;
always @ (posedge clk_i)
begin
if ((user_burst_cnt == 2 && data_port_fifo_rdy && FAMILY == "SPARTAN6")
    || (user_burst_cnt == 2 && data_port_fifo_rdy &&  FAMILY == "VIRTEX6")
   )
 
     user_bl_cnt_is_1 <= #TCQ 1'b1;
else
     user_bl_cnt_is_1 <= #TCQ 1'b0;
end
 
 
reg cmd_start_b;
always @(cmd_valid_i,cmd_valid_r1,cmd_rdy,user_bl_cnt_is_1,rd_mdata_en)
begin
   if (FAMILY == "SPARTAN6") begin
       cmd_start = cmd_valid_i & cmd_rdy ;
       cmd_start_b = cmd_valid_i & cmd_rdy ;
       end
   else if (MEM_BURST_LEN == 4 && FAMILY == "VIRTEX6")  begin
       cmd_start =  rd_mdata_en;  //  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
       cmd_start_b =  rd_mdata_en;  //  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
           end
   else if (MEM_BURST_LEN == 8 && FAMILY == "VIRTEX6")   begin
 
       cmd_start = (~cmd_valid_r1 & cmd_valid_i) | user_bl_cnt_is_1;  //  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
       cmd_start_b = (~cmd_valid_r1 & cmd_valid_i) | user_bl_cnt_is_1;  //  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
       end
 
end
 
 
// counter to count user burst length
always @( posedge clk_i)
begin
  if ( rst_i[0] )
    user_burst_cnt <= #TCQ   'd0;
  else if(cmd_start)  begin
       if (bl_i == 6'b000000)
          user_burst_cnt <= #TCQ 7'b1000000;
       else
          user_burst_cnt <= #TCQ bl_i;
      end
  else if(data_port_fifo_rdy)
     if (user_burst_cnt != 6'd0)
        user_burst_cnt <= #TCQ   user_burst_cnt - 1'b1;
     else
        user_burst_cnt <= #TCQ   'd0;
 
end
 
reg u_bcount_2;
always @ (posedge clk_i)
begin
if ((user_burst_cnt == 2  && data_rdy_i )|| (cmd_start && bl_i == 1))
    u_bcount_2 <= #TCQ   1'b1;
else if (last_word_o)
    u_bcount_2 <= #TCQ   1'b0;
end
 
assign  last_word_o = u_bcount_2 & data_rdy_i;
 
 
 
 
// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
// is assert and reassert during the last data
 
//data_valid_o logic
 
 
 
assign cmd_rdy_o = cmd_rdy;
 
always @( posedge clk_i)
begin
  if ( rst_i[0] )
    cmd_rdy <= #TCQ   1'b1;
  else if (cmd_start)
       cmd_rdy <= #TCQ   1'b0;
  else if  ((data_port_fifo_rdy && user_burst_cnt == 1))
      cmd_rdy <= #TCQ   1'b1;
 
 
end
 
 
 
always @ (posedge clk_i)
begin
  if (rst_i[0])
    data_valid <= #TCQ   'd0;
  else if (user_burst_cnt == 6'd1 && data_port_fifo_rdy)
    data_valid <= #TCQ   1'b0;
  else if(( user_burst_cnt >= 6'd1) || cmd_start)
    data_valid <= #TCQ   1'b1;
end
 
 
always @ (data_valid, data_port_fifo_rdy)
if (FAMILY == "SPARTAN6")
    data_valid_o = data_valid;
else
    data_valid_o = data_port_fifo_rdy;
 
 
 
generate
if (FAMILY == "SPARTAN6") begin : SP6_DGEN
sp6_data_gen #
 
(
   .TCQ               (TCQ),
   .ADDR_WIDTH      (32 ),
   .BL_WIDTH        (BL_WIDTH       ),
   .DWIDTH          (DWIDTH       ),
   .DATA_PATTERN    (DATA_PATTERN  ),
   .NUM_DQ_PINS      (NUM_DQ_PINS  ),
   .COLUMN_WIDTH     (COLUMN_WIDTH)
 
 )
 sp6_data_gen
 (
   .clk_i              (clk_i         ),
   .rst_i              (rst_i[1]         ),
   .data_rdy_i         (data_rdy_i    ),
   .prbs_fseed_i       (prbs_fseed_i),
 
   .data_mode_i        (data_mode_i   ),
   .cmd_startA         (cmd_start    ),
   .cmd_startB         (cmd_start    ),
   .cmd_startC         (cmd_start    ),
   .cmd_startD         (cmd_start    ),
   .cmd_startE         (cmd_start    ),
   .fixed_data_i         (fixed_data_i),
 
   .addr_i             (addr_i        ),
   .user_burst_cnt     (user_burst_cnt),
   .fifo_rdy_i         (data_port_fifo_rdy    ),
   .data_o             (data_o        )
  );
 
end
endgenerate
generate
if (FAMILY == "VIRTEX6") begin : V6_DGEN
v6_data_gen #
 
(
   .TCQ               (TCQ),
   .ADDR_WIDTH      (32 ),
   .BL_WIDTH        (BL_WIDTH       ),
   .MEM_BURST_LEN   (MEM_BURST_LEN),
   .DWIDTH          (DWIDTH       ),
   .DATA_PATTERN    (DATA_PATTERN  ),
   .NUM_DQ_PINS      (NUM_DQ_PINS  ),
   .SEL_VICTIM_LINE   (SEL_VICTIM_LINE),
 
   .COLUMN_WIDTH     (COLUMN_WIDTH)
 
 )
 v6_data_gen
 (
   .clk_i              (clk_i         ),
   .rst_i              (rst_i[1]      ),
   .data_rdy_i         (data_rdy_i    ),
   .prbs_fseed_i       (prbs_fseed_i),
 
   .data_mode_i        (data_mode_i   ),
   .cmd_startA         (cmd_start    ),
   .cmd_startB         (cmd_start    ),
   .cmd_startC         (cmd_start    ),
   .cmd_startD         (cmd_start    ),
   .cmd_startE         (cmd_start    ),
   .m_addr_i           (addr_i),//(m_addr_i        ),          
   .fixed_data_i       (fixed_data_i),
 
   .addr_i             (addr_i        ),
   .user_burst_cnt     (user_burst_cnt),
   .fifo_rdy_i         (data_port_fifo_rdy    ),
   .data_o             (data_o        )
  );
 
end
endgenerate
 
 
 
 
 
endmodule

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Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [example_design/] [rtl/] [traffic_gen/] [rd_data_gen.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`//*****************************************************************************`
2			`// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.`
3			`//`
4			`// This file contains confidential and proprietary information`
5			`// of Xilinx, Inc. and is protected under U.S. and`
6			`// international copyright and other intellectual property`
7			`// laws.`
8			`//`
9			`// DISCLAIMER`
10			`// This disclaimer is not a license and does not grant any`
11			`// rights to the materials distributed herewith. Except as`
12			`// otherwise provided in a valid license issued to you by`
13			`// Xilinx, and to the maximum extent permitted by applicable`
14			`// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
15			`// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
16			`// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
17			`// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
18			`// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
19			`// (2) Xilinx shall not be liable (whether in contract or tort,`
20			`// including negligence, or under any other theory of`
21			`// liability) for any loss or damage of any kind or nature`
22			`// related to, arising under or in connection with these`
23			`// materials, including for any direct, or any indirect,`
24			`// special, incidental, or consequential loss or damage`
25			`// (including loss of data, profits, goodwill, or any type of`
26			`// loss or damage suffered as a result of any action brought`
27			`// by a third party) even if such damage or loss was`
28			`// reasonably foreseeable or Xilinx had been advised of the`
29			`// possibility of the same.`
30			`//`
31			`// CRITICAL APPLICATIONS`
32			`// Xilinx products are not designed or intended to be fail-`
33			`// safe, or for use in any application requiring fail-safe`
34			`// performance, such as life-support or safety devices or`
35			`// systems, Class III medical devices, nuclear facilities,`
36			`// applications related to the deployment of airbags, or any`
37			`// other applications that could lead to death, personal`
38			`// injury, or severe property or environmental damage`
39			`// (individually and collectively, "Critical`
40			`// Applications"). Customer assumes the sole risk and`
41			`// liability of any use of Xilinx products in Critical`
42			`// Applications, subject only to applicable laws and`
43			`// regulations governing limitations on product liability.`
44			`//`
45			`// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
46			`// PART OF THIS FILE AT ALL TIMES.`
47			`//`
48			`//*****************************************************************************`
49			`// ____ ____`
50			`// / /\/ /`
51			`// /___/ \ / Vendor: Xilinx`
52			`// \ \ \/ Version: %version`
53			`// \ \ Application: MIG`
54			`// / / Filename: rd_data_gen.v`
55			`// /___/ /\ Date Last Modified:`
56			`// \ \ / \ Date Created:`
57			`// \___\/\___\`
58			`//`
59			`//Device: Spartan6`
60			`//Design Name: DDR/DDR2/DDR3/LPDDR`
61			`//Purpose: This module has all the timing control for generating "compare data"`
62			`// to compare the read data from memory.`
63			`//Reference:`
64			`//Revision History:`
65			`//*****************************************************************************`
66
67			`timescale 1ps/1ps
68
69			`module rd_data_gen #`
70			`(`
71			`parameter TCQ = 100,`
72			`parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6"`
73			`parameter MEM_BURST_LEN = 8,`
74
75			`parameter ADDR_WIDTH = 32,`
76			`parameter BL_WIDTH = 6,`
77			`parameter DWIDTH = 32,`
78			`parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"`
79			`parameter NUM_DQ_PINS = 8,`
80			`parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern`
81
82			`parameter COLUMN_WIDTH = 10`
83
84			`)`
85			`(`
86			`input clk_i, //`
87			`input [4:0] rst_i,`
88			`input [31:0] prbs_fseed_i,`
89			`input [3:0] data_mode_i, // "00" = bram;`
90
91			`output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.`
92			`// And then it should reasserted when`
93			`// it is generating the last_word.`
94			`input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.`
95			`output last_word_o,`
96
97			`// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.`
98			`input [DWIDTH-1:0] fixed_data_i,`
99			`input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.`
100			`input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data`
101			`output user_bl_cnt_is_1_o,`
102			`input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6`
103			`// connect from mcb_rd_empty when used as rd_data_gen in sp6`
104			`// connect from rd_data_valid in v6`
105			`// When both data_rdy and data_valid is asserted, the ouput data is valid.`
106			`output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the`
107			`// pattern is available.`
108			`output [DWIDTH-1:0] data_o, // generated data pattern`
109			`input rd_mdata_en`
110			`);`
111			`//`
112
113
114
115			`wire [31:0] prbs_data;`
116			`reg cmd_start;`
117			`reg [31:0] adata;`
118			`reg [31:0] hdata;`
119			`reg [31:0] ndata;`
120			`reg [31:0] w1data;`
121			`reg [NUM_DQ_PINS*4-1:0] v6_w1data;`
122
123			`reg [31:0] w0data;`
124			`reg [DWIDTH-1:0] data;`
125			`reg cmd_rdy;`
126			`reg data_valid;`
127			`reg [6:0]user_burst_cnt;`
128			`reg data_rdy_r1,data_rdy_r2;`
129			`reg next_count_is_one;`
130			`reg cmd_valid_r1;`
131			`reg [31:0] w3data;`
132
133			`assign data_port_fifo_rdy = data_rdy_i;`
134
135			`//assign cmd_start = cmd_valid_i & cmd_rdy ;`
136			`always @ (posedge clk_i)`
137			`begin`
138			`data_rdy_r1 <= #TCQ data_rdy_i;`
139			`data_rdy_r2 <= #TCQ data_rdy_r1;`
140			`cmd_valid_r1 <= #TCQ cmd_valid_i;`
141			`end`
142
143			`always @ (posedge clk_i)`
144			`begin`
145			`if (user_burst_cnt == 2 && data_rdy_i)`
146			`next_count_is_one <= #TCQ 1'b1;`
147			`else`
148			`next_count_is_one <= #TCQ 1'b0;`
149			`end`
150
151			`reg user_bl_cnt_is_1;`
152			`assign user_bl_cnt_is_1_o = user_bl_cnt_is_1;`
153			`always @ (posedge clk_i)`
154			`begin`
155			`if ((user_burst_cnt == 2 && data_port_fifo_rdy && FAMILY == "SPARTAN6")`
156			`\|\| (user_burst_cnt == 2 && data_port_fifo_rdy && FAMILY == "VIRTEX6")`
157			`)`
158
159			`user_bl_cnt_is_1 <= #TCQ 1'b1;`
160			`else`
161			`user_bl_cnt_is_1 <= #TCQ 1'b0;`
162			`end`
163
164
165			`reg cmd_start_b;`
166			`always @(cmd_valid_i,cmd_valid_r1,cmd_rdy,user_bl_cnt_is_1,rd_mdata_en)`
167			`begin`
168			`if (FAMILY == "SPARTAN6") begin`
169			`cmd_start = cmd_valid_i & cmd_rdy ;`
170			`cmd_start_b = cmd_valid_i & cmd_rdy ;`
171			`end`
172			`else if (MEM_BURST_LEN == 4 && FAMILY == "VIRTEX6") begin`
173			`cmd_start = rd_mdata_en; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface`
174			`cmd_start_b = rd_mdata_en; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface`
175			`end`
176			`else if (MEM_BURST_LEN == 8 && FAMILY == "VIRTEX6") begin`
177
178			`cmd_start = (~cmd_valid_r1 & cmd_valid_i) \| user_bl_cnt_is_1; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface`
179			`cmd_start_b = (~cmd_valid_r1 & cmd_valid_i) \| user_bl_cnt_is_1; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface`
180			`end`
181
182			`end`
183
184
185			`// counter to count user burst length`
186			`always @( posedge clk_i)`
187			`begin`
188			`if ( rst_i[0] )`
189			`user_burst_cnt <= #TCQ 'd0;`
190			`else if(cmd_start) begin`
191			`if (bl_i == 6'b000000)`
192			`user_burst_cnt <= #TCQ 7'b1000000;`
193			`else`
194			`user_burst_cnt <= #TCQ bl_i;`
195			`end`
196			`else if(data_port_fifo_rdy)`
197			`if (user_burst_cnt != 6'd0)`
198			`user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;`
199			`else`
200			`user_burst_cnt <= #TCQ 'd0;`
201
202			`end`
203
204			`reg u_bcount_2;`
205			`always @ (posedge clk_i)`
206			`begin`
207			`if ((user_burst_cnt == 2 && data_rdy_i )\|\| (cmd_start && bl_i == 1))`
208			`u_bcount_2 <= #TCQ 1'b1;`
209			`else if (last_word_o)`
210			`u_bcount_2 <= #TCQ 1'b0;`
211			`end`
212
213			`assign last_word_o = u_bcount_2 & data_rdy_i;`
214
215
216
217
218			`// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i`
219			`// is assert and reassert during the last data`
220
221			`//data_valid_o logic`
222
223
224
225			`assign cmd_rdy_o = cmd_rdy;`
226
227			`always @( posedge clk_i)`
228			`begin`
229			`if ( rst_i[0] )`
230			`cmd_rdy <= #TCQ 1'b1;`
231			`else if (cmd_start)`
232			`cmd_rdy <= #TCQ 1'b0;`
233			`else if ((data_port_fifo_rdy && user_burst_cnt == 1))`
234			`cmd_rdy <= #TCQ 1'b1;`
235
236
237			`end`
238
239
240
241			`always @ (posedge clk_i)`
242			`begin`
243			`if (rst_i[0])`
244			`data_valid <= #TCQ 'd0;`
245			`else if (user_burst_cnt == 6'd1 && data_port_fifo_rdy)`
246			`data_valid <= #TCQ 1'b0;`
247			`else if(( user_burst_cnt >= 6'd1) \|\| cmd_start)`
248			`data_valid <= #TCQ 1'b1;`
249			`end`
250
251
252			`always @ (data_valid, data_port_fifo_rdy)`
253			`if (FAMILY == "SPARTAN6")`
254			`data_valid_o = data_valid;`
255			`else`
256			`data_valid_o = data_port_fifo_rdy;`
257
258
259
260			`generate`
261			`if (FAMILY == "SPARTAN6") begin : SP6_DGEN`
262			`sp6_data_gen #`
263
264			`(`
265			`.TCQ (TCQ),`
266			`.ADDR_WIDTH (32 ),`
267			`.BL_WIDTH (BL_WIDTH ),`
268			`.DWIDTH (DWIDTH ),`
269			`.DATA_PATTERN (DATA_PATTERN ),`
270			`.NUM_DQ_PINS (NUM_DQ_PINS ),`
271			`.COLUMN_WIDTH (COLUMN_WIDTH)`
272
273			`)`
274			`sp6_data_gen`
275			`(`
276			`.clk_i (clk_i ),`
277			`.rst_i (rst_i[1] ),`
278			`.data_rdy_i (data_rdy_i ),`
279			`.prbs_fseed_i (prbs_fseed_i),`
280
281			`.data_mode_i (data_mode_i ),`
282			`.cmd_startA (cmd_start ),`
283			`.cmd_startB (cmd_start ),`
284			`.cmd_startC (cmd_start ),`
285			`.cmd_startD (cmd_start ),`
286			`.cmd_startE (cmd_start ),`
287			`.fixed_data_i (fixed_data_i),`
288
289			`.addr_i (addr_i ),`
290			`.user_burst_cnt (user_burst_cnt),`
291			`.fifo_rdy_i (data_port_fifo_rdy ),`
292			`.data_o (data_o )`
293			`);`
294
295			`end`
296			`endgenerate`
297			`generate`
298			`if (FAMILY == "VIRTEX6") begin : V6_DGEN`
299			`v6_data_gen #`
300
301			`(`
302			`.TCQ (TCQ),`
303			`.ADDR_WIDTH (32 ),`
304			`.BL_WIDTH (BL_WIDTH ),`
305			`.MEM_BURST_LEN (MEM_BURST_LEN),`
306			`.DWIDTH (DWIDTH ),`
307			`.DATA_PATTERN (DATA_PATTERN ),`
308			`.NUM_DQ_PINS (NUM_DQ_PINS ),`
309			`.SEL_VICTIM_LINE (SEL_VICTIM_LINE),`
310
311			`.COLUMN_WIDTH (COLUMN_WIDTH)`
312
313			`)`
314			`v6_data_gen`
315			`(`
316			`.clk_i (clk_i ),`
317			`.rst_i (rst_i[1] ),`
318			`.data_rdy_i (data_rdy_i ),`
319			`.prbs_fseed_i (prbs_fseed_i),`
320
321			`.data_mode_i (data_mode_i ),`
322			`.cmd_startA (cmd_start ),`
323			`.cmd_startB (cmd_start ),`
324			`.cmd_startC (cmd_start ),`
325			`.cmd_startD (cmd_start ),`
326			`.cmd_startE (cmd_start ),`
327			`.m_addr_i (addr_i),//(m_addr_i ),`
328			`.fixed_data_i (fixed_data_i),`
329
330			`.addr_i (addr_i ),`
331			`.user_burst_cnt (user_burst_cnt),`
332			`.fifo_rdy_i (data_port_fifo_rdy ),`
333			`.data_o (data_o )`
334			`);`
335
336			`end`
337			`endgenerate`
338
339
340
341
342
343			`endmodule`