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//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: %version
//  \   \         Application: MIG
//  /   /         Filename: wr_data_gen.v
// /___/   /\     Date Last Modified: 
// \   \  /  \    Date Created: 
//  \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR 
//Purpose:
//Reference:
//Revision History:
//*****************************************************************************
 
`timescale 1ps/1ps
 
module wr_data_gen #
 
(
   parameter TCQ           = 100,
   parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6"
   parameter MEM_BURST_LEN = 8,
 
   parameter MODE  = "WR", //"WR", "RD"
   parameter ADDR_WIDTH = 32,
   parameter BL_WIDTH = 6,
   parameter DWIDTH = 32,
   parameter DATA_PATTERN = "DGEN_PRBS", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
   parameter NUM_DQ_PINS   = 8,
   parameter SEL_VICTIM_LINE = 3,  // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
 
   parameter COLUMN_WIDTH = 10,
   parameter EYE_TEST   = "FALSE"
 
 )
 (
   input   clk_i,                 //
   input [4:0]  rst_i,
   input [31:0] prbs_fseed_i,
 
   input [3:0]  data_mode_i,   // "00" = bram; 
 
   output  cmd_rdy_o,             // ready to receive command. It should assert when data_port is ready at the                                        // beginning and will be deasserted once see the cmd_valid_i is asserted. 
                                  // And then it should reasserted when 
                                  // it is generating the last_word.
   input   cmd_valid_i,           // when both cmd_valid_i and cmd_rdy_o is high, the command  is valid.
   input   cmd_validB_i,
   input   cmd_validC_i,
 
   output  last_word_o,
 
 //  input [5:0] port_data_counts_i,// connect to data port fifo counts
//   input [ADDR_WIDTH-1:0] m_addr_i,
   input [DWIDTH-1:0] fixed_data_i,
 
   input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
   input [BL_WIDTH-1:0]   bl_i,   // generated burst length for control the burst data
 
   input   data_rdy_i,          // connect from mcb_wr_full when used as wr_data_gen
                                 // connect from mcb_rd_empty when used as rd_data_gen
                                 // When both data_rdy and data_valid is asserted, the ouput data is valid.
   output    data_valid_o,        // connect to wr_en or rd_en and is asserted whenever the 
                                 // pattern is available.
   output  [DWIDTH-1:0] data_o, // generated data pattern   
   output  reg          data_wr_end_o
 
 
);
// 
 
 
reg [DWIDTH-1:0] data;
 
 
 
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg   cmd_rdy,cmd_rdyB, cmd_rdyC,cmd_rdyD,cmd_rdyE,cmd_rdyF;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg   cmd_start,cmd_startB,cmd_startC,cmd_startD,cmd_startE,cmd_startF;
 
 
 
 
reg burst_count_reached2;
 
reg               data_valid;
reg [6:0]user_burst_cnt;
reg [2:0] walk_cnt;
 
wire fifo_not_full;
integer i,j;
reg [31:0] w3data;
 
assign fifo_not_full = data_rdy_i;
 
always @( posedge clk_i)
begin
if ((user_burst_cnt == 2 || (cmd_start && bl_i == 1 && FAMILY == "VIRTEX6")) && (fifo_not_full))
    data_wr_end_o <= #TCQ  1'b1;
else
    data_wr_end_o <= #TCQ  1'b0;
end
 
always @ (posedge clk_i)
begin
cmd_start  <= #TCQ  cmd_validC_i & cmd_rdyC ;
cmd_startB <= #TCQ  cmd_valid_i & cmd_rdyB;
cmd_startC <= #TCQ  cmd_validB_i & cmd_rdyC;
cmd_startD <= #TCQ  cmd_validB_i & cmd_rdyD;
cmd_startE <= #TCQ  cmd_validB_i & cmd_rdyE;
cmd_startF <= #TCQ  cmd_validB_i & cmd_rdyF;
end
 
 
// counter to count user burst length
always @( posedge clk_i)
begin
  if ( rst_i[0] )
    user_burst_cnt <= #TCQ 'd0;
  else if(cmd_start)
    if (FAMILY == "SPARTAN6") begin
       if (bl_i == 6'b000000)
          user_burst_cnt <= #TCQ 7'b1000000;
       else
     user_burst_cnt <= #TCQ bl_i;
 
       end
        else
     user_burst_cnt <= #TCQ bl_i;
  else if(fifo_not_full)
     if (user_burst_cnt != 6'd0)
       user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
     else
        user_burst_cnt <=#TCQ 'd0;
 
end
 
reg u_bcount_2;
wire last_word_t;
always @ (posedge clk_i)
begin
if ((user_burst_cnt == 2  && fifo_not_full )|| (cmd_startC && bl_i == 1))
    u_bcount_2 <= #TCQ 1'b1;
else if (last_word_o)
    u_bcount_2 <= #TCQ 1'b0;
end
 
 
 
assign  last_word_o = u_bcount_2 & fifo_not_full;
 
// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
// is assert and reassert during the last data
 
assign cmd_rdy_o = cmd_rdy & fifo_not_full;
 
 
always @( posedge clk_i)
begin
  if ( rst_i[0] )
    cmd_rdy <= #TCQ 1'b1;
  else if (cmd_start)
     if (bl_i == 1)
        cmd_rdy <= #TCQ 1'b1;
     else
       cmd_rdy <= #TCQ 1'b0;
  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
 
      cmd_rdy <= #TCQ 1'b1;
 
 
end
 
always @( posedge clk_i)
begin
  if ( rst_i [0])
    cmd_rdyB <= #TCQ 1'b1;
  else if (cmd_startB)
     if (bl_i == 1)
        cmd_rdyB <= #TCQ 1'b1;
     else
       cmd_rdyB <= #TCQ 1'b0;
  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
 
 
      cmd_rdyB <= #TCQ 1'b1;
 
 
end
 
always @( posedge clk_i)
begin
  if ( rst_i[0] )
    cmd_rdyC <= #TCQ 1'b1;
  else if (cmd_startC)
     if (bl_i == 1)
        cmd_rdyC <= #TCQ 1'b1;
     else
       cmd_rdyC <= #TCQ 1'b0;
  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
 
 
      cmd_rdyC <= #TCQ 1'b1;
 
 
end
 
always @( posedge clk_i)
begin
  if ( rst_i[0] )
    cmd_rdyD <= #TCQ 1'b1;
  else if (cmd_startD)
     if (bl_i == 1)
        cmd_rdyD <= #TCQ  1'b1;
     else
       cmd_rdyD <= #TCQ 1'b0;
  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
 
 
      cmd_rdyD <= #TCQ 1'b1;
 
 
end
 
always @( posedge clk_i)
begin
  if ( rst_i[0] )
    cmd_rdyE <= #TCQ 1'b1;
  else if (cmd_startE)
     if (bl_i == 1)
        cmd_rdyE <= #TCQ 1'b1;
     else
       cmd_rdyE <= #TCQ 1'b0;
  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
 
 
      cmd_rdyE <= #TCQ 1'b1;
 
 
end
 
 
 
always @( posedge clk_i)
begin
  if ( rst_i[0] )
    cmd_rdyF <= #TCQ 1'b1;
  else if (cmd_startF)
     if (bl_i == 1)
        cmd_rdyF <= #TCQ 1'b1;
     else
       cmd_rdyF <= #TCQ 1'b0;
  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
 
      cmd_rdyF <= #TCQ 1'b1;
 
 
end
 
 
 
always @ (posedge clk_i)
begin
  if (rst_i[1])
    data_valid <= #TCQ 'd0;
  else if(cmd_start)
    data_valid <= #TCQ 1'b1;
  else if (fifo_not_full && user_burst_cnt <= 6'd1)
    data_valid <= #TCQ 1'b0;
end
 
assign data_valid_o = data_valid & fifo_not_full;
 
 
generate
if (FAMILY == "SPARTAN6")  begin : SP6_WDGEN
 
sp6_data_gen #
 
(
   .TCQ             (TCQ),
   .ADDR_WIDTH      (32 ),
 
   .BL_WIDTH        (BL_WIDTH       ),
   .DWIDTH          (DWIDTH       ),
   .DATA_PATTERN    (DATA_PATTERN  ),
   .NUM_DQ_PINS      (NUM_DQ_PINS  ),
   .COLUMN_WIDTH     (COLUMN_WIDTH)
 
 )
 sp6_data_gen
 (
   .clk_i              (clk_i         ),
   .rst_i              (rst_i[1]         ),
   .data_rdy_i         (data_rdy_i    ),
   .prbs_fseed_i       (prbs_fseed_i),
 
   .data_mode_i        (data_mode_i   ),
   .cmd_startA         (cmd_start    ),
   .cmd_startB         (cmd_startB    ),
   .cmd_startC         (cmd_startC    ),
   .cmd_startD         (cmd_startD    ),
   .cmd_startE         (cmd_startE    ),
   .fixed_data_i         (fixed_data_i),
 
   .addr_i             (addr_i        ),
   .user_burst_cnt     (user_burst_cnt),
   .fifo_rdy_i         (fifo_not_full    ),
   .data_o             (data_o        )
  );
end
 
 
endgenerate
 
generate
if (FAMILY ==  "VIRTEX6")  begin : V6_WDGEN
 
v6_data_gen #
 
(
   .TCQ               (TCQ),
   .ADDR_WIDTH      (32 ),
   .BL_WIDTH        (BL_WIDTH       ),
   .DWIDTH          (DWIDTH       ),
   .MEM_BURST_LEN     (MEM_BURST_LEN),
 
   .DATA_PATTERN    (DATA_PATTERN  ),
   .NUM_DQ_PINS      (NUM_DQ_PINS  ),
   .SEL_VICTIM_LINE   (SEL_VICTIM_LINE),
 
   .COLUMN_WIDTH     (COLUMN_WIDTH),
    .EYE_TEST   (EYE_TEST)
 
 )
 v6_data_gen
 (
   .clk_i              (clk_i         ),
   .rst_i              (rst_i[1]      ),
   .data_rdy_i         (data_rdy_i    ),
   .prbs_fseed_i       (prbs_fseed_i),
 
   .data_mode_i        (data_mode_i   ),
   .cmd_startA         (cmd_start    ),
   .cmd_startB         (cmd_startB    ),
   .cmd_startC         (cmd_startC    ),
   .cmd_startD         (cmd_startD    ),
   .cmd_startE         (cmd_startE    ),
   .m_addr_i           (addr_i/*m_addr_i*/),
   .fixed_data_i         (fixed_data_i),
 
   .addr_i             (addr_i        ),
   .user_burst_cnt     (user_burst_cnt),
   .fifo_rdy_i         (fifo_not_full    ),
   .data_o             (data_o        )
  );
end
endgenerate
 
 
endmodule

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Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [example_design/] [rtl/] [traffic_gen/] [wr_data_gen.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`//*****************************************************************************`
2			`// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.`
3			`//`
4			`// This file contains confidential and proprietary information`
5			`// of Xilinx, Inc. and is protected under U.S. and`
6			`// international copyright and other intellectual property`
7			`// laws.`
8			`//`
9			`// DISCLAIMER`
10			`// This disclaimer is not a license and does not grant any`
11			`// rights to the materials distributed herewith. Except as`
12			`// otherwise provided in a valid license issued to you by`
13			`// Xilinx, and to the maximum extent permitted by applicable`
14			`// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
15			`// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
16			`// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
17			`// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
18			`// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
19			`// (2) Xilinx shall not be liable (whether in contract or tort,`
20			`// including negligence, or under any other theory of`
21			`// liability) for any loss or damage of any kind or nature`
22			`// related to, arising under or in connection with these`
23			`// materials, including for any direct, or any indirect,`
24			`// special, incidental, or consequential loss or damage`
25			`// (including loss of data, profits, goodwill, or any type of`
26			`// loss or damage suffered as a result of any action brought`
27			`// by a third party) even if such damage or loss was`
28			`// reasonably foreseeable or Xilinx had been advised of the`
29			`// possibility of the same.`
30			`//`
31			`// CRITICAL APPLICATIONS`
32			`// Xilinx products are not designed or intended to be fail-`
33			`// safe, or for use in any application requiring fail-safe`
34			`// performance, such as life-support or safety devices or`
35			`// systems, Class III medical devices, nuclear facilities,`
36			`// applications related to the deployment of airbags, or any`
37			`// other applications that could lead to death, personal`
38			`// injury, or severe property or environmental damage`
39			`// (individually and collectively, "Critical`
40			`// Applications"). Customer assumes the sole risk and`
41			`// liability of any use of Xilinx products in Critical`
42			`// Applications, subject only to applicable laws and`
43			`// regulations governing limitations on product liability.`
44			`//`
45			`// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
46			`// PART OF THIS FILE AT ALL TIMES.`
47			`//`
48			`//*****************************************************************************`
49			`// ____ ____`
50			`// / /\/ /`
51			`// /___/ \ / Vendor: Xilinx`
52			`// \ \ \/ Version: %version`
53			`// \ \ Application: MIG`
54			`// / / Filename: wr_data_gen.v`
55			`// /___/ /\ Date Last Modified:`
56			`// \ \ / \ Date Created:`
57			`// \___\/\___\`
58			`//`
59			`//Device: Spartan6`
60			`//Design Name: DDR/DDR2/DDR3/LPDDR`
61			`//Purpose:`
62			`//Reference:`
63			`//Revision History:`
64			`//*****************************************************************************`
65
66			`timescale 1ps/1ps
67
68			`module wr_data_gen #`
69
70			`(`
71			`parameter TCQ = 100,`
72			`parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6"`
73			`parameter MEM_BURST_LEN = 8,`
74
75			`parameter MODE = "WR", //"WR", "RD"`
76			`parameter ADDR_WIDTH = 32,`
77			`parameter BL_WIDTH = 6,`
78			`parameter DWIDTH = 32,`
79			`parameter DATA_PATTERN = "DGEN_PRBS", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"`
80			`parameter NUM_DQ_PINS = 8,`
81			`parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern`
82
83			`parameter COLUMN_WIDTH = 10,`
84			`parameter EYE_TEST = "FALSE"`
85
86			`)`
87			`(`
88			`input clk_i, //`
89			`input [4:0] rst_i,`
90			`input [31:0] prbs_fseed_i,`
91
92			`input [3:0] data_mode_i, // "00" = bram;`
93
94			`output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.`
95			`// And then it should reasserted when`
96			`// it is generating the last_word.`
97			`input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.`
98			`input cmd_validB_i,`
99			`input cmd_validC_i,`
100
101			`output last_word_o,`
102
103			`// input [5:0] port_data_counts_i,// connect to data port fifo counts`
104			`// input [ADDR_WIDTH-1:0] m_addr_i,`
105			`input [DWIDTH-1:0] fixed_data_i,`
106
107			`input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.`
108			`input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data`
109
110			`input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen`
111			`// connect from mcb_rd_empty when used as rd_data_gen`
112			`// When both data_rdy and data_valid is asserted, the ouput data is valid.`
113			`output data_valid_o, // connect to wr_en or rd_en and is asserted whenever the`
114			`// pattern is available.`
115			`output [DWIDTH-1:0] data_o, // generated data pattern`
116			`output reg data_wr_end_o`
117
118
119			`);`
120			`//`
121
122
123			`reg [DWIDTH-1:0] data;`
124
125
126
127			`(EQUIVALENT_REGISTER_REMOVAL="NO") reg cmd_rdy,cmd_rdyB, cmd_rdyC,cmd_rdyD,cmd_rdyE,cmd_rdyF;`
128			`(EQUIVALENT_REGISTER_REMOVAL="NO") reg cmd_start,cmd_startB,cmd_startC,cmd_startD,cmd_startE,cmd_startF;`
129
130
131
132
133			`reg burst_count_reached2;`
134
135			`reg data_valid;`
136			`reg [6:0]user_burst_cnt;`
137			`reg [2:0] walk_cnt;`
138
139			`wire fifo_not_full;`
140			`integer i,j;`
141			`reg [31:0] w3data;`
142
143			`assign fifo_not_full = data_rdy_i;`
144
145			`always @( posedge clk_i)`
146			`begin`
147			`if ((user_burst_cnt == 2 \|\| (cmd_start && bl_i == 1 && FAMILY == "VIRTEX6")) && (fifo_not_full))`
148			`data_wr_end_o <= #TCQ 1'b1;`
149			`else`
150			`data_wr_end_o <= #TCQ 1'b0;`
151			`end`
152
153			`always @ (posedge clk_i)`
154			`begin`
155			`cmd_start <= #TCQ cmd_validC_i & cmd_rdyC ;`
156			`cmd_startB <= #TCQ cmd_valid_i & cmd_rdyB;`
157			`cmd_startC <= #TCQ cmd_validB_i & cmd_rdyC;`
158			`cmd_startD <= #TCQ cmd_validB_i & cmd_rdyD;`
159			`cmd_startE <= #TCQ cmd_validB_i & cmd_rdyE;`
160			`cmd_startF <= #TCQ cmd_validB_i & cmd_rdyF;`
161			`end`
162
163
164			`// counter to count user burst length`
165			`always @( posedge clk_i)`
166			`begin`
167			`if ( rst_i[0] )`
168			`user_burst_cnt <= #TCQ 'd0;`
169			`else if(cmd_start)`
170			`if (FAMILY == "SPARTAN6") begin`
171			`if (bl_i == 6'b000000)`
172			`user_burst_cnt <= #TCQ 7'b1000000;`
173			`else`
174			`user_burst_cnt <= #TCQ bl_i;`
175
176			`end`
177			`else`
178			`user_burst_cnt <= #TCQ bl_i;`
179			`else if(fifo_not_full)`
180			`if (user_burst_cnt != 6'd0)`
181			`user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;`
182			`else`
183			`user_burst_cnt <=#TCQ 'd0;`
184
185			`end`
186
187			`reg u_bcount_2;`
188			`wire last_word_t;`
189			`always @ (posedge clk_i)`
190			`begin`
191			`if ((user_burst_cnt == 2 && fifo_not_full )\|\| (cmd_startC && bl_i == 1))`
192			`u_bcount_2 <= #TCQ 1'b1;`
193			`else if (last_word_o)`
194			`u_bcount_2 <= #TCQ 1'b0;`
195			`end`
196
197
198
199			`assign last_word_o = u_bcount_2 & fifo_not_full;`
200
201			`// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i`
202			`// is assert and reassert during the last data`
203
204			`assign cmd_rdy_o = cmd_rdy & fifo_not_full;`
205
206
207			`always @( posedge clk_i)`
208			`begin`
209			`if ( rst_i[0] )`
210			`cmd_rdy <= #TCQ 1'b1;`
211			`else if (cmd_start)`
212			`if (bl_i == 1)`
213			`cmd_rdy <= #TCQ 1'b1;`
214			`else`
215			`cmd_rdy <= #TCQ 1'b0;`
216			`else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )`
217
218			`cmd_rdy <= #TCQ 1'b1;`
219
220
221			`end`
222
223			`always @( posedge clk_i)`
224			`begin`
225			`if ( rst_i [0])`
226			`cmd_rdyB <= #TCQ 1'b1;`
227			`else if (cmd_startB)`
228			`if (bl_i == 1)`
229			`cmd_rdyB <= #TCQ 1'b1;`
230			`else`
231			`cmd_rdyB <= #TCQ 1'b0;`
232			`else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )`
233
234
235			`cmd_rdyB <= #TCQ 1'b1;`
236
237
238			`end`
239
240			`always @( posedge clk_i)`
241			`begin`
242			`if ( rst_i[0] )`
243			`cmd_rdyC <= #TCQ 1'b1;`
244			`else if (cmd_startC)`
245			`if (bl_i == 1)`
246			`cmd_rdyC <= #TCQ 1'b1;`
247			`else`
248			`cmd_rdyC <= #TCQ 1'b0;`
249			`else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )`
250
251
252			`cmd_rdyC <= #TCQ 1'b1;`
253
254
255			`end`
256
257			`always @( posedge clk_i)`
258			`begin`
259			`if ( rst_i[0] )`
260			`cmd_rdyD <= #TCQ 1'b1;`
261			`else if (cmd_startD)`
262			`if (bl_i == 1)`
263			`cmd_rdyD <= #TCQ 1'b1;`
264			`else`
265			`cmd_rdyD <= #TCQ 1'b0;`
266			`else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )`
267
268
269			`cmd_rdyD <= #TCQ 1'b1;`
270
271
272			`end`
273
274			`always @( posedge clk_i)`
275			`begin`
276			`if ( rst_i[0] )`
277			`cmd_rdyE <= #TCQ 1'b1;`
278			`else if (cmd_startE)`
279			`if (bl_i == 1)`
280			`cmd_rdyE <= #TCQ 1'b1;`
281			`else`
282			`cmd_rdyE <= #TCQ 1'b0;`
283			`else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )`
284
285
286			`cmd_rdyE <= #TCQ 1'b1;`
287
288
289			`end`
290
291
292
293			`always @( posedge clk_i)`
294			`begin`
295			`if ( rst_i[0] )`
296			`cmd_rdyF <= #TCQ 1'b1;`
297			`else if (cmd_startF)`
298			`if (bl_i == 1)`
299			`cmd_rdyF <= #TCQ 1'b1;`
300			`else`
301			`cmd_rdyF <= #TCQ 1'b0;`
302			`else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )`
303
304			`cmd_rdyF <= #TCQ 1'b1;`
305
306
307			`end`
308
309
310
311			`always @ (posedge clk_i)`
312			`begin`
313			`if (rst_i[1])`
314			`data_valid <= #TCQ 'd0;`
315			`else if(cmd_start)`
316			`data_valid <= #TCQ 1'b1;`
317			`else if (fifo_not_full && user_burst_cnt <= 6'd1)`
318			`data_valid <= #TCQ 1'b0;`
319			`end`
320
321			`assign data_valid_o = data_valid & fifo_not_full;`
322
323
324			`generate`
325			`if (FAMILY == "SPARTAN6") begin : SP6_WDGEN`
326
327			`sp6_data_gen #`
328
329			`(`
330			`.TCQ (TCQ),`
331			`.ADDR_WIDTH (32 ),`
332
333			`.BL_WIDTH (BL_WIDTH ),`
334			`.DWIDTH (DWIDTH ),`
335			`.DATA_PATTERN (DATA_PATTERN ),`
336			`.NUM_DQ_PINS (NUM_DQ_PINS ),`
337			`.COLUMN_WIDTH (COLUMN_WIDTH)`
338
339			`)`
340			`sp6_data_gen`
341			`(`
342			`.clk_i (clk_i ),`
343			`.rst_i (rst_i[1] ),`
344			`.data_rdy_i (data_rdy_i ),`
345			`.prbs_fseed_i (prbs_fseed_i),`
346
347			`.data_mode_i (data_mode_i ),`
348			`.cmd_startA (cmd_start ),`
349			`.cmd_startB (cmd_startB ),`
350			`.cmd_startC (cmd_startC ),`
351			`.cmd_startD (cmd_startD ),`
352			`.cmd_startE (cmd_startE ),`
353			`.fixed_data_i (fixed_data_i),`
354
355			`.addr_i (addr_i ),`
356			`.user_burst_cnt (user_burst_cnt),`
357			`.fifo_rdy_i (fifo_not_full ),`
358			`.data_o (data_o )`
359			`);`
360			`end`
361
362
363			`endgenerate`
364
365			`generate`
366			`if (FAMILY == "VIRTEX6") begin : V6_WDGEN`
367
368			`v6_data_gen #`
369
370			`(`
371			`.TCQ (TCQ),`
372			`.ADDR_WIDTH (32 ),`
373			`.BL_WIDTH (BL_WIDTH ),`
374			`.DWIDTH (DWIDTH ),`
375			`.MEM_BURST_LEN (MEM_BURST_LEN),`
376
377			`.DATA_PATTERN (DATA_PATTERN ),`
378			`.NUM_DQ_PINS (NUM_DQ_PINS ),`
379			`.SEL_VICTIM_LINE (SEL_VICTIM_LINE),`
380
381			`.COLUMN_WIDTH (COLUMN_WIDTH),`
382			`.EYE_TEST (EYE_TEST)`
383
384			`)`
385			`v6_data_gen`
386			`(`
387			`.clk_i (clk_i ),`
388			`.rst_i (rst_i[1] ),`
389			`.data_rdy_i (data_rdy_i ),`
390			`.prbs_fseed_i (prbs_fseed_i),`
391
392			`.data_mode_i (data_mode_i ),`
393			`.cmd_startA (cmd_start ),`
394			`.cmd_startB (cmd_startB ),`
395			`.cmd_startC (cmd_startC ),`
396			`.cmd_startD (cmd_startD ),`
397			`.cmd_startE (cmd_startE ),`
398			`.m_addr_i (addr_i/m_addr_i/),`
399			`.fixed_data_i (fixed_data_i),`
400
401			`.addr_i (addr_i ),`
402			`.user_burst_cnt (user_burst_cnt),`
403			`.fifo_rdy_i (fifo_not_full ),`
404			`.data_o (data_o )`
405			`);`
406			`end`
407			`endgenerate`
408
409
410			`endmodule`