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/****************************************************************************************

*

*    File Name:  ddr.v

*      Version:  6.00

*        Model:  BUS Functional

*

* Dependencies:  ddr_model_parameters.vh

*

*  Description:  Micron SDRAM DDR (Double Data Rate)

*

*   Limitation:  - Doesn't check for 8K-cycle refresh.

*                - Doesn't check power-down entry/exit

*                - Doesn't check self-refresh entry/exit.

*

*         Note:  - Set simulator resolution to "ps" accuracy

*                - Set DEBUG = 0 to disable $display messages

*                - Model assume Clk and Clk# crossing at both edge

*

*   Disclaimer   This software code and all associated documentation, comments or other

*  of Warranty:  information (collectively "Software") is provided "AS IS" without

*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY

*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED

*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES

*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT

*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE

*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.

*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR

*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,

*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE

*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,

*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,

*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,

*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,

*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE

*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

*                DAMAGES. Because some jurisdictions prohibit the exclusion or

*                limitation of liability for consequential or incidental damages, the

*                above limitation may not apply to you.

*

*                Copyright 2003 Micron Technology, Inc. All rights reserved.

*

* Rev  Author Date        Changes

* ---  ------ ----------  ---------------------------------------

* 2.1   SPH    03/19/2002  - Second Release

*                          - Fix tWR and several incompatability

*                            between different simulators

* 3.0   TFK    02/18/2003  - Added tDSS and tDSH timing checks.

*                          - Added tDQSH and tDQSL timing checks.

* 3.1   CAH    05/28/2003  - update all models to release version 3.1

*                            (no changes to this model)

* 3.2   JMK    06/16/2003  - updated all DDR400 models to support CAS Latency 3

* 3.3   JMK    09/11/2003  - Added initialization sequence checks.

* 4.0   JMK    12/01/2003  - Grouped parameters into "ddr_parameters.v"

*                          - Fixed tWTR check

* 4.1   JMK    01/14/2004  - Grouped specify parameters by speed grade

*                          - Fixed mem_sizes parameter

* 4.2   JMK    03/19/2004  - Fixed pulse width checking on Dqs

* 4.3   JMK    04/27/2004  - Changed BL wire size in tb module

*                          - Changed Dq_buf size to [15:0]

* 5.0   JMK    06/16/2004  - Added read to write checking.

*                          - Added read with precharge truncation to write checking.

*                          - Added associative memory array to reduce memory consumption.

*                          - Added checking for required DQS edges during write.

* 5.1   JMK    08/16/2004  - Fixed checking for required DQS edges during write.

*                          - Fixed wdqs_valid window.

* 5.2   JMK    09/24/2004  - Read or Write without activate will be ignored.

* 5.3   JMK    10/27/2004  - Added tMRD checking during Auto Refresh and Activate.

*                          - Added tRFC checking during Load Mode and Precharge.

* 5.4   JMK    12/13/2004  - The model will not respond to illegal command sequences.

* 5.5   SPH    01/13/2005  - The model will issue a halt on illegal command sequences.

*       JMK    02/11/2005  - Changed the display format for numbers to hex.

* 5.6   JMK    04/22/2005  - Fixed Write with auto precharge calculation.

* 5.7   JMK    08/05/2005  - Changed conditions for read with precharge truncation error.

*                          - Renamed parameters file with .vh extension.

* 5.8   BAS    12/26/2006  - Added parameters for T46A part - 256Mb

*                          - Added x32 functionality

* 6.00  JMK    05/31/2007  - Added ddr_184_dimm module model

* 6.00  BAS    05/31/2007  - Updated 128Mb, 256Mb, 512Mb, and 1024Mb parameter sheets

****************************************************************************************/

// DO NOT CHANGE THE TIMESCALE

// MAKE SURE YOUR SIMULATOR USE "PS" RESOLUTION

`timescale 1ns / 1ps

module ddr_model_c3 (Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Ba , Addr, Dm, Dq, Dqs);

    `include "ddr_model_parameters_c3.vh"

    // Port Declarations

    input                         Clk;

    input                         Clk_n;

    input                         Cke;

    input                         Cs_n;

    input                         Ras_n;

    input                         Cas_n;

    input                         We_n;

    input                 [1 : 0] Ba;

    input     [ADDR_BITS - 1 : 0] Addr;

    input       [DM_BITS - 1 : 0] Dm;

    inout       [DQ_BITS - 1 : 0] Dq;

    inout      [DQS_BITS - 1 : 0] Dqs;

    // Internal Wires (fixed width)

    wire                 [31 : 0] Dq_in;

    wire                  [3 : 0] Dqs_in;

    wire                  [3 : 0] Dm_in;

    assign Dq_in   [DQ_BITS - 1 : 0] = Dq;

    assign Dqs_in [DQS_BITS - 1 : 0] = Dqs;

    assign Dm_in   [DM_BITS - 1 : 0] = Dm;

    // Data pair

    reg                  [31 : 0] dq_rise;

    reg                   [3 : 0] dm_rise;

    reg                  [31 : 0] dq_fall;

    reg                   [3 : 0] dm_fall;

    reg                   [7 : 0] dm_pair;

    reg                  [31 : 0] Dq_buf;

    // Mode Register

    reg       [ADDR_BITS - 1 : 0] Mode_reg;

    // Internal System Clock

    reg                           CkeZ, Sys_clk;

    // Internal Dqs initialize

    reg                           Dqs_int;

    // Dqs buffer

    reg        [DQS_BITS - 1 : 0] Dqs_out;

    // Dq buffer

    reg         [DQ_BITS - 1 : 0] Dq_out;

    // Read pipeline variables

    reg                           Read_cmnd [0 : 6];

    reg                   [1 : 0] Read_bank [0 : 6];

    reg        [COL_BITS - 1 : 0] Read_cols [0 : 6];

    // Write pipeline variables

    reg                           Write_cmnd [0 : 3];

    reg                   [1 : 0] Write_bank [0 : 3];

    reg        [COL_BITS - 1 : 0] Write_cols [0 : 3];

    // Auto precharge variables

    reg                           Read_precharge  [0 : 3];

    reg                           Write_precharge [0 : 3];

    integer                       Count_precharge [0 : 3];

    // Manual precharge variables

    reg                           A10_precharge  [0 : 6];

    reg                   [1 : 0] Bank_precharge [0 : 6];

    reg                           Cmnd_precharge [0 : 6];

    // Burst terminate variables

    reg                           Cmnd_bst [0 : 6];

    // Memory Banks

`ifdef FULL_MEM

    reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<full_mem_bits)-1];

`else

    reg         [DQ_BITS - 1 : 0] mem_array  [0 : (1<<part_mem_bits)-1];

    reg   [full_mem_bits - 1 : 0] addr_array [0 : (1<<part_mem_bits)-1];

    reg   [part_mem_bits     : 0] mem_used;

    initial mem_used = 0;

`endif

    // Dqs edge checking

    integer i;

    reg  [3 :0] expect_pos_dqs;

    reg  [3 :0] expect_neg_dqs;

    // Burst counter

    reg        [COL_BITS - 1 : 0] Burst_counter;

    // Precharge variables

    reg                           Pc_b0, Pc_b1, Pc_b2, Pc_b3;

    // Activate variables

    reg                           Act_b0, Act_b1, Act_b2, Act_b3;

    // Data IO variables

    reg                           Data_in_enable;

    reg                           Data_out_enable;

    // Internal address mux variables

    reg                   [1 : 0] Prev_bank;

    reg                   [1 : 0] Bank_addr;

    reg        [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp;

    reg       [ADDR_BITS - 1 : 0] Rows_addr;

    reg       [ADDR_BITS - 1 : 0] B0_row_addr;

    reg       [ADDR_BITS - 1 : 0] B1_row_addr;

    reg       [ADDR_BITS - 1 : 0] B2_row_addr;

    reg       [ADDR_BITS - 1 : 0] B3_row_addr;

    // DLL Reset variable

    reg                           DLL_enable;

    reg                           DLL_reset;

    reg                           DLL_done;

    integer                       DLL_count;

    integer                       aref_count;

    integer                       Prech_count;

    reg                           power_up_done;

    // Write DQS for tDSS, tDSH, tDQSH, tDQSL checks

    wire      wdqs_valid = Write_cmnd[2] || Write_cmnd[1] || Data_in_enable;

    // Commands Decode

    wire      Active_enable   = ~Cs_n & ~Ras_n &  Cas_n &  We_n;

    wire      Aref_enable     = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;

    wire      Burst_term      = ~Cs_n &  Ras_n &  Cas_n & ~We_n;

    wire      Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n &  Ba[0] & ~Ba[1];

    wire      Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[0] & ~Ba[1];

    wire      Prech_enable    = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;

    wire      Read_enable     = ~Cs_n &  Ras_n & ~Cas_n &  We_n;

    wire      Write_enable    = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;

    // Burst Length Decode

    wire [3:0] burst_length = 1 << (Mode_reg[2:0]);

    reg  [3:0] read_precharge_truncation;

    // CAS Latency Decode

    wire [2:0] cas_latency_x2 = (Mode_reg[6:4] === 3'o6) ? 5 : 2*Mode_reg[6:4];

    // DQS Buffer

    assign    Dqs = Dqs_out;

    // DQ Buffer

    assign    Dq  = Dq_out;

    // Timing Check

    time      MRD_chk;

    time      RFC_chk;

    time      RRD_chk;

    time      RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;

    time      RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3;

    time      RC_chk0, RC_chk1, RC_chk2, RC_chk3;

    time      RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;

    time      RP_chk0, RP_chk1, RP_chk2, RP_chk3;

    time      WR_chk0, WR_chk1, WR_chk2, WR_chk3;

    initial begin

        CkeZ = 1'b0;

        Sys_clk = 1'b0;

        {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000;

        {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111;

        Dqs_int = 1'b0;

        Dqs_out = {DQS_BITS{1'bz}};

        Dq_out = {DQ_BITS{1'bz}};

        Data_in_enable = 1'b0;

        Data_out_enable = 1'b0;

        DLL_enable = 1'b0;

        DLL_reset = 1'b0;

        DLL_done = 1'b0;

        DLL_count = 0;

        aref_count = 0;

        Prech_count = 0;

        power_up_done = 0;

        MRD_chk = 0;

        RFC_chk = 0;

        RRD_chk = 0;

        {RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3} = 0;

        {RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3} = 0;

        {RC_chk0, RC_chk1, RC_chk2, RC_chk3} = 0;

        {RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3} = 0;

        {RP_chk0, RP_chk1, RP_chk2, RP_chk3} = 0;

        {WR_chk0, WR_chk1, WR_chk2, WR_chk3} = 0;

        $timeformat (-9, 3, " ns", 12);

    end

    // System Clock

    always begin

        @ (posedge Clk) begin

            Sys_clk = CkeZ;

            CkeZ = Cke;

        end

        @ (negedge Clk) begin

            Sys_clk = 1'b0;

        end

    end

    // Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high

    always @(Cke) begin

        if (Cke === 1'b1) begin

            if (!((Cs_n) || (~Cs_n &  Ras_n & Cas_n &  We_n))) begin

                $display ("%m: at time %t MEMORY ERROR:  You must have a Deselect or NOP command applied", $time);

                $display ("%m:           when the Clock Enable is brought High.");

            end

        end

    end

    // Check the initialization sequence

    initial begin

        @ (posedge Cke) begin

            @ (posedge DLL_enable) begin

                aref_count = 0;

                @ (posedge DLL_reset) begin

                    @ (Prech_count) begin

                        if (aref_count >= 2) begin

                            if (DEBUG) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time);

                            power_up_done = 1;

                        end else begin

                            aref_count = 0;

                            @ (aref_count >= 2) begin

                                if (DEBUG) $display ("%m: at time %t MEMORY:  Power Up and Initialization Sequence is complete", $time);

                                power_up_done = 1;

                            end

                        end

                    end

                end

            end

        end

    end

    // Write Memory

    task write_mem;

        input [full_mem_bits - 1 : 0] addr;

        input       [DQ_BITS - 1 : 0] data;

        reg       [part_mem_bits : 0] i;

        begin

`ifdef FULL_MEM

            mem_array[addr] = data;

`else

            begin : loop

                for (i = 0; i < mem_used; i = i + 1) begin

                    if (addr_array[i] === addr) begin

                        disable loop;

                    end

                end

            end

            if (i === mem_used) begin

                if (i === (1<<part_mem_bits)) begin

                    $display ("At time %t ERROR: Memory overflow.\n  Write to Address %h with Data %h will be lost.\n  You must increase the part_mem_bits parameter or `define FULL_MEM.", $time, addr, data);

                end else begin

                    mem_used = mem_used + 1;

                    addr_array[i] = addr;

                end

            end

            mem_array[i] = data;

`endif

        end

    endtask

    // Read Memory

    task read_mem;

        input [full_mem_bits - 1 : 0] addr;

        output      [DQ_BITS - 1 : 0] data;

        reg       [part_mem_bits : 0] i;

        begin

`ifdef FULL_MEM

            data = mem_array[addr];

`else

            begin : loop

                for (i = 0; i < mem_used; i = i + 1) begin

                    if (addr_array[i] === addr) begin

                        disable loop;

                    end

                end

            end

            if (i <= mem_used) begin

                data = mem_array[i];

            end

`endif

        end

    endtask

    // Burst Decode

    task Burst_Decode;

    begin

        // Advance Burst Counter

        if (Burst_counter < burst_length) begin

            Burst_counter = Burst_counter + 1;

        end

        // Burst Type

        if (Mode_reg[3] === 1'b0) begin                         // Sequential Burst

            Cols_temp = Cols_addr + 1;

        end else if (Mode_reg[3] === 1'b1) begin                // Interleaved Burst

            Cols_temp[2] =  Burst_counter[2] ^ Cols_brst[2];

            Cols_temp[1] =  Burst_counter[1] ^ Cols_brst[1];

            Cols_temp[0] =  Burst_counter[0] ^ Cols_brst[0];

        end

        // Burst Length

        if (burst_length === 2) begin

            Cols_addr [0] = Cols_temp [0];

        end else if (burst_length === 4) begin

            Cols_addr [1 : 0] = Cols_temp [1 : 0];

        end else if (burst_length === 8) begin

            Cols_addr [2 : 0] = Cols_temp [2 : 0];

        end else begin

            Cols_addr = Cols_temp;

        end

        // Data Counter

        if (Burst_counter >= burst_length) begin

            Data_in_enable = 1'b0;

            Data_out_enable = 1'b0;

            read_precharge_truncation = 4'h0;

        end

    end

    endtask

    // Manual Precharge Pipeline

    task Manual_Precharge_Pipeline;

    begin

        // A10 Precharge Pipeline

        A10_precharge[0] = A10_precharge[1];

        A10_precharge[1] = A10_precharge[2];

        A10_precharge[2] = A10_precharge[3];

        A10_precharge[3] = A10_precharge[4];

        A10_precharge[4] = A10_precharge[5];

        A10_precharge[5] = A10_precharge[6];

        A10_precharge[6] = 1'b0;

        // Bank Precharge Pipeline

        Bank_precharge[0] = Bank_precharge[1];

        Bank_precharge[1] = Bank_precharge[2];

        Bank_precharge[2] = Bank_precharge[3];

        Bank_precharge[3] = Bank_precharge[4];

        Bank_precharge[4] = Bank_precharge[5];

        Bank_precharge[5] = Bank_precharge[6];

        Bank_precharge[6] = 2'b0;

        // Command Precharge Pipeline

        Cmnd_precharge[0] = Cmnd_precharge[1];

        Cmnd_precharge[1] = Cmnd_precharge[2];

        Cmnd_precharge[2] = Cmnd_precharge[3];

        Cmnd_precharge[3] = Cmnd_precharge[4];

        Cmnd_precharge[4] = Cmnd_precharge[5];

        Cmnd_precharge[5] = Cmnd_precharge[6];

        Cmnd_precharge[6] = 1'b0;

        // Terminate a Read if same bank or all banks

        if (Cmnd_precharge[0] === 1'b1) begin

            if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin

                if (Data_out_enable === 1'b1) begin

                    Data_out_enable = 1'b0;

                    read_precharge_truncation = 4'hF;

                end

            end

        end

    end

    endtask

    // Burst Terminate Pipeline

    task Burst_Terminate_Pipeline;

    begin

        // Command Precharge Pipeline

        Cmnd_bst[0] = Cmnd_bst[1];

        Cmnd_bst[1] = Cmnd_bst[2];

        Cmnd_bst[2] = Cmnd_bst[3];

        Cmnd_bst[3] = Cmnd_bst[4];

        Cmnd_bst[4] = Cmnd_bst[5];

        Cmnd_bst[5] = Cmnd_bst[6];

        Cmnd_bst[6] = 1'b0;

        // Terminate a Read regardless of banks

        if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin

            Data_out_enable = 1'b0;

        end

    end

    endtask

    // Dq and Dqs Drivers

    task Dq_Dqs_Drivers;

    begin

        // read command pipeline

        Read_cmnd [0] = Read_cmnd [1];

        Read_cmnd [1] = Read_cmnd [2];

        Read_cmnd [2] = Read_cmnd [3];

        Read_cmnd [3] = Read_cmnd [4];

        Read_cmnd [4] = Read_cmnd [5];

        Read_cmnd [5] = Read_cmnd [6];

        Read_cmnd [6] = 1'b0;

        // read bank pipeline

        Read_bank [0] = Read_bank [1];

        Read_bank [1] = Read_bank [2];

        Read_bank [2] = Read_bank [3];

        Read_bank [3] = Read_bank [4];

        Read_bank [4] = Read_bank [5];

        Read_bank [5] = Read_bank [6];

        Read_bank [6] = 2'b0;

        // read column pipeline

        Read_cols [0] = Read_cols [1];

        Read_cols [1] = Read_cols [2];

        Read_cols [2] = Read_cols [3];

        Read_cols [3] = Read_cols [4];

        Read_cols [4] = Read_cols [5];

        Read_cols [5] = Read_cols [6];

        Read_cols [6] = 0;

        // Initialize Read command

        if (Read_cmnd [0] === 1'b1) begin

            Data_out_enable = 1'b1;

            Bank_addr = Read_bank [0];

            Cols_addr = Read_cols [0];

            Cols_brst = Cols_addr [2 : 0];

            Burst_counter = 0;

            // Row Address Mux

            case (Bank_addr)

                2'd0    : Rows_addr = B0_row_addr;

                2'd1    : Rows_addr = B1_row_addr;

                2'd2    : Rows_addr = B2_row_addr;

                2'd3    : Rows_addr = B3_row_addr;

                default : $display ("At time %t ERROR: Invalid Bank Address", $time);

            endcase

        end

        // Toggle Dqs during Read command

        if (Data_out_enable === 1'b1) begin

            Dqs_int = 1'b0;

            if (Dqs_out === {DQS_BITS{1'b0}}) begin

                Dqs_out = {DQS_BITS{1'b1}};

            end else if (Dqs_out === {DQS_BITS{1'b1}}) begin

                Dqs_out = {DQS_BITS{1'b0}};

            end else begin

                Dqs_out = {DQS_BITS{1'b0}};

            end

        end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0) begin

            Dqs_out = {DQS_BITS{1'bz}};

        end

        // Initialize dqs for Read command

        if (Read_cmnd [2] === 1'b1) begin

            if (Data_out_enable === 1'b0) begin

                Dqs_int = 1'b1;

                Dqs_out = {DQS_BITS{1'b0}};

            end

        end

        // Read latch

        if (Data_out_enable === 1'b1) begin

            // output data

            read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out);

            if (DEBUG) begin

                $display ("At time %t READ : Bank = %h, Row = %h, Col = %h, Data = %h", $time, Bank_addr, Rows_addr, Cols_addr, Dq_out);

            end

        end else begin

            Dq_out = {DQ_BITS{1'bz}};

        end

    end

    endtask

    // Write FIFO and DM Mask Logic

    task Write_FIFO_DM_Mask_Logic;

    begin

        // Write command pipeline

        Write_cmnd [0] = Write_cmnd [1];

        Write_cmnd [1] = Write_cmnd [2];

        Write_cmnd [2] = Write_cmnd [3];

        Write_cmnd [3] = 1'b0;

        // Write command pipeline

        Write_bank [0] = Write_bank [1];

        Write_bank [1] = Write_bank [2];

        Write_bank [2] = Write_bank [3];

        Write_bank [3] = 2'b0;

        // Write column pipeline

        Write_cols [0] = Write_cols [1];

        Write_cols [1] = Write_cols [2];

        Write_cols [2] = Write_cols [3];

        Write_cols [3] = {COL_BITS{1'b0}};

        // Initialize Write command

        if (Write_cmnd [0] === 1'b1) begin

            Data_in_enable = 1'b1;

            Bank_addr = Write_bank [0];

            Cols_addr = Write_cols [0];

            Cols_brst = Cols_addr [2 : 0];

            Burst_counter = 0;

            // Row address mux

            case (Bank_addr)

                2'd0    : Rows_addr = B0_row_addr;

                2'd1    : Rows_addr = B1_row_addr;

                2'd2    : Rows_addr = B2_row_addr;

                2'd3    : Rows_addr = B3_row_addr;

                default : $display ("At time %t ERROR: Invalid Row Address", $time);

            endcase

        end

        // Write data

        if (Data_in_enable === 1'b1) begin

            // Data Buffer

            read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf);

            // write negedge Dqs on posedge Sys_clk

            if (Sys_clk) begin

                if (!dm_fall[0]) begin

                    Dq_buf [ 7 : 0] = dq_fall [ 7 : 0];

                end

                if (!dm_fall[1]) begin

                    Dq_buf [15 : 8] = dq_fall [15 : 8];

                end

                if (!dm_fall[2]) begin

                    Dq_buf [23 : 16] = dq_fall [23 : 16];

                end

                if (!dm_fall[3]) begin

                    Dq_buf [31 : 24] = dq_fall [31 : 24];