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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [example_design/] [sim/] [functional/] [ddr_model_parameters_c3.vh] - Blame information for rev 2

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/****************************************************************************************
2 
*
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*   Disclaimer   This software code and all associated documentation, comments or other
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*  of Warranty:  information (collectively "Software") is provided "AS IS" without
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*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
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*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
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*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
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*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
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*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
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*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
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*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
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*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
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*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
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*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
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*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
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*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
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*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
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*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
19 
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
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*                DAMAGES. Because some jurisdictions prohibit the exclusion or
21 
*                limitation of liability for consequential or incidental damages, the
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*                above limitation may not apply to you.
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*
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*                Copyright 2003 Micron Technology, Inc. All rights reserved.
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*
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****************************************************************************************/
27 
 
28 
    // Timing parameters based on Speed Grade
29 
 
30 
`ifdef x128Mb
31 
 
32 
`ifdef sg5B                               //              Timing Parameters for -5B (CL = 3)
33 
    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
34 
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
35 
    parameter tMRD             =    10.0; // tMRD   ns    Load Mode Register command cycle time
36 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
37 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
38 
    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
39 
    parameter tRFC             =    70.0; // tRFC   ns    Refresh to Refresh Command interval time
40 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
41 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
42 
    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
43 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
44 
`else `ifdef sg6T                         //              Timing Parameters for -6T (CL = 2.5)
45 
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
46 
    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
47 
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
48 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
49 
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
50 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
51 
    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
52 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
53 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
54 
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
55 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
56 
`else `ifdef sg75E                        //              Timing Parameters for -75E (CL = 2)
57 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
58 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
59 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
60 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
61 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
62 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
63 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
64 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
65 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
66 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
67 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
68 
`else `ifdef sg75Z                        //              Timing Parameters for -75Z (CL = 2)
69 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
70 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
71 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
72 
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
73 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
74 
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
75 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
76 
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
77 
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
78 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
79 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
80 
`else `define sg75                        //              Timing Parameters for -75 (CL = 2.5)
81 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
82 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
83 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
84 
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
85 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
86 
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
87 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
88 
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
89 
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
90 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
91 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
92 
`endif `endif `endif `endif
93 
 
94 
      // Size Parameters based on Part Width
95 
 
96 
`ifdef x4
97 
    parameter ADDR_BITS        =      12; // Set this parameter to control how many Address bits are used
98 
    parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used
99 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
100 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
101 
    parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
102 
`else `ifdef x8
103 
    parameter ADDR_BITS        =      12; // Set this parameter to control how many Address bits are used
104 
    parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used
105 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
106 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
107 
    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
108 
`else `define x16
109 
    parameter ADDR_BITS        =      12; // Set this parameter to control how many Address bits are used
110 
    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
111 
    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
112 
    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
113 
    parameter COL_BITS         =       9; // Set this parameter to control how many Column bits are used
114 
`endif `endif
115 
 
116 
 
117 
`else `ifdef x256Mb
118 
 
119 
`ifdef sg5B                               //              Timing Parameters for -5B (CL = 3)
120 
    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
121 
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
122 
    parameter tMRD             =    10.0; // tMRD   ns    Load Mode Register command cycle time
123 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
124 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
125 
    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
126 
    parameter tRFC             =    70.0; // tRFC   ns    Refresh to Refresh Command interval time
127 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
128 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
129 
    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
130 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
131 
`else `ifdef sg6T                         //              Timing Parameters for -6T (CL = 2.5)
132 
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
133 
    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
134 
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
135 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
136 
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
137 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
138 
    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
139 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
140 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
141 
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
142 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
143 
`else `ifdef sg6                          //              Timing Parameters for -6 (CL = 2.5)
144 
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
145 
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
146 
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
147 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
148 
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
149 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
150 
    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
151 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
152 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
153 
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
154 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
155 
`else `ifdef sg75E                        //              Timing Parameters for -75E (CL = 2)
156 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
157 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
158 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
159 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
160 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
161 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
162 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
163 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
164 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
165 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
166 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
167 
`else `ifdef sg75Z                        //              Timing Parameters for -75Z (CL = 2)
168 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
169 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
170 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
171 
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
172 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
173 
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
174 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
175 
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
176 
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
177 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
178 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
179 
`else `define sg75                        //              Timing Parameters for -75 (CL = 2.5)
180 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
181 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
182 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
183 
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
184 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
185 
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
186 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
187 
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
188 
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
189 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
190 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
191 
`endif `endif `endif `endif `endif
192 
    // Size Parameters based on Part Width
193 
 
194 
`ifdef x4
195 
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
196 
    parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used
197 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
198 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
199 
    parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
200 
`else `ifdef x8
201 
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
202 
    parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used
203 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
204 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
205 
    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
206 
`else `define x16
207 
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
208 
    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
209 
    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
210 
    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
211 
    parameter COL_BITS         =       9; // Set this parameter to control how many Column bits are used
212 
`endif `endif
213 
 
214 
 
215 
`else `ifdef x512Mb
216 
 
217 
`ifdef sg5B                               //              Timing Parameters for -5B (CL = 3)
218 
    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
219 
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
220 
    parameter tMRD             =    10.0; // tMRD   ns    Load Mode Register command cycle time
221 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
222 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
223 
    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
224 
    parameter tRFC             =    70.0; // tRFC   ns    Refresh to Refresh Command interval time
225 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
226 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
227 
    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
228 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
229 
`else `ifdef sg6T                         //              Timing Parameters for -6T (CL = 2.5)
230 
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
231 
    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
232 
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
233 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
234 
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
235 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
236 
    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
237 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
238 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
239 
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
240 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
241 
`else `ifdef sg6                          //              Timing Parameters for -6 (CL = 2.5)
242 
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
243 
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
244 
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
245 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
246 
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
247 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
248 
    parameter tRFC             =    72.0; // tRFC   ns    Refresh to Refresh Command interval time
249 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
250 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
251 
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
252 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
253 
`else `ifdef sg75E                        //              Timing Parameters for -75E (CL = 2)
254 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
255 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
256 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
257 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
258 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
259 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
260 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
261 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
262 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
263 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
264 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
265 
`else `ifdef sg75Z                        //              Timing Parameters for -75Z (CL = 2)
266 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
267 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
268 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
269 
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
270 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
271 
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
272 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
273 
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
274 
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
275 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
276 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
277 
`else `define sg75                        //              Timing Parameters for -75 (CL = 2.5)
278 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
279 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
280 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
281 
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
282 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
283 
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
284 
    parameter tRFC             =    75.0; // tRFC   ns    Refresh to Refresh Command interval time
285 
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
286 
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
287 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
288 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
289 
`endif `endif `endif `endif `endif
290 
 
291 
    // Size Parameters based on Part Width
292 
 
293 
`ifdef x4
294 
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
295 
    parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used
296 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
297 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
298 
    parameter COL_BITS         =      12; // Set this parameter to control how many Column bits are used
299 
`else `ifdef x8
300 
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
301 
    parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used
302 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
303 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
304 
    parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
305 
`else `define x16
306 
    parameter ADDR_BITS        =      13; // Set this parameter to control how many Address bits are used
307 
    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
308 
    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
309 
    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
310 
    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
311 
`endif `endif
312 
 
313 
`else `define x1Gb
314 
 
315 
`ifdef sg5B                               //              Timing Parameters for -5B (CL = 3)
316 
    parameter tCK              =     5.0; // tCK    ns    Nominal Clock Cycle Time
317 
    parameter tDQSQ            =     0.4; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
318 
    parameter tMRD             =    10.0; // tMRD   ns    Load Mode Register command cycle time
319 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
320 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
321 
    parameter tRC              =    55.0; // tRC    ns    Active to Active/Auto Refresh command time
322 
    parameter tRFC             =   120.0; // tRFC   ns    Refresh to Refresh Command interval time
323 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
324 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
325 
    parameter tRRD             =    10.0; // tRRD   ns    Active bank a to Active bank b command time
326 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
327 
`else `ifdef sg6T                         //              Timing Parameters for -6T (CL = 2.5)
328 
    parameter tCK              =     6.0; // tCK    ns    Nominal Clock Cycle Time
329 
    parameter tDQSQ            =    0.45; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
330 
    parameter tMRD             =    12.0; // tMRD   ns    Load Mode Register command cycle time
331 
    parameter tRAP             =    15.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
332 
    parameter tRAS             =    42.0; // tRAS   ns    Active to Precharge command time
333 
    parameter tRC              =    60.0; // tRC    ns    Active to Active/Auto Refresh command time
334 
    parameter tRFC             =   120.0; // tRFC   ns    Refresh to Refresh Command interval time
335 
    parameter tRCD             =    15.0; // tRCD   ns    Active to Read/Write command time
336 
    parameter tRP              =    15.0; // tRP    ns    Precharge command period
337 
    parameter tRRD             =    12.0; // tRRD   ns    Active bank a to Active bank b command time
338 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
339 
`else `define sg75                        //              Timing Parameters for -75 (CL = 2.5)
340 
    parameter tCK              =     7.5; // tCK    ns    Nominal Clock Cycle Time
341 
    parameter tDQSQ            =     0.5; // tDQSQ  ns    DQS-DQ skew, DQS to last DQ valid, per group, per access
342 
    parameter tMRD             =    15.0; // tMRD   ns    Load Mode Register command cycle time
343 
    parameter tRAP             =    20.0; // tRAP   ns    ACTIVE to READ with Auto precharge command
344 
    parameter tRAS             =    40.0; // tRAS   ns    Active to Precharge command time
345 
    parameter tRC              =    65.0; // tRC    ns    Active to Active/Auto Refresh command time
346 
    parameter tRFC             =   120.0; // tRFC   ns    Refresh to Refresh Command interval time
347 
    parameter tRCD             =    20.0; // tRCD   ns    Active to Read/Write command time
348 
    parameter tRP              =    20.0; // tRP    ns    Precharge command period
349 
    parameter tRRD             =    15.0; // tRRD   ns    Active bank a to Active bank b command time
350 
    parameter tWR              =    15.0; // tWR    ns    Write recovery time
351 
`endif `endif
352 
    // Size Parameters based on Part Width
353 
 
354 
`ifdef x4
355 
    parameter ADDR_BITS        =      14; // Set this parameter to control how many Address bits are used
356 
    parameter DQ_BITS          =       4; // Set this parameter to control how many Data bits are used
357 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
358 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
359 
    parameter COL_BITS         =      12; // Set this parameter to control how many Column bits are used
360 
`else `ifdef x8
361 
    parameter ADDR_BITS        =      14; // Set this parameter to control how many Address bits are used
362 
    parameter DQ_BITS          =       8; // Set this parameter to control how many Data bits are used
363 
    parameter DQS_BITS         =       1; // Set this parameter to control how many DQS bits are used
364 
    parameter DM_BITS          =       1; // Set this parameter to control how many DM bits are used
365 
    parameter COL_BITS         =      11; // Set this parameter to control how many Column bits are used
366 
`else `define x16
367 
    parameter ADDR_BITS        =      14; // Set this parameter to control how many Address bits are used
368 
    parameter DQ_BITS          =      16; // Set this parameter to control how many Data bits are used
369 
    parameter DQS_BITS         =       2; // Set this parameter to control how many DQS bits are used
370 
    parameter DM_BITS          =       2; // Set this parameter to control how many DM bits are used
371 
    parameter COL_BITS         =      10; // Set this parameter to control how many Column bits are used
372 
`endif `endif
373 
 
374 
`endif `endif `endif
375 
 
376 
    parameter BA_BITS          =       2;  // Set this parmaeter to control how many Bank Address bits are used
377 
    parameter full_mem_bits    =       BA_BITS+ADDR_BITS+COL_BITS; //10; // BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used
378 
    parameter part_mem_bits    =       10; // Set this parameter to control how many unique addresses are used
379 
 
380 
    parameter no_halt          =       1; // If set to 1, the model won't halt on command sequence/major errors
381 
    parameter DEBUG            =       1; // Turn on DEBUG message

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