Subversion Repositories usb_fpga_2_14

verilog  work  ../../rtl/example_top.v

verilog  work  ../../rtl/infrastructure.v

verilog  work  ../../rtl/memc_tb_top.v

verilog  work  ../../rtl/memc_wrapper.v

verilog  work  ../../rtl/mcb_controller/iodrp_controller.v

verilog  work  ../../rtl/mcb_controller/iodrp_mcb_controller.v

verilog  work  ../../rtl/mcb_controller/mcb_raw_wrapper.v

verilog  work  ../../rtl/mcb_controller/mcb_soft_calibration.v

verilog  work  ../../rtl/mcb_controller/mcb_soft_calibration_top.v

verilog  work  ../../rtl/mcb_controller/mcb_ui_top.v

verilog  work  ../../rtl/traffic_gen/afifo.v

verilog  work  ../../rtl/traffic_gen/cmd_gen.v

verilog  work  ../../rtl/traffic_gen/cmd_prbs_gen.v

verilog  work  ../../rtl/traffic_gen/data_prbs_gen.v

verilog  work  ../../rtl/traffic_gen/init_mem_pattern_ctr.v

verilog  work  ../../rtl/traffic_gen/mcb_flow_control.v

verilog  work  ../../rtl/traffic_gen/mcb_traffic_gen.v

verilog  work  ../../rtl/traffic_gen/rd_data_gen.v

verilog  work  ../../rtl/traffic_gen/read_data_path.v

verilog  work  ../../rtl/traffic_gen/read_posted_fifo.v

verilog  work  ../../rtl/traffic_gen/sp6_data_gen.v

verilog  work  ../../rtl/traffic_gen/tg_status.v

verilog  work  ../../rtl/traffic_gen/v6_data_gen.v

verilog  work  ../../rtl/traffic_gen/wr_data_gen.v

verilog  work  ../../rtl/traffic_gen/write_data_path.v

verilog  work  $XILINX/verilog/src/glbl.v

verilog  work  ./sim_tb_top.v

verilog  work  ./ddr_model_c3.v -d x512Mb -d FULL_MEM -d sg5B -d x16 -i ./