URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [datasheet.txt] - Blame information for rev 2

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CORE Generator Options:
   Target Device              : xc6slx16-ftg256
   Speed Grade                : -2
   HDL                        : verilog
   Synthesis Tool             : Foundation_ISE
 
MIG Output Options:
   Component Name             : mem0
   No of Controllers          : 1
   Hardware Test Bench           : disabled
 
 
/*******************************************************/
/*                  Controller 3                       */
/*******************************************************/
Controller Options :
   Memory                  : DDR_SDRAM
   Interface               : NATIVE
   Design Clock Frequency  : 5000 ps (200.00 MHz)
   Memory Type             : Components
   Memory Part             : MT46V32M16XX-5B-IT
   Equivalent Part(s)      : MT46V32M16BN-5B-IT
   Row Address             : 13
   Bank Address            : 2
   Data Mask               : enabled
 
Memory Options :
   Mode Register :
   Burst Length                       : 4(010)
   CAS Latency                        : 3
   DLL Enable                         : Enable-Normal
   Output Drive Strength              : Normal
 
User Interface Parameters :
   Configuration Type     : Two 32-bit bi-directional and four 32-bit unidirectional ports
   Ports Selected         : Port0, Port1, Port2, Port3, Port4, Port5
   Memory Address Mapping : ROW_BANK_COLUMN
 
   Arbitration Algorithm  : Round Robin
 
   Arbitration            :
      Time Slot0 : 012345
      Time Slot1 : 123450
      Time Slot2 : 234501
      Time Slot3 : 345012
      Time Slot4 : 450123
      Time Slot5 : 501234
      Time Slot6 : 012345
      Time Slot7 : 123450
      Time Slot8 : 234501
      Time Slot9 : 345012
      Time Slot10: 450123
      Time Slot11: 501234
 
FPGA Options :
   Class for Address and Control       : II
   Class for Data                      : II
   Memory Interface Pin Termination    : EXTERN_TERM
   DQ/DQS                              : 25 Ohms
   Bypass Calibration                  : enabled
   Debug Signals for Memory Controller : Disable
   Input Clock Type                    : Single-Ended
 

Line No.	Rev	Author	Line
1	2	ZTEX
2
3			`CORE Generator Options:`
4			`Target Device : xc6slx16-ftg256`
5			`Speed Grade : -2`
6			`HDL : verilog`
7			`Synthesis Tool : Foundation_ISE`
8
9			`MIG Output Options:`
10			`Component Name : mem0`
11			`No of Controllers : 1`
12			`Hardware Test Bench : disabled`
13
14
15			`/*******************************************************/`
16			`/* Controller 3 */`
17			`/*******************************************************/`
18			`Controller Options :`
19			`Memory : DDR_SDRAM`
20			`Interface : NATIVE`
21			`Design Clock Frequency : 5000 ps (200.00 MHz)`
22			`Memory Type : Components`
23			`Memory Part : MT46V32M16XX-5B-IT`
24			`Equivalent Part(s) : MT46V32M16BN-5B-IT`
25			`Row Address : 13`
26			`Bank Address : 2`
27			`Data Mask : enabled`
28
29			`Memory Options :`
30			`Mode Register :`
31			`Burst Length : 4(010)`
32			`CAS Latency : 3`
33			`DLL Enable : Enable-Normal`
34			`Output Drive Strength : Normal`
35
36			`User Interface Parameters :`
37			`Configuration Type : Two 32-bit bi-directional and four 32-bit unidirectional ports`
38			`Ports Selected : Port0, Port1, Port2, Port3, Port4, Port5`
39			`Memory Address Mapping : ROW_BANK_COLUMN`
40
41			`Arbitration Algorithm : Round Robin`
42
43			`Arbitration :`
44			`Time Slot0 : 012345`
45			`Time Slot1 : 123450`
46			`Time Slot2 : 234501`
47			`Time Slot3 : 345012`
48			`Time Slot4 : 450123`
49			`Time Slot5 : 501234`
50			`Time Slot6 : 012345`
51			`Time Slot7 : 123450`
52			`Time Slot8 : 234501`
53			`Time Slot9 : 345012`
54			`Time Slot10: 450123`
55			`Time Slot11: 501234`
56
57			`FPGA Options :`
58			`Class for Address and Control : II`
59			`Class for Data : II`
60			`Memory Interface Pin Termination : EXTERN_TERM`
61			`DQ/DQS : 25 Ohms`
62			`Bypass Calibration : enabled`
63			`Debug Signals for Memory Controller : Disable`
64			`Input Clock Type : Single-Ended`
65

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Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [datasheet.txt] - Blame information for rev 2