URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [rtl/] [infrastructure.v.diff] - Blame information for rev 2

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Line No.	Rev	Author	Line
1	2	ZTEX	`--- infrastructure.orig.v 2014-05-22 14:50:42.000000000 +0200`
2			`+++ infrastructure.v 2014-06-02 14:43:45.000000000 +0200`
3			`@@ -123,44 +123,11 @@`
4
5			`wire sys_rst;`
6			`wire bufpll_mcb_locked;`
7			`- (* KEEP = "TRUE" *) wire sys_clk_ibufg;`
8
9			`assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i;`
10			`assign clk0 = clk0_bufg;`
11			`assign pll_lock = bufpll_mcb_locked;`
12
13			`- generate`
14			`- if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk`
15			`-`
16			`- //***********************************************************************`
17			`- // Differential input clock input buffers`
18			`- //***********************************************************************`
19			`-`
20			`- IBUFGDS #`
21			`- (`
22			`- .DIFF_TERM ("TRUE")`
23			`- )`
24			`- u_ibufg_sys_clk`
25			`- (`
26			`- .I (sys_clk_p),`
27			`- .IB (sys_clk_n),`
28			`- .O (sys_clk_ibufg)`
29			`- );`
30			`-`
31			`- end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk`
32			`-`
33			`- //***********************************************************************`
34			`- // SINGLE_ENDED input clock input buffers`
35			`- //***********************************************************************`
36			`-`
37			`- IBUFG u_ibufg_sys_clk`
38			`- (`
39			`- .I (sys_clk),`
40			`- .O (sys_clk_ibufg)`
41			`- );`
42			`- end`
43			`- endgenerate`
44			`-`
45			`//***************************************************************************`
46			`// Global clock generation and distribution`
47			`//***************************************************************************`
48			`@@ -199,7 +166,7 @@`
49			`(`
50			`.CLKFBIN (clkfbout_clkfbin),`
51			`.CLKINSEL (1'b1),`
52			`- .CLKIN1 (sys_clk_ibufg),`
53			`+ .CLKIN1 (sys_clk),`
54			`.CLKIN2 (1'b0),`
55			`.DADDR (5'b0),`
56			`.DCLK (1'b0),`

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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [rtl/] [infrastructure.v.diff] - Blame information for rev 2