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//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version: %version

//  \   \         Application: MIG

//  /   /         Filename: mcb_raw_wrapper.v

// /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:24 $

// \   \  /  \    Date Created: Thu June 24 2008

//  \___\/\___\

//

//Device: Spartan6

//Design Name: DDR/DDR2/DDR3/LPDDR 

//Purpose:

//Reference:

//   This module is the intialization control logic of the memory interface.

//   All commands are issued from here acoording to the burst, CAS Latency and

//   the user commands.

//   

// Revised History:  

//    Rev 1.1 - added port_enable assignment for all configurations  and rearrange 

//              assignment siganls according to port number

//            - added timescale directive  -SN 7-28-08

//            - added C_ARB_NUM_TIME_SLOTS and removed the slot 12 through 

//              15 -SN 7-28-08

//            - changed C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TWR /C_MEMCLK_PERIOD) -SN 7-28-08

//            - removed ghighb, gpwrdnb, gsr, gwe in port declaration. 

//              For now tb need to force the signals inside the MCB and Wrapper

//              until a glbl.v is ready.  Not sure how to do this in NCVerilog 

//              flow. -SN 7-28-08

//

//    Rev 1.2 -- removed p*_cmd_error signals -SN 8-05-08

//    Rev 1.3 -- Added gate logic for data port rd_en and wr_en in Config 3,4,5   - SN 8-8-08

//    Rev 1.4 -- update changes that required by MCB core.  - SN 9-11-09

//    Rev 1.5 -- update. CMD delays has been removed in Sept 26 database. -- SN 9-28-08

//               delay_cas_90,delay_ras_90,delay_cke_90,delay_odt_90,delay_rst_90 

//               delay_we_90 ,delay_address,delay_ba_90 =

//               --removed :assign #50 delay_dqnum = dqnum;

//               --removed :assign #50 delay_dqpum = dqpum;

//               --removed :assign #50 delay_dqnlm = dqnlm;

//               --removed :assign #50 delay_dqplm = dqplm;

//               --removed : delay_dqsIO_w_en_90_n

//               --removed : delay_dqsIO_w_en_90_p              

//               --removed : delay_dqsIO_w_en_0     

//               -- corrected spelling error: C_MEM_RTRAS

//    Rev 1.6 -- update IODRP2 and OSERDES connection and was updated by Chip.  1-12-09              

//                 -- rename the memc_wrapper.v to mcb_raw_wrapper.v

//    Rev 1.7   -- .READEN    is removed in IODRP2_MCB 1-28-09

//              -- connection has been updated                            

//    Rev 1.8   -- update memory parameter equations.    1-30_2009

//              -- added portion of Soft IP               

//              -- CAL_CLK_DIV is not used but MCB still has it

//    Rev  1.9  -- added Error checking for Invalid command to unidirectional port   

//    Rev  1.10 -- changed the backend connection so that Simulation will work while

//                 sw tools try to fix the model issues.                  2-3-2009      

//                 sysclk_2x_90 name is changed to sysclk_2x_180 . It created confusions.

//                 It is acutally 180 degree difference.

//    Rev  1.11 -- Added soft_calibration_top. 

//    Rev  1.12 -- fixed ui_clk connection to MCB when soft_calib_ip is on. 5-14-2009   

//    Rev  1.13 -- Added PULLUP/PULLDN for DQS/DQSN, UDQS/UDQSN lines.

//    Rev  1.14 -- Added minium condition for tRTP valud/                        

//    REv  1.15 -- Bring the SKIP_IN_TERM_CAL and SKIP_DYNAMIC_CAL from calib_ip to top.  6-16-2009

//    Rev  1.16 -- Fixed the WTR for DDR. 6-23-2009

//    Rev  1.17 -- Fixed width mismatch for px_cmd_ra,px_cmd_ca,px_cmd_ba 7-02-2009

//    Rev  1.18 -- Added lumpdelay parameters for 1.0 silicon support to bypass Calibration 7-10-2010

//    Rev  1.19 -- Added soft fix to support refresh command. 7-15-2009.

//    Rev  1.20 -- Turned on the CALIB_SOFT_IP and C_MC_CALIBRATION_MODE is used to enable/disable

//                 Dynamic DQS calibration in Soft Calibration module.

//    Rev  1.21 -- Added extra generate mcbx_dram_odt pin condition. It will not be generated if

//                 RTT value is set to "disabled"

//              -- Corrected the UIUDQSDEC connection between soft_calib and MCB.

//              -- PLL_LOCK pin to MCB tie high. Soft Calib module asserts MCB_RST when pll_lock is deasserted. 1-19-2010                

//    Rev  1.22 -- Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .

//    Rev  1.23 -- Added DDR2 Initialization fix when C_CALIB_SOFT_IP set to "FALSE" 

//    Rev  1.24 -- Fixed reset problem when MCB exits from SUSPEND SELFREFRESH mode.

//    Rev  1.25 -- Added a new parameter C_USR_INTERFACE_MODE for AXI interface application. Axi DDRx controller

//                 never assert wr_en  or rd_en when wr_full or rd_empty is asserted. 

//    Rev  1.26 -- Synchronize sys_rst before connecting to mcb_soft_calibration module to fix

//                 CDC static timing issue.

//*************************************************************************************************************************

`define DEBUG

`timescale 1ps / 1ps

module mcb_raw_wrapper #

 (

parameter  C_MEMCLK_PERIOD          = 2500,       // /Mem clk period (in ps)

parameter  C_PORT_ENABLE            = 6'b111111,    //  config1 : 6b'111111,  config2: 4'b1111. config3 : 3'b111, config4: 2'b11, config5 1'b1

                                                  //  C_PORT_ENABLE[5] => User port 5,  ...,C_PORT_ENABLE[0] => User port 0

// Should the C_MEM_ADDR_ORDER made available to user ??

parameter  C_MEM_ADDR_ORDER             = "BANK_ROW_COLUMN" , //RowBankCol//ADDR_ORDER_MC : 0: Bank Row Col 1: Row Bank Col. User Address mapping oreder

parameter C_USR_INTERFACE_MODE       = "NATIVE", // Option is "NATIVE", "AXI"

                                               // This should default to "NATIVE" and only AXI interface

                                               // can set to "AXI"

////////////////////////////////////////////////////////////////////////////////////////////////

//  The parameter belows are not exposed to non-embedded users.

// for now this arb_time_slot_x attributes will not exposed to user and will be generated from MIG tool 

// to translate the logical port to physical port. For advance user, translate the logical port

// to physical port before passing them to this wrapper.

// MIG need to save the user setting in project file.

parameter  C_ARB_NUM_TIME_SLOTS     = 12,                      // For advance mode, allow user to either choose 10 or 12

parameter  C_ARB_TIME_SLOT_0        = 18'o012345,               // Config 1: "B32_B32_X32_X32_X32_X32"

parameter  C_ARB_TIME_SLOT_1        = 18'o123450,               //            User port 0 --->MCB port 0,User port 1 --->MCB port 1 

parameter  C_ARB_TIME_SLOT_2        = 18'o234501,               //            User port 2 --->MCB port 2,User port 3 --->MCB port 3

parameter  C_ARB_TIME_SLOT_3        = 18'o345012,               //            User port 4 --->MCB port 4,User port 5 --->MCB port 5

parameter  C_ARB_TIME_SLOT_4        = 18'o450123,               // Config 2: "B32_B32_B32_B32"  

parameter  C_ARB_TIME_SLOT_5        = 18'o501234,             //            User port 0     --->  MCB port 0

parameter  C_ARB_TIME_SLOT_6        = 18'o012345,             //            User port 1     --->  MCB port 1

parameter  C_ARB_TIME_SLOT_7        = 18'o123450,             //            User port 2     --->  MCB port 2

parameter  C_ARB_TIME_SLOT_8        = 18'o234501,             //            User port 3     --->  MCB port 4

parameter  C_ARB_TIME_SLOT_9        = 18'o345012,             // Config 3: "B64_B32_B3"   

parameter  C_ARB_TIME_SLOT_10       = 18'o450123,             //            User port 0     --->  MCB port 0

parameter  C_ARB_TIME_SLOT_11       = 18'o501234,             //            User port 1     --->  MCB port 2

                                                               //            User port 2     --->  MCB port 4

                                                               // Config 4: "B64_B64"              

                                                               //            User port 0     --->  MCB port 0

                                                               //            User port 1     --->  MCB port 2

                                                               // Config 5  "B128"              

                                                               //            User port 0     --->  MCB port 0

parameter  C_PORT_CONFIG               =  "B128",

// Memory Timings

parameter  C_MEM_TRAS              =   45000,            //CEIL (tRAS/tCK)

parameter  C_MEM_TRCD               =   12500,            //CEIL (tRCD/tCK)

parameter  C_MEM_TREFI              =   7800,             //CEIL (tREFI/tCK) number of clocks

parameter  C_MEM_TRFC               =   127500,           //CEIL (tRFC/tCK)

parameter  C_MEM_TRP                =   12500,            //CEIL (tRP/tCK)

parameter  C_MEM_TWR                =   15000,            //CEIL (tWR/tCK)

parameter  C_MEM_TRTP               =   7500,             //CEIL (tRTP/tCK)

parameter  C_MEM_TWTR               =   7500,

parameter  C_NUM_DQ_PINS               =  8,

parameter  C_MEM_TYPE                  =  "DDR3",

parameter  C_MEM_DENSITY               =  "512M",

parameter  C_MEM_BURST_LEN             =  8,       // MIG Rules for setting this parameter

                                                   // For DDR3  this one always set to 8; 

                                                   // For DDR2  Config 1 : MemWidth x8,x16:=> 4; MemWidth  x4     => 8

                                                   //           Config 2 : MemWidth x8,x16:=> 4; MemWidth  x4     => 8

                                                   //           Config 3 : Data Port Width: 32   MemWidth x8,x16:=> 4; MemWidth  x4     => 8

                                                   //                      Data Port Width: 64   MemWidth x16   :=> 4; MemWidth  x8,x4     => 8

                                                   //           Config 4 : Data Port Width: 64   MemWidth x16   :=> 4; MemWidth  x4,x8, => 8    

                                                   //           Config 5 : Data Port Width: 128  MemWidth x4, x8,x16: => 8

parameter  C_MEM_CAS_LATENCY           =  4,

parameter  C_MEM_ADDR_WIDTH            =  13,    // extracted from selected Memory part

parameter  C_MEM_BANKADDR_WIDTH        =  3,     // extracted from selected Memory part

parameter  C_MEM_NUM_COL_BITS          =  11,    // extracted from selected Memory part

parameter  C_MEM_DDR3_CAS_LATENCY      = 7,

parameter  C_MEM_MOBILE_PA_SR          = "FULL",  //"FULL", "HALF" Mobile DDR Partial Array Self-Refresh 

parameter  C_MEM_DDR1_2_ODS            = "FULL",  //"FULL"  :REDUCED" 

parameter  C_MEM_DDR3_ODS              = "DIV6",

parameter  C_MEM_DDR2_RTT              = "50OHMS",

parameter  C_MEM_DDR3_RTT              =  "DIV2",

parameter  C_MEM_MDDR_ODS              =  "FULL",

parameter  C_MEM_DDR2_DIFF_DQS_EN      =  "YES",

parameter  C_MEM_DDR2_3_PA_SR          =  "OFF",

parameter  C_MEM_DDR3_CAS_WR_LATENCY   =   5,        // this parameter is hardcoded  by MIG tool which depends on the memory clock frequency

                                                     //C_MEMCLK_PERIOD ave = 2.5ns to < 3.3 ns, CWL = 5 

                                                     //C_MEMCLK_PERIOD ave = 1.875ns to < 2.5 ns, CWL = 6 

                                                     //C_MEMCLK_PERIOD ave = 1.5ns to <1.875ns, CSL = 7 

                                                     //C_MEMCLK_PERIOD avg = 1.25ns to < 1.5ns , CWL = 8

parameter  C_MEM_DDR3_AUTO_SR         =  "ENABLED",

parameter  C_MEM_DDR2_3_HIGH_TEMP_SR  =  "NORMAL",

parameter  C_MEM_DDR3_DYN_WRT_ODT     =  "OFF",

parameter  C_MEM_TZQINIT_MAXCNT       = 10'd512,  // DDR3 Minimum delay between resets

//Calibration 

parameter  C_MC_CALIB_BYPASS        = "NO",

parameter  C_MC_CALIBRATION_RA      = 15'h0000,

parameter  C_MC_CALIBRATION_BA      = 3'h0,

parameter C_CALIB_SOFT_IP           = "TRUE",

parameter C_SKIP_IN_TERM_CAL = 1'b0,     //provides option to skip the input termination calibration

parameter C_SKIP_DYNAMIC_CAL = 1'b0,     //provides option to skip the dynamic delay calibration

parameter C_SKIP_DYN_IN_TERM = 1'b1,     // provides option to skip the input termination calibration

parameter C_SIMULATION       = "FALSE",  // Tells us whether the design is being simulated or implemented

////////////////LUMP DELAY Params ////////////////////////////

/// ADDED for 1.0 silicon support to bypass Calibration //////

/// 07-10-09 chipl

//////////////////////////////////////////////////////////////

parameter LDQSP_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter UDQSP_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter LDQSN_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter UDQSN_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ0_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ1_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ2_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ3_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ4_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ5_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ6_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ7_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ8_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ9_TAP_DELAY_VAL  = 0,  // 0 to 255 inclusive

parameter DQ10_TAP_DELAY_VAL = 0,  // 0 to 255 inclusive

parameter DQ11_TAP_DELAY_VAL = 0,  // 0 to 255 inclusive

parameter DQ12_TAP_DELAY_VAL = 0,  // 0 to 255 inclusive

parameter DQ13_TAP_DELAY_VAL = 0,  // 0 to 255 inclusive

parameter DQ14_TAP_DELAY_VAL = 0,  // 0 to 255 inclusive

parameter DQ15_TAP_DELAY_VAL = 0,  // 0 to 255 inclusive

//*************

// MIG tool need to do DRC on this parameter to make sure this is valid Column address to avoid boundary crossing for the current Burst Size setting.

parameter  C_MC_CALIBRATION_CA      = 12'h000,

parameter  C_MC_CALIBRATION_CLK_DIV     = 1,

parameter  C_MC_CALIBRATION_MODE    = "CALIBRATION"     ,   // "CALIBRATION", "NOCALIBRATION"

parameter  C_MC_CALIBRATION_DELAY   = "HALF",   // "QUARTER", "HALF","THREEQUARTER", "FULL"

parameter C_P0_MASK_SIZE           = 4,

parameter C_P0_DATA_PORT_SIZE      = 32,

parameter C_P1_MASK_SIZE           = 4,

parameter C_P1_DATA_PORT_SIZE         = 32

    )

  (

      // high-speed PLL clock interface

      input sysclk_2x,

      input sysclk_2x_180,

      input pll_ce_0,

      input pll_ce_90,

      input pll_lock,

      input sys_rst,

      // Not needed as ioi netlist are not used

//***********************************************************************************

//  Below User Port siganls needs to be customized when generating codes from MIG tool

//  The corresponding internal codes that directly use the commented out port signals 

//  needs to be removed when gernerating wrapper outputs.

//!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

      //User Port0 Interface Signals

      // p0_xxxx signals  shows up in Config 1 , Config 2 , Config 3, Config4 and Config 5

      // cmd port 0 signals

      input             p0_arb_en,

      input             p0_cmd_clk,

      input             p0_cmd_en,

      input [2:0]       p0_cmd_instr,

      input [5:0]       p0_cmd_bl,

      input [29:0]      p0_cmd_byte_addr,

      output            p0_cmd_empty,

      output            p0_cmd_full,

      // Data Wr Port signals

      // p0_wr_xx signals  shows up in Config 1 

      // p0_wr_xx signals  shows up in Config 2

      // p0_wr_xx signals  shows up in Config 3

      // p0_wr_xx signals  shows up in Config 4

      // p0_wr_xx signals  shows up in Config 5

      input             p0_wr_clk,

      input             p0_wr_en,

      input [C_P0_MASK_SIZE - 1:0]      p0_wr_mask,

      input [C_P0_DATA_PORT_SIZE - 1:0] p0_wr_data,

      output            p0_wr_full,        //

      output            p0_wr_empty,//

      output [6:0]      p0_wr_count,//

      output            p0_wr_underrun,//

      output            p0_wr_error,//

      //Data Rd Port signals

      // p0_rd_xx signals  shows up in Config 1 

      // p0_rd_xx signals  shows up in Config 2

      // p0_rd_xx signals  shows up in Config 3

      // p0_rd_xx signals  shows up in Config 4

      // p0_rd_xx signals  shows up in Config 5

      input             p0_rd_clk,

      input             p0_rd_en,

      output [C_P0_DATA_PORT_SIZE - 1:0]        p0_rd_data,

      output            p0_rd_full,//

      output            p0_rd_empty,//

      output [6:0]      p0_rd_count,

      output            p0_rd_overflow,//

      output            p0_rd_error,//

      //****************************

      //User Port1 Interface Signals

      // This group of signals only appear on Config 1,2,3,4 when generated from MIG tool

      input             p1_arb_en,

      input             p1_cmd_clk,

      input             p1_cmd_en,

      input [2:0]       p1_cmd_instr,

      input [5:0]       p1_cmd_bl,

      input [29:0]      p1_cmd_byte_addr,

      output            p1_cmd_empty,

      output            p1_cmd_full,

      // Data Wr Port signals

      input             p1_wr_clk,

      input             p1_wr_en,

      input [C_P1_MASK_SIZE - 1:0]      p1_wr_mask,

      input [C_P1_DATA_PORT_SIZE - 1:0] p1_wr_data,

      output            p1_wr_full,

      output            p1_wr_empty,

      output [6:0]      p1_wr_count,

      output            p1_wr_underrun,

      output            p1_wr_error,

      //Data Rd Port signals

      input             p1_rd_clk,

      input             p1_rd_en,

      output [C_P1_DATA_PORT_SIZE - 1:0]        p1_rd_data,

      output            p1_rd_full,

      output            p1_rd_empty,

      output [6:0]      p1_rd_count,

      output            p1_rd_overflow,

      output            p1_rd_error,

      //****************************

      //User Port2 Interface Signals

      // This group of signals only appear on Config 1,2,3 when generated from MIG tool

      // p2_xxxx signals  shows up in Config 1 , Config 2 and Config 3

      // p_cmd port 2 signals

      input             p2_arb_en,

      input             p2_cmd_clk,

      input             p2_cmd_en,

      input [2:0]       p2_cmd_instr,

      input [5:0]       p2_cmd_bl,

      input [29:0]      p2_cmd_byte_addr,

      output            p2_cmd_empty,

      output            p2_cmd_full,

      // Data Wr Port signals

      // p2_wr_xx signals  shows up in Config 1 and Wr Dir  

      // p2_wr_xx signals  shows up in Config 2

      // p2_wr_xx signals  shows up in Config 3

      input             p2_wr_clk,

      input             p2_wr_en,

      input [3:0]       p2_wr_mask,

      input [31:0]      p2_wr_data,

      output            p2_wr_full,

      output            p2_wr_empty,

      output [6:0]      p2_wr_count,

      output            p2_wr_underrun,

      output            p2_wr_error,

      //Data Rd Port signals

      // p2_rd_xx signals  shows up in Config 1 and Rd Dir

      // p2_rd_xx signals  shows up in Config 2

      // p2_rd_xx signals  shows up in Config 3

      input             p2_rd_clk,

      input             p2_rd_en,

      output [31:0]     p2_rd_data,

      output            p2_rd_full,

      output            p2_rd_empty,

      output [6:0]      p2_rd_count,

      output            p2_rd_overflow,

      output            p2_rd_error,

      //****************************

      //User Port3 Interface Signals

      // This group of signals only appear on Config 1,2 when generated from MIG tool

      input             p3_arb_en,

      input             p3_cmd_clk,

      input             p3_cmd_en,

      input [2:0]       p3_cmd_instr,

      input [5:0]       p3_cmd_bl,

      input [29:0]      p3_cmd_byte_addr,

      output            p3_cmd_empty,

      output            p3_cmd_full,

      // Data Wr Port signals

      // p3_wr_xx signals  shows up in Config 1 and Wr Dir

      // p3_wr_xx signals  shows up in Config 2

      input             p3_wr_clk,

      input             p3_wr_en,

      input [3:0]       p3_wr_mask,

      input [31:0]      p3_wr_data,

      output            p3_wr_full,

      output            p3_wr_empty,

      output [6:0]      p3_wr_count,

      output            p3_wr_underrun,

      output            p3_wr_error,

      //Data Rd Port signals

      // p3_rd_xx signals  shows up in Config 1 and Rd Dir when generated from MIG ttols

      // p3_rd_xx signals  shows up in Config 2 

      input             p3_rd_clk,

      input             p3_rd_en,

      output [31:0]     p3_rd_data,

      output            p3_rd_full,

      output            p3_rd_empty,

      output [6:0]      p3_rd_count,

      output            p3_rd_overflow,

      output            p3_rd_error,

      //****************************

      //User Port4 Interface Signals

      // This group of signals only appear on Config 1,2,3,4 when generated from MIG tool

      // p4_xxxx signals only shows up in Config 1

      input             p4_arb_en,

      input             p4_cmd_clk,

      input             p4_cmd_en,

      input [2:0]       p4_cmd_instr,

      input [5:0]       p4_cmd_bl,

      input [29:0]      p4_cmd_byte_addr,

      output            p4_cmd_empty,

      output            p4_cmd_full,

      // Data Wr Port signals

      // p4_wr_xx signals only shows up in Config 1 and Wr Dir

      input             p4_wr_clk,

      input             p4_wr_en,

      input [3:0]       p4_wr_mask,

      input [31:0]      p4_wr_data,

      output            p4_wr_full,

      output            p4_wr_empty,

      output [6:0]      p4_wr_count,

      output            p4_wr_underrun,

      output            p4_wr_error,

      //Data Rd Port signals

      // p4_rd_xx signals only shows up in Config 1 and Rd Dir

      input             p4_rd_clk,

      input             p4_rd_en,

      output [31:0]     p4_rd_data,

      output            p4_rd_full,

      output            p4_rd_empty,

      output [6:0]      p4_rd_count,

      output            p4_rd_overflow,

      output            p4_rd_error,

      //****************************

      //User Port5 Interface Signals

      // p5_xxxx signals only shows up in Config 1; p5_wr_xx or p5_rd_xx depends on the user port settings

      input             p5_arb_en,

      input             p5_cmd_clk,

      input             p5_cmd_en,

      input [2:0]       p5_cmd_instr,

      input [5:0]       p5_cmd_bl,

      input [29:0]      p5_cmd_byte_addr,

      output            p5_cmd_empty,

      output            p5_cmd_full,

      // Data Wr Port signals

      input             p5_wr_clk,

      input             p5_wr_en,

      input [3:0]       p5_wr_mask,

      input [31:0]      p5_wr_data,

      output            p5_wr_full,

      output            p5_wr_empty,

      output [6:0]      p5_wr_count,

      output            p5_wr_underrun,

      output            p5_wr_error,

      //Data Rd Port signals

      input             p5_rd_clk,

      input             p5_rd_en,

      output [31:0]     p5_rd_data,

      output            p5_rd_full,

      output            p5_rd_empty,

      output [6:0]      p5_rd_count,

      output            p5_rd_overflow,

      output            p5_rd_error,

//*****************************************************

      // memory interface signals    

      output [C_MEM_ADDR_WIDTH-1:0]     mcbx_dram_addr,

      output [C_MEM_BANKADDR_WIDTH-1:0] mcbx_dram_ba,

      output                            mcbx_dram_ras_n,

      output                            mcbx_dram_cas_n,

      output                            mcbx_dram_we_n,

      output                            mcbx_dram_cke,

      output                            mcbx_dram_clk,

      output                            mcbx_dram_clk_n,

      inout [C_NUM_DQ_PINS-1:0]         mcbx_dram_dq,

      inout                             mcbx_dram_dqs,

      inout                             mcbx_dram_dqs_n,

      inout                             mcbx_dram_udqs,

      inout                             mcbx_dram_udqs_n,

      output                            mcbx_dram_udm,

      output                            mcbx_dram_ldm,

      output                            mcbx_dram_odt,

      output                            mcbx_dram_ddr3_rst,

      // Calibration signals

      input calib_recal,              // Input signal to trigger calibration

     // output calib_done,        // 0=calibration not done or is in progress.  

                                // 1=calibration is complete.  Also a MEM_READY indicator

   //Input - RZQ pin from board - expected to have a 2*R resistor to ground

   //Input - Z-stated IO pin - either unbonded IO, or IO garanteed not to be driven externally

      inout                             rzq,           // RZQ pin from board - expected to have a 2*R resistor to ground

      inout                             zio,           // Z-stated IO pin - either unbonded IO, or IO garanteed not to be driven externally

      // new added signals *********************************

      // these signals are for dynamic Calibration IP

      input                             ui_read,

      input                             ui_add,

      input                             ui_cs,

      input                             ui_clk,

      input                             ui_sdi,

      input     [4:0]                   ui_addr,

      input                             ui_broadcast,

      input                             ui_drp_update,

      input                             ui_done_cal,

      input                             ui_cmd,

      input                             ui_cmd_in,

      input                             ui_cmd_en,

      input     [3:0]                   ui_dqcount,

      input                             ui_dq_lower_dec,

      input                             ui_dq_lower_inc,

      input                             ui_dq_upper_dec,

      input                             ui_dq_upper_inc,

      input                             ui_udqs_inc,

      input                             ui_udqs_dec,

      input                             ui_ldqs_inc,

      input                             ui_ldqs_dec,

      output     [7:0]                  uo_data,

      output                            uo_data_valid,

      output                            uo_done_cal,

      output                            uo_cmd_ready_in,

      output                            uo_refrsh_flag,

      output                            uo_cal_start,

      output                            uo_sdo,

      output   [31:0]                   status,

      input                             selfrefresh_enter,

      output                            selfrefresh_mode

         );

  function integer cdiv (input integer num,

                         input integer div); // ceiling divide

    begin

      cdiv = (num/div) + (((num%div)>0) ? 1 : 0);

    end

  endfunction // cdiv

// parameters added by AM for OSERDES2 12/09/2008, these parameters may not have to change 

localparam C_OSERDES2_DATA_RATE_OQ = "SDR";           //SDR, DDR

localparam C_OSERDES2_DATA_RATE_OT = "SDR";           //SDR, DDR

localparam C_OSERDES2_SERDES_MODE_MASTER  = "MASTER";        //MASTER, SLAVE

localparam C_OSERDES2_SERDES_MODE_SLAVE   = "SLAVE";        //MASTER, SLAVE

localparam C_OSERDES2_OUTPUT_MODE_SE      = "SINGLE_ENDED";   //SINGLE_ENDED, DIFFERENTIAL

localparam C_OSERDES2_OUTPUT_MODE_DIFF    = "DIFFERENTIAL";

localparam C_BUFPLL_0_LOCK_SRC       = "LOCK_TO_0";

localparam C_DQ_IODRP2_DATA_RATE             = "SDR";

localparam C_DQ_IODRP2_SERDES_MODE_MASTER    = "MASTER";

localparam C_DQ_IODRP2_SERDES_MODE_SLAVE     = "SLAVE";

localparam C_DQS_IODRP2_DATA_RATE             = "SDR";

localparam C_DQS_IODRP2_SERDES_MODE_MASTER    = "MASTER";

localparam C_DQS_IODRP2_SERDES_MODE_SLAVE     = "SLAVE";

// MIG always set the below ADD_LATENCY to zero

localparam  C_MEM_DDR3_ADD_LATENCY      =  "OFF";

localparam  C_MEM_DDR2_ADD_LATENCY      =  0;

localparam  C_MEM_MOBILE_TC_SR          =  0; // not supported

//////////////////////////////////////////////////////////////////////////////////

                                              // Attribute Declarations

                                              // Attributes set from GUI

                                              //

                                         //

   // the local param for the time slot varis according to User Port Configuration  

   // This section also needs to be customized when gernerating wrapper outputs.

   //*****************************************************************************

// For Configuration 1  and this section will be used in RAW file

localparam arbtimeslot0   = {C_ARB_TIME_SLOT_0   };

localparam arbtimeslot1   = {C_ARB_TIME_SLOT_1   };

localparam arbtimeslot2   = {C_ARB_TIME_SLOT_2   };

localparam arbtimeslot3   = {C_ARB_TIME_SLOT_3   };

localparam arbtimeslot4   = {C_ARB_TIME_SLOT_4   };

localparam arbtimeslot5   = {C_ARB_TIME_SLOT_5   };

localparam arbtimeslot6   = {C_ARB_TIME_SLOT_6   };

localparam arbtimeslot7   = {C_ARB_TIME_SLOT_7   };

localparam arbtimeslot8   = {C_ARB_TIME_SLOT_8   };

localparam arbtimeslot9   = {C_ARB_TIME_SLOT_9   };

localparam arbtimeslot10  = {C_ARB_TIME_SLOT_10  };

localparam arbtimeslot11  = {C_ARB_TIME_SLOT_11  };

// convert the memory timing to memory clock units. I

localparam MEM_RAS_VAL  = ((C_MEM_TRAS + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);

localparam MEM_RCD_VAL  = ((C_MEM_TRCD  + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);

localparam MEM_REFI_VAL = ((C_MEM_TREFI + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) - 25;

localparam MEM_RFC_VAL  = ((C_MEM_TRFC  + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);

localparam MEM_RP_VAL   = ((C_MEM_TRP   + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);

localparam MEM_WR_VAL   = ((C_MEM_TWR   + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);

localparam MEM_RTP_CK    = cdiv(C_MEM_TRTP,C_MEMCLK_PERIOD);

localparam MEM_RTP_VAL = (C_MEM_TYPE == "DDR3") ? (MEM_RTP_CK < 4) ? 4 : MEM_RTP_CK

                                               : (MEM_RTP_CK < 2) ? 2 : MEM_RTP_CK;

localparam MEM_WTR_VAL  = (C_MEM_TYPE == "DDR")   ? 2 :

                          (C_MEM_TYPE == "DDR3")  ? 4 :

                          (C_MEM_TYPE == "MDDR")  ? C_MEM_TWTR :

                          (C_MEM_TYPE == "LPDDR")  ? C_MEM_TWTR :

                          ((C_MEM_TYPE == "DDR2") && (((C_MEM_TWTR  + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) > 2)) ? ((C_MEM_TWTR  + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD) :

                          (C_MEM_TYPE == "DDR2")  ? 2

                                                  : 3 ;

localparam  C_MEM_DDR2_WRT_RECOVERY = (C_MEM_TYPE != "DDR2") ? 5: ((C_MEM_TWR   + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);

localparam  C_MEM_DDR3_WRT_RECOVERY = (C_MEM_TYPE != "DDR3") ? 5: ((C_MEM_TWR   + C_MEMCLK_PERIOD -1) /C_MEMCLK_PERIOD);

//localparam MEM_TYPE = (C_MEM_TYPE == "LPDDR") ? "MDDR": C_MEM_TYPE;

////////////////////////////////////////////////////////////////////////////

// wire Declarations

////////////////////////////////////////////////////////////////////////////

wire [31:0]  addr_in0;

reg [127:0]  allzero = 0;

// UNISIM Model <-> IOI

//dqs clock network interface

wire       dqs_out_p;

wire       dqs_out_n;