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//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version: %version

//  \   \         Application: MIG

//  /   /         Filename: mcb_soft_calibration.v

// /___/   /\     Date Last Modified: $Date: 2011/06/02 07:17:24 $

// \   \  /  \    Date Created: Mon Feb 9 2009

//  \___\/\___\

//

//Device: Spartan6

//Design Name: DDR/DDR2/DDR3/LPDDR

//Purpose:  Xilinx reference design for MCB Soft

//           Calibration

//Reference:

//

//  Revision:      Date:  Comment

//       1.0:  2/06/09:   Initial version for MIG wrapper.

//       1.1:  2/09/09:   moved Max_Value_Previous assignments to be completely inside CASE statement for next-state logic (needed to get it working correctly)

//       1.2:  2/12/09:   Many other changes.

//       1.3:  2/26/09:   Removed section with Max_Value_pre and DQS_COUNT_PREVIOUS_pre, and instead added PREVIOUS_STATE reg and moved assignment to within STATE

//       1.4:  3/02/09:   Removed comments out of sensitivity list of always block to mux SDI, SDO, CS, and ADD.  Also added reg declaration for PREVIOUS_STATE

//       1.5:  3/16/09:   Added pll_lock port, and using it to gate reset.  Changing RST (except input port) to RST_reg and gating it with pll_lock.

//       1.6:  6/05/09:   Added START_DYN_CAL_PRE with pulse on SYSRST; removed MCB_UIDQCOUNT.

//       1.7:  6/24/09:   Gave RZQ and ZIO each their own unique ADD and SDI nets

//       2.0:  7/30/09:   Added dynamic Input Termination

//       2.1:  8/02/09:   Added sampling of DQS input delays to make sure we never decrement below h00 (or increment above hEF).

//       2.2:  8/04/09:   Added 2's compliment register "DQS_COUNT_VIRTUAL", and signficantly changed the increment/decrement algorythm - now will track a virtual

//                        negative DQS_COUNT value if needed.  Got rid of DQS_COUNT_UP/DOWN registers

//       2.3:  10/10/09:  Massive overhaul

//       2.4:  10/14/09:  Fixed: from START, if SKIP_IN_TERM_CAL go to WRITE_CALIBRATE

//       2.5:  10/15/09:  Changed OVERRIDE_DQS_CAL to CALMODE_EQ_CALIBRATION, and made it override SKIP_DYNAMIC_CAL (to 1) whenever C_MC_CALIBRATION_MODE="NOCALIBRATION"

//       2.6:  12/15/09:  Changed STATE from 7-bit to 6-bit.  Dropped (* FSM_ENCODING="BINARY" *) for STATE. Moved MCB_UICMDEN = 0 from OFF_RZQ_PTERM to RST_DELAY. 

//                        Changed the "reset" always block so that RST_reg is always set to 1 when the PLL loses lock, and is now held in reset for at least 16 clocks.  Added PNSKEW option.

//       2.7:  12/23/09:  Added new states "SKEW" and "MULTIPLY_DIVIDE" to help with timing.

//       2.8:  01/14/10:  Added functionality to allow for SUSPEND.  Changed MCB_SYSRST port from wire to reg.

//       2.9:  02/01/10:  More changes to SUSPEND and Reset logic to handle SUSPEND properly.  Also - eliminated 2's comp DQS_COUNT_VIRTUAL, and replaced with 8bit TARGET_DQS_DELAY which

//                        will track most recnet Max_Value.  Eliminated DQS_COUNT_PREVIOUS. Combined DQS_COUNT_INITIAL and DQS_Delay into DQS_DELAY_INITIAL.  Changed DQS_COUNT* to DQS_DELAY*.

//                        Changed MCB_SYSRST port back to wire (from reg).

//       3.0:  02/10/10:  Added count_inc and count_dec to add a few (4) UI_CLK cycles latency to the INC and DEC signals (to deal with latency on UOREFRSHFLAG)

//       3.1:  02/23/10:  Registered the DONE_SOFTANDHARD_CAL for timing.   

//       3.2:  02/28/10:  Corrected the   WAIT_SELFREFRESH_EXIT_DQS_CAL logic;

//       3.3:  03/02/10:  Changed PNSKEW to default on (1'b1)

//       3.4:  03/04/10:  Recoded the RST_Reg logic.

//       3.5:  03/05/10:  Changed Result register to be 16-bits.  Changed DQS_NUMERATOR/DENOMINATOR values to 3/8 (from 6/16)

//       3.6:  03/10/10:  Improvements to Reset logic    

//       3.7:  04/12/10:  Added DDR2 Initialization fix to meet 400 ns wait as outlined in step d) of JEDEC DDR2 spec .

//       3.8:  05/24/10:  Added 200us Wait logic to control CKE_Train. The 200us Wait counter assumes UI_CLK freq not higher than 100 MHz.

//       3.9   02/11/11:  Apply a different skkew for the P and N inputs for the differential LDQS and UDQS signals to provide more noise immunity.

//       4.0   04/11/11:  Added sync FF for RZA_IN and ZIO_IN async inputs.

//       4.1   03/08/12:  Fixed SELFREFRESH_MCB_REQ logic. It should not need depend on the SM STATE so that

//                        MCB can come out of selfresh mode. SM requires refresh cycle to update the DQS value. 

//       4.2   05/10/12:  All P/N terms of input and bidir memory pins are initialized with value of ZERO. TZQINIT_MAXCNT

//                        are set to 8 for LPDDR,DDR and DDR2 interface .

//                        Keep the UICMDEN in assertion state when SM is in RST_DELAY state so that MCB will not start doing

//                        Premable detection until the second deassertion of MCB_SYSRST. 

//                        

// End Revision

//**********************************************************************************

`timescale 1ps/1ps

module mcb_soft_calibration # (

  parameter       C_MEM_TZQINIT_MAXCNT  = 10'd512,  // DDR3 Minimum delay between resets

  parameter       C_MC_CALIBRATION_MODE = "CALIBRATION", // if set to CALIBRATION will reset DQS IDELAY to DQS_NUMERATOR/DQS_DENOMINATOR local_param values

                                                         // if set to NOCALIBRATION then defaults to hard cal blocks setting of C_MC_CALBRATION_DELAY (Quarter, etc)

  parameter       C_SIMULATION          = "FALSE",  // Tells us whether the design is being simulated or implemented

  parameter       SKIP_IN_TERM_CAL      = 1'b0,     // provides option to skip the input termination calibration

  parameter       SKIP_DYNAMIC_CAL      = 1'b0,     // provides option to skip the dynamic delay calibration

  parameter       SKIP_DYN_IN_TERM      = 1'b1,      // provides option to skip the input termination calibration

  parameter       C_MEM_TYPE = "DDR"            // provides the memory device used for the design

  )

  (

  input   wire            UI_CLK,                   // main clock input for logic and IODRP CLK pins.  At top level, this should also connect to IODRP2_MCB CLK pins

  input   wire            RST,                      // main system reset for both this Soft Calibration block - also will act as a passthrough to MCB's SYSRST

  (* IOB = "FALSE" *) output  reg            DONE_SOFTANDHARD_CAL,

                                                    // active high flag signals soft calibration of input delays is complete and MCB_UODONECAL is high (MCB hard calib complete)

  input   wire            PLL_LOCK,                 // Lock signal from PLL

  input   wire            SELFREFRESH_REQ,

  input   wire            SELFREFRESH_MCB_MODE,

  output  reg             SELFREFRESH_MCB_REQ ,

  output  reg             SELFREFRESH_MODE,

  output  wire            IODRP_ADD,                // IODRP ADD port

  output  wire            IODRP_SDI,                // IODRP SDI port

  input   wire            RZQ_IN,                   // RZQ pin from board - expected to have a 2*R resistor to ground

  input   wire            RZQ_IODRP_SDO,            // RZQ IODRP's SDO port

  output  reg             RZQ_IODRP_CS      = 1'b0, // RZQ IODRP's CS port

  input   wire            ZIO_IN,                   // Z-stated IO pin - garanteed not to be driven externally

  input   wire            ZIO_IODRP_SDO,            // ZIO IODRP's SDO port

  output  reg             ZIO_IODRP_CS      = 1'b0, // ZIO IODRP's CS port

  output  wire            MCB_UIADD,                // to MCB's UIADD port

  output  wire            MCB_UISDI,                // to MCB's UISDI port

  input   wire            MCB_UOSDO,                // from MCB's UOSDO port (User output SDO)

  input   wire            MCB_UODONECAL,            // indicates when MCB hard calibration process is complete

  input   wire            MCB_UOREFRSHFLAG,         //  high during refresh cycle and time when MCB is innactive

  output  wire            MCB_UICS,                 // to MCB's UICS port (User Input CS)

  output  reg             MCB_UIDRPUPDATE   = 1'b1, // MCB's UIDRPUPDATE port (gets passed to IODRP2_MCB's MEMUPDATE port: this controls shadow latch used during IODRP2_MCB writes).  Currently just trasnparent

  output  wire            MCB_UIBROADCAST,          // only to MCB's UIBROADCAST port (User Input BROADCAST - gets passed to IODRP2_MCB's BKST port)

  output  reg   [4:0]     MCB_UIADDR        = 5'b0, //  to MCB's UIADDR port (gets passed to IODRP2_MCB's AUXADDR port

  output  reg             MCB_UICMDEN       = 1'b1, //  set to 1 to take control of UI interface - removes control from internal calib block

  output  reg             MCB_UIDONECAL     = 1'b0, //  set to 0 to "tell" controller that it's still in a calibrate state

  output               MCB_UIDQLOWERDEC ,

  output               MCB_UIDQLOWERINC ,

  output               MCB_UIDQUPPERDEC ,

  output               MCB_UIDQUPPERINC ,

  output  reg             MCB_UILDQSDEC     = 1'b0,

  output  reg             MCB_UILDQSINC     = 1'b0,

  output  wire            MCB_UIREAD,               //  enables read w/o writing by turning on a SDO->SDI loopback inside the IODRP2_MCBs (doesn't exist in regular IODRP2).  IODRPCTRLR_R_WB becomes don't-care.

  output  reg             MCB_UIUDQSDEC     = 1'b0,

  output  reg             MCB_UIUDQSINC     = 1'b0,

  output                  MCB_RECAL         , //  future hook to drive MCB's RECAL pin - initiates a hard re-calibration sequence when high

  output  reg             MCB_UICMD,

  output  reg             MCB_UICMDIN,

  output  reg   [3:0]     MCB_UIDQCOUNT,

  input   wire  [7:0]     MCB_UODATA,

  input   wire            MCB_UODATAVALID,

  input   wire            MCB_UOCMDREADY,

  input   wire            MCB_UO_CAL_START,

  output  wire            MCB_SYSRST,               //  drives the MCB's SYSRST pin - the main reset for MCB

  output  reg   [7:0]     Max_Value,

  output  reg            CKE_Train

  );

localparam [4:0]

          IOI_DQ0       = {4'h0, 1'b1},

          IOI_DQ1       = {4'h0, 1'b0},

          IOI_DQ2       = {4'h1, 1'b1},

          IOI_DQ3       = {4'h1, 1'b0},

          IOI_DQ4       = {4'h2, 1'b1},

          IOI_DQ5       = {4'h2, 1'b0},

          IOI_DQ6       = {4'h3, 1'b1},

          IOI_DQ7       = {4'h3, 1'b0},

          IOI_DQ8       = {4'h4, 1'b1},

          IOI_DQ9       = {4'h4, 1'b0},

          IOI_DQ10      = {4'h5, 1'b1},

          IOI_DQ11      = {4'h5, 1'b0},

          IOI_DQ12      = {4'h6, 1'b1},

          IOI_DQ13      = {4'h6, 1'b0},

          IOI_DQ14      = {4'h7, 1'b1},

          IOI_DQ15      = {4'h7, 1'b0},

          IOI_UDM       = {4'h8, 1'b1},

          IOI_LDM       = {4'h8, 1'b0},

          IOI_CK_P      = {4'h9, 1'b1},

          IOI_CK_N      = {4'h9, 1'b0},

          IOI_RESET     = {4'hA, 1'b1},

          IOI_A11       = {4'hA, 1'b0},

          IOI_WE        = {4'hB, 1'b1},

          IOI_BA2       = {4'hB, 1'b0},

          IOI_BA0       = {4'hC, 1'b1},

          IOI_BA1       = {4'hC, 1'b0},

          IOI_RASN      = {4'hD, 1'b1},

          IOI_CASN      = {4'hD, 1'b0},

          IOI_UDQS_CLK  = {4'hE, 1'b1},

          IOI_UDQS_PIN  = {4'hE, 1'b0},

          IOI_LDQS_CLK  = {4'hF, 1'b1},

          IOI_LDQS_PIN  = {4'hF, 1'b0};

localparam  [5:0]   START                     = 6'h00,

                    LOAD_RZQ_NTERM            = 6'h01,

                    WAIT1                     = 6'h02,

                    LOAD_RZQ_PTERM            = 6'h03,

                    WAIT2                     = 6'h04,

                    INC_PTERM                 = 6'h05,

                    MULTIPLY_DIVIDE           = 6'h06,

                    LOAD_ZIO_PTERM            = 6'h07,

                    WAIT3                     = 6'h08,

                    LOAD_ZIO_NTERM            = 6'h09,

                    WAIT4                     = 6'h0A,

                    INC_NTERM                 = 6'h0B,

                    SKEW                      = 6'h0C,

                    WAIT_FOR_START_BROADCAST  = 6'h0D,

                    BROADCAST_PTERM           = 6'h0E,

                    WAIT5                     = 6'h0F,

                    BROADCAST_NTERM           = 6'h10,

                    WAIT6                     = 6'h11,

                    LDQS_CLK_WRITE_P_TERM     = 6'h12,

                    LDQS_CLK_P_TERM_WAIT      = 6'h13,

                    LDQS_CLK_WRITE_N_TERM     = 6'h14,

                    LDQS_CLK_N_TERM_WAIT      = 6'h15,

                    LDQS_PIN_WRITE_P_TERM     = 6'h16,

                    LDQS_PIN_P_TERM_WAIT      = 6'h17,

                    LDQS_PIN_WRITE_N_TERM     = 6'h18,

                    LDQS_PIN_N_TERM_WAIT      = 6'h19,

                    UDQS_CLK_WRITE_P_TERM     = 6'h1A,

                    UDQS_CLK_P_TERM_WAIT      = 6'h1B,

                    UDQS_CLK_WRITE_N_TERM     = 6'h1C,

                    UDQS_CLK_N_TERM_WAIT      = 6'h1D,

                    UDQS_PIN_WRITE_P_TERM     = 6'h1E,

                    UDQS_PIN_P_TERM_WAIT      = 6'h1F,

                    UDQS_PIN_WRITE_N_TERM     = 6'h20,

                    UDQS_PIN_N_TERM_WAIT      = 6'h21,

                    OFF_RZQ_PTERM             = 6'h22,

                    WAIT7                     = 6'h23,

                    OFF_ZIO_NTERM             = 6'h24,

                    WAIT8                     = 6'h25,

                    RST_DELAY                 = 6'h26,

                    START_DYN_CAL_PRE         = 6'h27,

                    WAIT_FOR_UODONE           = 6'h28,

                    LDQS_WRITE_POS_INDELAY    = 6'h29,

                    LDQS_WAIT1                = 6'h2A,

                    LDQS_WRITE_NEG_INDELAY    = 6'h2B,

                    LDQS_WAIT2                = 6'h2C,

                    UDQS_WRITE_POS_INDELAY    = 6'h2D,

                    UDQS_WAIT1                = 6'h2E,

                    UDQS_WRITE_NEG_INDELAY    = 6'h2F,

                    UDQS_WAIT2                = 6'h30,

                    START_DYN_CAL             = 6'h31,

                    WRITE_CALIBRATE           = 6'h32,

                    WAIT9                     = 6'h33,

                    READ_MAX_VALUE            = 6'h34,

                    WAIT10                    = 6'h35,

                    ANALYZE_MAX_VALUE         = 6'h36,

                    FIRST_DYN_CAL             = 6'h37,

                    INCREMENT                 = 6'h38,

                    DECREMENT                 = 6'h39,

                    DONE                      = 6'h3A;

localparam  [1:0]   RZQ           = 2'b00,

                    ZIO           = 2'b01,

                    MCB_PORT      = 2'b11;

localparam          WRITE_MODE    = 1'b0;

localparam          READ_MODE     = 1'b1;

// IOI Registers

localparam  [7:0]   NoOp          = 8'h00,

                    DelayControl  = 8'h01,

                    PosEdgeInDly  = 8'h02,

                    NegEdgeInDly  = 8'h03,

                    PosEdgeOutDly = 8'h04,

                    NegEdgeOutDly = 8'h05,

                    MiscCtl1      = 8'h06,

                    MiscCtl2      = 8'h07,

                    MaxValue      = 8'h08;

// IOB Registers

localparam  [7:0]   PDrive        = 8'h80,

                    PTerm         = 8'h81,

                    NDrive        = 8'h82,

                    NTerm         = 8'h83,

                    SlewRateCtl   = 8'h84,

                    LVDSControl   = 8'h85,

                    MiscControl   = 8'h86,

                    InputControl  = 8'h87,

                    TestReadback  = 8'h88;

// No multi/divide is required when a 55 ohm resister is used on RZQ

//localparam          MULT          = 1;

//localparam          DIV           = 1;

// use 7/4 scaling factor when the 100 ohm RZQ is used

localparam          MULT          = 7;

localparam          DIV           = 4;

localparam          PNSKEW        = 1'b1; //Default is 1'b1. Change to 1'b0 if PSKEW and NSKEW are not required

localparam          PNSKEWDQS     = 1'b1;

localparam          MULT_S    = 9;

localparam          DIV_S     = 8;

localparam          MULT_W    = 7;

localparam          DIV_W     = 8;

localparam          DQS_NUMERATOR   = 3;

localparam          DQS_DENOMINATOR = 8;

localparam          INCDEC_THRESHOLD= 8'h03; // parameter for the threshold which triggers an inc/dec to occur.  2 for half, 4 for quarter, 3 for three eighths

reg   [5:0]   P_Term       /* synthesis syn_preserve = 1 */;

reg   [6:0]   N_Term       /* synthesis syn_preserve = 1 */;

reg   [5:0]   P_Term_s     /* synthesis syn_preserve = 1 */;

reg   [6:0]   N_Term_s     /* synthesis syn_preserve = 1 */;

reg   [5:0]   P_Term_w     /* synthesis syn_preserve = 1 */;

reg   [6:0]   N_Term_w     /* synthesis syn_preserve = 1 */;

reg   [5:0]   P_Term_Prev  /* synthesis syn_preserve = 1 */;

reg   [6:0]   N_Term_Prev  /* synthesis syn_preserve = 1 */;

//(* FSM_ENCODING="USER" *) reg [5:0] STATE = START;   //XST does not pick up "BINARY" - use COMPACT instead if binary is desired

reg [5:0] STATE ;

reg   [7:0]   IODRPCTRLR_MEMCELL_ADDR /* synthesis syn_preserve = 1 */;

reg   [7:0]   IODRPCTRLR_WRITE_DATA /* synthesis syn_preserve = 1 */;

reg   [1:0]   Active_IODRP /* synthesis syn_maxfan = 1 */;

// synthesis attribute max_fanout of Active_IODRP is 1

reg           IODRPCTRLR_R_WB = 1'b0;

reg           IODRPCTRLR_CMD_VALID = 1'b0;

reg           IODRPCTRLR_USE_BKST = 1'b0;

reg           MCB_CMD_VALID = 1'b0;

reg           MCB_USE_BKST = 1'b0;

reg           Pre_SYSRST = 1'b1 /* synthesis syn_maxfan = 5 */; //internally generated reset which will OR with RST input to drive MCB's SYSRST pin (MCB_SYSRST)

// synthesis attribute max_fanout of Pre_SYSRST is 5

reg           IODRP_SDO;

reg   [7:0]   Max_Value_Previous  = 8'b0 /* synthesis syn_preserve = 1 */;

reg   [5:0]   count = 6'd0;               //counter for adding 18 extra clock cycles after setting Calibrate bit

reg           counter_en  = 1'b0;         //counter enable for "count"

reg           First_Dyn_Cal_Done = 1'b0;  //flag - high after the very first dynamic calibration is done

wire          START_BROADCAST ;     // Trigger to start Broadcast to IODRP2_MCBs to set Input Impedance - state machine will wait for this to be high

reg   [7:0]   DQS_DELAY_INITIAL   = 8'b0 /* synthesis syn_preserve = 1 */;

reg   [7:0]   DQS_DELAY ;        // contains the latest values written to LDQS and UDQS Input Delays

reg   [7:0]   TARGET_DQS_DELAY;  // used to track the target for DQS input delays - only gets updated if the Max Value changes by more than the threshold

reg   [7:0]   counter_inc;       // used to delay Inc signal by several ui_clk cycles (to deal with latency on UOREFRSHFLAG)

reg   [7:0]   counter_dec;       // used to delay Dec signal by several ui_clk cycles (to deal with latency on UOREFRSHFLAG)

wire  [7:0]   IODRPCTRLR_READ_DATA;

wire          IODRPCTRLR_RDY_BUSY_N;

wire          IODRP_CS;

wire  [7:0]   MCB_READ_DATA;

reg           RST_reg;

reg           Block_Reset;

reg           MCB_UODATAVALID_U;

wire  [2:0]   Inc_Dec_REFRSH_Flag;  // 3-bit flag to show:Inc is needed, Dec needed, refresh cycle taking place

wire  [7:0]   Max_Value_Delta_Up;   // tracks amount latest Max Value has gone up from previous Max Value read

wire  [7:0]   Half_MV_DU;           // half of Max_Value_Delta_Up

wire  [7:0]   Max_Value_Delta_Dn;   // tracks amount latest Max Value has gone down from previous Max Value read

wire  [7:0]   Half_MV_DD;           // half of Max_Value_Delta_Dn

reg   [9:0]   RstCounter = 10'h0;

wire          rst_tmp;

reg           LastPass_DynCal;

reg           First_In_Term_Done;

wire          Inc_Flag;               // flag to increment Dynamic Delay

wire          Dec_Flag;               // flag to decrement Dynamic Delay

wire          CALMODE_EQ_CALIBRATION; // will calculate and set the DQS input delays if C_MC_CALIBRATION_MODE parameter = "CALIBRATION"

wire  [7:0]   DQS_DELAY_LOWER_LIMIT;  // Lower limit for DQS input delays 

wire  [7:0]   DQS_DELAY_UPPER_LIMIT;  // Upper limit for DQS input delays

wire          SKIP_DYN_IN_TERMINATION;//wire to allow skipping dynamic input termination if either the one-time or dynamic parameters are 1

wire          SKIP_DYNAMIC_DQS_CAL;   //wire allowing skipping dynamic DQS delay calibration if either SKIP_DYNIMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION

wire  [7:0]   Quarter_Max_Value;

wire  [7:0]   Half_Max_Value;

reg           PLL_LOCK_R1;

reg           PLL_LOCK_R2;

reg           SELFREFRESH_REQ_R1;

reg           SELFREFRESH_REQ_R2;

reg           SELFREFRESH_REQ_R3;

reg           SELFREFRESH_MCB_MODE_R1;

reg           SELFREFRESH_MCB_MODE_R2;

reg           SELFREFRESH_MCB_MODE_R3;

reg           WAIT_SELFREFRESH_EXIT_DQS_CAL;

reg           PERFORM_START_DYN_CAL_AFTER_SELFREFRESH;

reg           START_DYN_CAL_STATE_R1;

reg           PERFORM_START_DYN_CAL_AFTER_SELFREFRESH_R1;

reg           Rst_condition1;

wire          non_violating_rst;

reg [15:0]    WAIT_200us_COUNTER;

reg [7:0]     WaitTimer;

reg           WarmEnough;

wire   pre_sysrst_minpulse_width_ok;

reg [3:0] pre_sysrst_cnt;

// move the default assignment here to make FORMALITY happy.

assign START_BROADCAST = 1'b1;

assign MCB_RECAL = 1'b0;

assign MCB_UIDQLOWERDEC = 1'b0;

assign MCB_UIDQLOWERINC = 1'b0;

assign MCB_UIDQUPPERDEC = 1'b0;

assign MCB_UIDQUPPERINC = 1'b0;

// 'defines for which pass of the interleaved dynamic algorythm is taking place

`define IN_TERM_PASS  1'b0

`define DYN_CAL_PASS  1'b1

assign  Inc_Dec_REFRSH_Flag     = {Inc_Flag,Dec_Flag,MCB_UOREFRSHFLAG};

assign  Max_Value_Delta_Up      = Max_Value - Max_Value_Previous;

assign  Half_MV_DU              = {1'b0,Max_Value_Delta_Up[7:1]};

assign  Max_Value_Delta_Dn      = Max_Value_Previous - Max_Value;

assign  Half_MV_DD              = {1'b0,Max_Value_Delta_Dn[7:1]};

assign  CALMODE_EQ_CALIBRATION  = (C_MC_CALIBRATION_MODE == "CALIBRATION") ? 1'b1 : 1'b0; // will calculate and set the DQS input delays if = 1'b1

assign  Half_Max_Value          = Max_Value >> 1;

assign  Quarter_Max_Value       = Max_Value >> 2;

assign  DQS_DELAY_LOWER_LIMIT   = Quarter_Max_Value;  // limit for DQS_DELAY for decrements; could optionally be assigned to any 8-bit hex value here

assign  DQS_DELAY_UPPER_LIMIT   = Half_Max_Value;     // limit for DQS_DELAY for increments; could optionally be assigned to any 8-bit hex value here

assign  SKIP_DYN_IN_TERMINATION = SKIP_DYN_IN_TERM || SKIP_IN_TERM_CAL; //skip dynamic input termination if either the one-time or dynamic parameters are 1

assign  SKIP_DYNAMIC_DQS_CAL    = ~CALMODE_EQ_CALIBRATION || SKIP_DYNAMIC_CAL; //skip dynamic DQS delay calibration if either SKIP_DYNAMIC_CAL=1, or if C_MC_CALIBRATION_MODE=NOCALIBRATION

always @ (posedge UI_CLK)

     DONE_SOFTANDHARD_CAL    <= ((DQS_DELAY_INITIAL != 8'h00) || (STATE == DONE)) && MCB_UODONECAL;  //high when either DQS input delays initialized, or STATE=DONE and UODONECAL high

iodrp_controller iodrp_controller(

  .memcell_address  (IODRPCTRLR_MEMCELL_ADDR),

  .write_data       (IODRPCTRLR_WRITE_DATA),

  .read_data        (IODRPCTRLR_READ_DATA),

  .rd_not_write     (IODRPCTRLR_R_WB),

  .cmd_valid        (IODRPCTRLR_CMD_VALID),

  .rdy_busy_n       (IODRPCTRLR_RDY_BUSY_N),

  .use_broadcast    (1'b0),

  .sync_rst         (RST_reg),

  .DRP_CLK          (UI_CLK),

  .DRP_CS           (IODRP_CS),

  .DRP_SDI          (IODRP_SDI),

  .DRP_ADD          (IODRP_ADD),

  .DRP_SDO          (IODRP_SDO),

  .DRP_BKST         ()

  );

iodrp_mcb_controller iodrp_mcb_controller(

  .memcell_address  (IODRPCTRLR_MEMCELL_ADDR),

  .write_data       (IODRPCTRLR_WRITE_DATA),

  .read_data        (MCB_READ_DATA),

  .rd_not_write     (IODRPCTRLR_R_WB),

  .cmd_valid        (MCB_CMD_VALID),

  .rdy_busy_n       (MCB_RDY_BUSY_N),

  .use_broadcast    (MCB_USE_BKST),

  .drp_ioi_addr     (MCB_UIADDR),

  .sync_rst         (RST_reg),

  .DRP_CLK          (UI_CLK),

  .DRP_CS           (MCB_UICS),

  .DRP_SDI          (MCB_UISDI),

  .DRP_ADD          (MCB_UIADD),

  .DRP_BKST         (MCB_UIBROADCAST),

  .DRP_SDO          (MCB_UOSDO),

  .MCB_UIREAD       (MCB_UIREAD)

  );

//******************************************************************************************

// Mult_Divide Function - multiplies by a constant MULT and then divides by the DIV constant

//******************************************************************************************

function [7:0] Mult_Divide;

input   [7:0]   Input;

input   [7:0]   Mult;

input   [7:0]   Div;

reg     [3:0]   count;

reg     [15:0]   Result;

begin

  Result  = 0;

  for (count = 0; count < Mult; count = count+1) begin

    Result    = Result + Input;

  end

  Result      = Result / Div;

  Mult_Divide = Result[7:0];

end

endfunction

 always @ (posedge UI_CLK, posedge RST)

  begin

   if (RST)

     WAIT_200us_COUNTER <= (C_SIMULATION == "TRUE") ? 16'h7FF0 : 16'h0;

   else

      if (WAIT_200us_COUNTER[15])  // UI_CLK maximum is up to 100 MHz.

        WAIT_200us_COUNTER <= WAIT_200us_COUNTER                        ;

      else

        WAIT_200us_COUNTER <= WAIT_200us_COUNTER + 1'b1;

  end

generate

if( C_MEM_TYPE == "DDR2") begin : gen_cketrain_a

always @ ( posedge UI_CLK, posedge RST)

begin

if (RST)

   CKE_Train <= 1'b0;

else

  if (STATE == WAIT_FOR_UODONE && MCB_UODONECAL)

   CKE_Train <= 1'b0;

  else if (WAIT_200us_COUNTER[15] && ~MCB_UODONECAL)

   CKE_Train <= 1'b1;

  else

   CKE_Train <= 1'b0;

end

end

endgenerate

generate

if( C_MEM_TYPE != "DDR2") begin : gen_cketrain_b

always @ (RST)

   CKE_Train <= 1'b0;

end

endgenerate

//********************************************

//PLL_LOCK and Reset signals

//********************************************

localparam  RST_CNT         = 10'h010;          //defines pulse-width for reset

localparam  TZQINIT_MAXCNT  = (C_MEM_TYPE == "DDR3") ? C_MEM_TZQINIT_MAXCNT + RST_CNT : 8 + RST_CNT;

assign rst_tmp    = (~PLL_LOCK_R2 && ~SELFREFRESH_MODE); //rst_tmp becomes 1 if you lose PLL lock (registered twice for metastblty) and the device is not in SUSPEND

// Rst_contidtion1 is to make sure RESET will not happen again within TZQINIT_MAXCNT

assign non_violating_rst = RST & Rst_condition1;         //non_violating_rst is when the user-reset RST occurs and TZQINIT (min time between resets for DDR3) is not being violated

assign MCB_SYSRST = (Pre_SYSRST );

always @ (posedge UI_CLK or posedge RST ) begin

  if (RST) begin

    Block_Reset <= 1'b0;

    RstCounter  <= 10'b0;

end

  else begin

    Block_Reset <= 1'b0;                   //default to allow STATE to move out of RST_DELAY state

    if (Pre_SYSRST)

      RstCounter  <= RST_CNT;              //whenever STATE wants to reset the MCB, set RstCounter to h10

    else begin

      if (RstCounter < TZQINIT_MAXCNT) begin //if RstCounter is less than d512 than this will execute

        Block_Reset <= 1'b1;               //STATE won't exit RST_DELAY state

        RstCounter  <= RstCounter + 1'b1;  //and Rst_Counter increments

      end

    end

  end

end

always @ (posedge UI_CLK ) begin

if (RstCounter >= TZQINIT_MAXCNT)

    Rst_condition1 <= 1'b1;

else

    Rst_condition1 <= 1'b0;

end

// -- non_violating_rst asserts whenever (system-level reset) RST is asserted but must be after TZQINIT_MAXCNT is reached (min-time between resets for DDR3)

// -- After power stablizes, we will hold MCB in reset state for at least 200us before beginning initialization  process.   

// -- If the PLL loses lock during normal operation, no ui_clk will be present because mcb_drp_clk is from a BUFGCE which

//    is gated by pll's lock signal.   When the PLL locks again, the RST_reg stays asserted for at least 200 us which

//    will cause MCB to reset and reinitialize the memory afterwards.

// -- During SUSPEND operation, the PLL will lose lock but non_violating_rst remains low (de-asserted) and WAIT_200us_COUNTER stays at 

//    its terminal count.  The PLL_LOCK input does not come direct from PLL, rather it is driven by gated_pll_lock from mcb_raw_wrapper module

//    The gated_pll_lock in the mcb_raw_wrapper does not de-assert during SUSPEND operation, hence PLL_LOCK will not de-assert, and the soft calibration 

//    state machine will not reset during SUSPEND.

// -- RST_reg is the control signal that resets the mcb_soft_calibration's State Machine. The MCB_SYSRST is now equal to 

//    Pre_SYSRST. When State Machine is performing "INPUT Termination Calibration", it holds the MCB in reset by assertign MCB_SYSRST. 

//    It will deassert the MCB_SYSRST so that it can grab the bus to broadcast the P and N term value to all of the DQ pins. Once the calibrated INPUT 

//    termination is set, the State Machine will issue another short MCB_SYSRST so that MCB will use the tuned input termination during DQS preamble calibration.

always @ (posedge UI_CLK or posedge non_violating_rst ) begin

  if (non_violating_rst)

    RST_reg <= 1'b1;

  else if (~WAIT_200us_COUNTER[15])

    RST_reg <= 1'b1;

  else

    RST_reg     <= rst_tmp;

end

//********************************************

// stretching the pre_sysrst to satisfy the minimum pusle width

always @ (posedge UI_CLK )begin

  if (STATE == START_DYN_CAL_PRE)

     pre_sysrst_cnt <= pre_sysrst_cnt + 1;

  else

     pre_sysrst_cnt <= 4'b0;

end

assign pre_sysrst_minpulse_width_ok = pre_sysrst_cnt[3];

//********************************************

// SUSPEND Logic

//********************************************

always @ ( posedge UI_CLK, posedge RST) begin

  //SELFREFRESH_MCB_MODE is clocked by sysclk_2x_180

  if (RST)

    begin

      SELFREFRESH_MCB_MODE_R1 <= 1'b0;

      SELFREFRESH_MCB_MODE_R2 <= 1'b0;

      SELFREFRESH_MCB_MODE_R3 <= 1'b0;

      SELFREFRESH_REQ_R1      <= 1'b0;

      SELFREFRESH_REQ_R2      <= 1'b0;

      SELFREFRESH_REQ_R3      <= 1'b0;

      PLL_LOCK_R1             <= 1'b0;

      PLL_LOCK_R2             <= 1'b0;

    end

  else

    begin

      SELFREFRESH_MCB_MODE_R1 <= SELFREFRESH_MCB_MODE;

      SELFREFRESH_MCB_MODE_R2 <= SELFREFRESH_MCB_MODE_R1;

      SELFREFRESH_MCB_MODE_R3 <= SELFREFRESH_MCB_MODE_R2;

      SELFREFRESH_REQ_R1      <= SELFREFRESH_REQ;

      SELFREFRESH_REQ_R2      <= SELFREFRESH_REQ_R1;

      SELFREFRESH_REQ_R3      <= SELFREFRESH_REQ_R2;

      PLL_LOCK_R1             <= PLL_LOCK;

      PLL_LOCK_R2             <= PLL_LOCK_R1;