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//*****************************************************************************
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// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 3.92
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// \ \ Application : MIG
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// / / Filename : mem0 #.v
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// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:09 $
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// \ \ / \ Date Created : Tue Feb 23 2010
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// \___\/\___\
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//
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//Device : Spartan-6
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//Design Name : DDR/DDR2/DDR3/LPDDR
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//Purpose : This is a template file for the design top module. This module contains
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// all the four memory controllers and the two infrastructures. However,
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// only the enabled modules will be active and others inactive.
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//Reference :
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//Revision History :
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//*****************************************************************************
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`timescale 1ns/1ps
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(* X_CORE_INFO = "mig_v3_92_ddr_ddr_s6, Coregen 14.7" , CORE_GENERATION_INFO = "ddr_ddr_s6,mig_v3_92,{component_name=mem0, C3_MEM_INTERFACE_TYPE=DDR_SDRAM, C3_CLK_PERIOD=5000, C3_MEMORY_PART=mt46v32m16xx-5b-it, C3_MEMORY_DEVICE_WIDTH=16, C3_OUTPUT_DRV=FULL, C3_PORT_CONFIG=Two 32-bit bi-directional and four 32-bit unidirectional ports, C3_MEM_ADDR_ORDER=ROW_BANK_COLUMN, C3_PORT_ENABLE=Port0_Port1_Port2_Port3_Port4_Port5, C3_CLASS_ADDR=II, C3_CLASS_DATA=II, C3_INPUT_PIN_TERMINATION=EXTERN_TERM, C3_DATA_TERMINATION=25 Ohms, C3_CLKFBOUT_MULT_F=4, C3_CLKOUT_DIVIDE=2, C3_DEBUG_PORT=0, INPUT_CLK_TYPE=Single-Ended, LANGUAGE=Verilog, SYNTHESIS_TOOL=Foundation_ISE, NO_OF_CONTROLLERS=1}" *)
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module mem0 #
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(
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parameter C3_P0_MASK_SIZE = 4,
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parameter C3_P0_DATA_PORT_SIZE = 32,
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parameter C3_P1_MASK_SIZE = 4,
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parameter C3_P1_DATA_PORT_SIZE = 32,
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parameter DEBUG_EN = 0,
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// # = 1, Enable debug signals/controls,
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// = 0, Disable debug signals/controls.
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parameter C3_MEMCLK_PERIOD = 5000,
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// Memory data transfer clock period
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parameter C3_CALIB_SOFT_IP = "TRUE",
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// # = TRUE, Enables the soft calibration logic,
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// # = FALSE, Disables the soft calibration logic.
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parameter C3_SIMULATION = "FALSE",
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// # = TRUE, Simulating the design. Useful to reduce the simulation time,
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// # = FALSE, Implementing the design.
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parameter C3_RST_ACT_LOW = 0,
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// # = 1 for active low reset,
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// # = 0 for active high reset.
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parameter C3_INPUT_CLK_TYPE = "SINGLE_ENDED",
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// input clock type DIFFERENTIAL or SINGLE_ENDED
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parameter C3_MEM_ADDR_ORDER = "ROW_BANK_COLUMN",
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// The order in which user address is provided to the memory controller,
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// ROW_BANK_COLUMN or BANK_ROW_COLUMN
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parameter C3_NUM_DQ_PINS = 16,
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// External memory data width
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parameter C3_MEM_ADDR_WIDTH = 13,
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// External memory address width
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parameter C3_MEM_BANKADDR_WIDTH = 2
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// External memory bank address width
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)
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(
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inout [C3_NUM_DQ_PINS-1:0] mcb3_dram_dq,
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output [C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a,
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output [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba,
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output mcb3_dram_cke,
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output mcb3_dram_ras_n,
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output mcb3_dram_cas_n,
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output mcb3_dram_we_n,
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output mcb3_dram_dm,
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inout mcb3_dram_udqs,
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inout mcb3_rzq,
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output mcb3_dram_udm,
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input c3_sys_clk,
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input c3_sys_rst_i,
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output c3_calib_done,
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output c3_clk0,
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output c3_rst0,
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inout mcb3_dram_dqs,
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output mcb3_dram_ck,
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output mcb3_dram_ck_n,
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input c3_p0_cmd_clk,
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input c3_p0_cmd_en,
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input [2:0] c3_p0_cmd_instr,
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input [5:0] c3_p0_cmd_bl,
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input [29:0] c3_p0_cmd_byte_addr,
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output c3_p0_cmd_empty,
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output c3_p0_cmd_full,
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input c3_p0_wr_clk,
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input c3_p0_wr_en,
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input [C3_P0_MASK_SIZE - 1:0] c3_p0_wr_mask,
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input [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_wr_data,
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output c3_p0_wr_full,
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output c3_p0_wr_empty,
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output [6:0] c3_p0_wr_count,
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output c3_p0_wr_underrun,
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output c3_p0_wr_error,
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input c3_p0_rd_clk,
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input c3_p0_rd_en,
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output [C3_P0_DATA_PORT_SIZE - 1:0] c3_p0_rd_data,
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output c3_p0_rd_full,
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output c3_p0_rd_empty,
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output [6:0] c3_p0_rd_count,
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output c3_p0_rd_overflow,
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output c3_p0_rd_error,
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input c3_p1_cmd_clk,
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input c3_p1_cmd_en,
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input [2:0] c3_p1_cmd_instr,
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input [5:0] c3_p1_cmd_bl,
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input [29:0] c3_p1_cmd_byte_addr,
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output c3_p1_cmd_empty,
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output c3_p1_cmd_full,
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input c3_p1_wr_clk,
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input c3_p1_wr_en,
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input [C3_P1_MASK_SIZE - 1:0] c3_p1_wr_mask,
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input [C3_P1_DATA_PORT_SIZE - 1:0] c3_p1_wr_data,
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output c3_p1_wr_full,
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output c3_p1_wr_empty,
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output [6:0] c3_p1_wr_count,
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output c3_p1_wr_underrun,
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output c3_p1_wr_error,
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input c3_p1_rd_clk,
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input c3_p1_rd_en,
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output [C3_P1_DATA_PORT_SIZE - 1:0] c3_p1_rd_data,
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output c3_p1_rd_full,
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output c3_p1_rd_empty,
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output [6:0] c3_p1_rd_count,
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output c3_p1_rd_overflow,
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output c3_p1_rd_error,
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input c3_p2_cmd_clk,
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input c3_p2_cmd_en,
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input [2:0] c3_p2_cmd_instr,
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input [5:0] c3_p2_cmd_bl,
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input [29:0] c3_p2_cmd_byte_addr,
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output c3_p2_cmd_empty,
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output c3_p2_cmd_full,
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input c3_p2_wr_clk,
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input c3_p2_wr_en,
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input [3:0] c3_p2_wr_mask,
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input [31:0] c3_p2_wr_data,
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output c3_p2_wr_full,
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output c3_p2_wr_empty,
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output [6:0] c3_p2_wr_count,
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output c3_p2_wr_underrun,
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output c3_p2_wr_error,
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input c3_p3_cmd_clk,
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input c3_p3_cmd_en,
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input [2:0] c3_p3_cmd_instr,
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input [5:0] c3_p3_cmd_bl,
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input [29:0] c3_p3_cmd_byte_addr,
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output c3_p3_cmd_empty,
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output c3_p3_cmd_full,
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input c3_p3_rd_clk,
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input c3_p3_rd_en,
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output [31:0] c3_p3_rd_data,
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output c3_p3_rd_full,
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output c3_p3_rd_empty,
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output [6:0] c3_p3_rd_count,
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output c3_p3_rd_overflow,
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output c3_p3_rd_error,
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input c3_p4_cmd_clk,
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input c3_p4_cmd_en,
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input [2:0] c3_p4_cmd_instr,
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input [5:0] c3_p4_cmd_bl,
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input [29:0] c3_p4_cmd_byte_addr,
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output c3_p4_cmd_empty,
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output c3_p4_cmd_full,
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input c3_p4_wr_clk,
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input c3_p4_wr_en,
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input [3:0] c3_p4_wr_mask,
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input [31:0] c3_p4_wr_data,
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output c3_p4_wr_full,
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output c3_p4_wr_empty,
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output [6:0] c3_p4_wr_count,
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output c3_p4_wr_underrun,
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output c3_p4_wr_error,
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input c3_p5_cmd_clk,
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input c3_p5_cmd_en,
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input [2:0] c3_p5_cmd_instr,
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input [5:0] c3_p5_cmd_bl,
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input [29:0] c3_p5_cmd_byte_addr,
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output c3_p5_cmd_empty,
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output c3_p5_cmd_full,
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input c3_p5_rd_clk,
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input c3_p5_rd_en,
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output [31:0] c3_p5_rd_data,
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output c3_p5_rd_full,
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output c3_p5_rd_empty,
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output [6:0] c3_p5_rd_count,
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output c3_p5_rd_overflow,
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output c3_p5_rd_error
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);
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// The parameter CX_PORT_ENABLE shows all the active user ports in the design.
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// For example, the value 6'b111100 tells that only port-2, port-3, port-4
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// and port-5 are enabled. The other two ports are inactive. An inactive port
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// can be a disabled port or an invisible logical port. Few examples to the
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// invisible logical port are port-4 and port-5 in the user port configuration,
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// Config-2: Four 32-bit bi-directional ports and the ports port-2 through
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// port-5 in Config-4: Two 64-bit bi-directional ports. Please look into the
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// Chapter-2 of ug388.pdf in the /docs directory for further details.
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localparam C3_PORT_ENABLE = 6'b111111;
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localparam C3_PORT_CONFIG = "B32_B32_W32_R32_W32_R32";
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localparam C3_CLKOUT0_DIVIDE = 2;
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localparam C3_CLKOUT1_DIVIDE = 2;
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localparam C3_CLKOUT2_DIVIDE = 16;
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localparam C3_CLKOUT3_DIVIDE = 8;
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localparam C3_CLKFBOUT_MULT = 4;
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localparam C3_DIVCLK_DIVIDE = 1;
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localparam C3_ARB_ALGORITHM = 0;
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localparam C3_ARB_NUM_TIME_SLOTS = 12;
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localparam C3_ARB_TIME_SLOT_0 = 18'o012345;
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localparam C3_ARB_TIME_SLOT_1 = 18'o123450;
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localparam C3_ARB_TIME_SLOT_2 = 18'o234501;
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localparam C3_ARB_TIME_SLOT_3 = 18'o345012;
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localparam C3_ARB_TIME_SLOT_4 = 18'o450123;
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localparam C3_ARB_TIME_SLOT_5 = 18'o501234;
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localparam C3_ARB_TIME_SLOT_6 = 18'o012345;
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localparam C3_ARB_TIME_SLOT_7 = 18'o123450;
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localparam C3_ARB_TIME_SLOT_8 = 18'o234501;
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localparam C3_ARB_TIME_SLOT_9 = 18'o345012;
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localparam C3_ARB_TIME_SLOT_10 = 18'o450123;
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localparam C3_ARB_TIME_SLOT_11 = 18'o501234;
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localparam C3_MEM_TRAS = 40000;
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localparam C3_MEM_TRCD = 15000;
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localparam C3_MEM_TREFI = 7800000;
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localparam C3_MEM_TRFC = 70000;
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localparam C3_MEM_TRP = 15000;
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localparam C3_MEM_TWR = 15000;
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localparam C3_MEM_TRTP = 7500;
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localparam C3_MEM_TWTR = 2;
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localparam C3_MEM_TYPE = "DDR";
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localparam C3_MEM_DENSITY = "512Mb";
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localparam C3_MEM_BURST_LEN = 4;
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localparam C3_MEM_CAS_LATENCY = 3;
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localparam C3_MEM_NUM_COL_BITS = 10;
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localparam C3_MEM_DDR1_2_ODS = "FULL";
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localparam C3_MEM_DDR2_RTT = "150OHMS";
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localparam C3_MEM_DDR2_DIFF_DQS_EN = "YES";
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localparam C3_MEM_DDR2_3_PA_SR = "FULL";
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localparam C3_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL";
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localparam C3_MEM_DDR3_CAS_LATENCY = 6;
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284 |
|
|
localparam C3_MEM_DDR3_ODS = "DIV6";
|
285 |
|
|
localparam C3_MEM_DDR3_RTT = "DIV2";
|
286 |
|
|
localparam C3_MEM_DDR3_CAS_WR_LATENCY = 5;
|
287 |
|
|
localparam C3_MEM_DDR3_AUTO_SR = "ENABLED";
|
288 |
|
|
localparam C3_MEM_MOBILE_PA_SR = "FULL";
|
289 |
|
|
localparam C3_MEM_MDDR_ODS = "FULL";
|
290 |
|
|
localparam C3_MC_CALIB_BYPASS = "NO";
|
291 |
|
|
localparam C3_MC_CALIBRATION_MODE = "CALIBRATION";
|
292 |
|
|
localparam C3_MC_CALIBRATION_DELAY = "HALF";
|
293 |
|
|
localparam C3_SKIP_IN_TERM_CAL = 1;
|
294 |
|
|
localparam C3_SKIP_DYNAMIC_CAL = 0;
|
295 |
|
|
localparam C3_LDQSP_TAP_DELAY_VAL = 0;
|
296 |
|
|
localparam C3_LDQSN_TAP_DELAY_VAL = 0;
|
297 |
|
|
localparam C3_UDQSP_TAP_DELAY_VAL = 0;
|
298 |
|
|
localparam C3_UDQSN_TAP_DELAY_VAL = 0;
|
299 |
|
|
localparam C3_DQ0_TAP_DELAY_VAL = 0;
|
300 |
|
|
localparam C3_DQ1_TAP_DELAY_VAL = 0;
|
301 |
|
|
localparam C3_DQ2_TAP_DELAY_VAL = 0;
|
302 |
|
|
localparam C3_DQ3_TAP_DELAY_VAL = 0;
|
303 |
|
|
localparam C3_DQ4_TAP_DELAY_VAL = 0;
|
304 |
|
|
localparam C3_DQ5_TAP_DELAY_VAL = 0;
|
305 |
|
|
localparam C3_DQ6_TAP_DELAY_VAL = 0;
|
306 |
|
|
localparam C3_DQ7_TAP_DELAY_VAL = 0;
|
307 |
|
|
localparam C3_DQ8_TAP_DELAY_VAL = 0;
|
308 |
|
|
localparam C3_DQ9_TAP_DELAY_VAL = 0;
|
309 |
|
|
localparam C3_DQ10_TAP_DELAY_VAL = 0;
|
310 |
|
|
localparam C3_DQ11_TAP_DELAY_VAL = 0;
|
311 |
|
|
localparam C3_DQ12_TAP_DELAY_VAL = 0;
|
312 |
|
|
localparam C3_DQ13_TAP_DELAY_VAL = 0;
|
313 |
|
|
localparam C3_DQ14_TAP_DELAY_VAL = 0;
|
314 |
|
|
localparam C3_DQ15_TAP_DELAY_VAL = 0;
|
315 |
|
|
localparam C3_MCB_USE_EXTERNAL_BUFPLL = 1;
|
316 |
|
|
localparam C3_SMALL_DEVICE = "FALSE"; // The parameter is set to TRUE for all packages of xc6slx9 device
|
317 |
|
|
// as most of them cannot fit the complete example design when the
|
318 |
|
|
// Chip scope modules are enabled
|
319 |
|
|
localparam C3_INCLK_PERIOD = ((C3_MEMCLK_PERIOD * C3_CLKFBOUT_MULT) / (C3_DIVCLK_DIVIDE * C3_CLKOUT0_DIVIDE * 2));
|
320 |
|
|
localparam DBG_WR_STS_WIDTH = 32;
|
321 |
|
|
localparam DBG_RD_STS_WIDTH = 32;
|
322 |
|
|
localparam C3_ARB_TIME0_SLOT = {C3_ARB_TIME_SLOT_0[17:15], C3_ARB_TIME_SLOT_0[14:12], C3_ARB_TIME_SLOT_0[11:9], C3_ARB_TIME_SLOT_0[8:6], C3_ARB_TIME_SLOT_0[5:3], C3_ARB_TIME_SLOT_0[2:0]};
|
323 |
|
|
localparam C3_ARB_TIME1_SLOT = {C3_ARB_TIME_SLOT_1[17:15], C3_ARB_TIME_SLOT_1[14:12], C3_ARB_TIME_SLOT_1[11:9], C3_ARB_TIME_SLOT_1[8:6], C3_ARB_TIME_SLOT_1[5:3], C3_ARB_TIME_SLOT_1[2:0]};
|
324 |
|
|
localparam C3_ARB_TIME2_SLOT = {C3_ARB_TIME_SLOT_2[17:15], C3_ARB_TIME_SLOT_2[14:12], C3_ARB_TIME_SLOT_2[11:9], C3_ARB_TIME_SLOT_2[8:6], C3_ARB_TIME_SLOT_2[5:3], C3_ARB_TIME_SLOT_2[2:0]};
|
325 |
|
|
localparam C3_ARB_TIME3_SLOT = {C3_ARB_TIME_SLOT_3[17:15], C3_ARB_TIME_SLOT_3[14:12], C3_ARB_TIME_SLOT_3[11:9], C3_ARB_TIME_SLOT_3[8:6], C3_ARB_TIME_SLOT_3[5:3], C3_ARB_TIME_SLOT_3[2:0]};
|
326 |
|
|
localparam C3_ARB_TIME4_SLOT = {C3_ARB_TIME_SLOT_4[17:15], C3_ARB_TIME_SLOT_4[14:12], C3_ARB_TIME_SLOT_4[11:9], C3_ARB_TIME_SLOT_4[8:6], C3_ARB_TIME_SLOT_4[5:3], C3_ARB_TIME_SLOT_4[2:0]};
|
327 |
|
|
localparam C3_ARB_TIME5_SLOT = {C3_ARB_TIME_SLOT_5[17:15], C3_ARB_TIME_SLOT_5[14:12], C3_ARB_TIME_SLOT_5[11:9], C3_ARB_TIME_SLOT_5[8:6], C3_ARB_TIME_SLOT_5[5:3], C3_ARB_TIME_SLOT_5[2:0]};
|
328 |
|
|
localparam C3_ARB_TIME6_SLOT = {C3_ARB_TIME_SLOT_6[17:15], C3_ARB_TIME_SLOT_6[14:12], C3_ARB_TIME_SLOT_6[11:9], C3_ARB_TIME_SLOT_6[8:6], C3_ARB_TIME_SLOT_6[5:3], C3_ARB_TIME_SLOT_6[2:0]};
|
329 |
|
|
localparam C3_ARB_TIME7_SLOT = {C3_ARB_TIME_SLOT_7[17:15], C3_ARB_TIME_SLOT_7[14:12], C3_ARB_TIME_SLOT_7[11:9], C3_ARB_TIME_SLOT_7[8:6], C3_ARB_TIME_SLOT_7[5:3], C3_ARB_TIME_SLOT_7[2:0]};
|
330 |
|
|
localparam C3_ARB_TIME8_SLOT = {C3_ARB_TIME_SLOT_8[17:15], C3_ARB_TIME_SLOT_8[14:12], C3_ARB_TIME_SLOT_8[11:9], C3_ARB_TIME_SLOT_8[8:6], C3_ARB_TIME_SLOT_8[5:3], C3_ARB_TIME_SLOT_8[2:0]};
|
331 |
|
|
localparam C3_ARB_TIME9_SLOT = {C3_ARB_TIME_SLOT_9[17:15], C3_ARB_TIME_SLOT_9[14:12], C3_ARB_TIME_SLOT_9[11:9], C3_ARB_TIME_SLOT_9[8:6], C3_ARB_TIME_SLOT_9[5:3], C3_ARB_TIME_SLOT_9[2:0]};
|
332 |
|
|
localparam C3_ARB_TIME10_SLOT = {C3_ARB_TIME_SLOT_10[17:15], C3_ARB_TIME_SLOT_10[14:12], C3_ARB_TIME_SLOT_10[11:9], C3_ARB_TIME_SLOT_10[8:6], C3_ARB_TIME_SLOT_10[5:3], C3_ARB_TIME_SLOT_10[2:0]};
|
333 |
|
|
localparam C3_ARB_TIME11_SLOT = {C3_ARB_TIME_SLOT_11[17:15], C3_ARB_TIME_SLOT_11[14:12], C3_ARB_TIME_SLOT_11[11:9], C3_ARB_TIME_SLOT_11[8:6], C3_ARB_TIME_SLOT_11[5:3], C3_ARB_TIME_SLOT_11[2:0]};
|
334 |
|
|
|
335 |
|
|
wire c3_sys_clk_p;
|
336 |
|
|
wire c3_sys_clk_n;
|
337 |
|
|
wire c3_async_rst;
|
338 |
|
|
wire c3_sysclk_2x;
|
339 |
|
|
wire c3_sysclk_2x_180;
|
340 |
|
|
wire c3_pll_ce_0;
|
341 |
|
|
wire c3_pll_ce_90;
|
342 |
|
|
wire c3_pll_lock;
|
343 |
|
|
wire c3_mcb_drp_clk;
|
344 |
|
|
wire c3_cmp_error;
|
345 |
|
|
wire c3_cmp_data_valid;
|
346 |
|
|
wire c3_vio_modify_enable;
|
347 |
|
|
wire [2:0] c3_vio_data_mode_value;
|
348 |
|
|
wire [2:0] c3_vio_addr_mode_value;
|
349 |
|
|
wire [31:0] c3_cmp_data;
|
350 |
|
|
wire c3_p2_rd_clk;
|
351 |
|
|
wire c3_p2_rd_en;
|
352 |
|
|
wire[31:0] c3_p2_rd_data;
|
353 |
|
|
wire c3_p2_rd_full;
|
354 |
|
|
wire c3_p2_rd_empty;
|
355 |
|
|
wire[6:0] c3_p2_rd_count;
|
356 |
|
|
wire c3_p2_rd_overflow;
|
357 |
|
|
wire c3_p2_rd_error;
|
358 |
|
|
wire c3_p3_wr_clk;
|
359 |
|
|
wire c3_p3_wr_en;
|
360 |
|
|
wire[3:0] c3_p3_wr_mask;
|
361 |
|
|
wire[31:0] c3_p3_wr_data;
|
362 |
|
|
wire c3_p3_wr_full;
|
363 |
|
|
wire c3_p3_wr_empty;
|
364 |
|
|
wire[6:0] c3_p3_wr_count;
|
365 |
|
|
wire c3_p3_wr_underrun;
|
366 |
|
|
wire c3_p3_wr_error;
|
367 |
|
|
wire c3_p4_rd_clk;
|
368 |
|
|
wire c3_p4_rd_en;
|
369 |
|
|
wire[31:0] c3_p4_rd_data;
|
370 |
|
|
wire c3_p4_rd_full;
|
371 |
|
|
wire c3_p4_rd_empty;
|
372 |
|
|
wire[6:0] c3_p4_rd_count;
|
373 |
|
|
wire c3_p4_rd_overflow;
|
374 |
|
|
wire c3_p4_rd_error;
|
375 |
|
|
wire c3_p5_wr_clk;
|
376 |
|
|
wire c3_p5_wr_en;
|
377 |
|
|
wire[3:0] c3_p5_wr_mask;
|
378 |
|
|
wire[31:0] c3_p5_wr_data;
|
379 |
|
|
wire c3_p5_wr_full;
|
380 |
|
|
wire c3_p5_wr_empty;
|
381 |
|
|
wire[6:0] c3_p5_wr_count;
|
382 |
|
|
wire c3_p5_wr_underrun;
|
383 |
|
|
wire c3_p5_wr_error;
|
384 |
|
|
|
385 |
|
|
|
386 |
|
|
reg c1_aresetn;
|
387 |
|
|
reg c3_aresetn;
|
388 |
|
|
reg c4_aresetn;
|
389 |
|
|
reg c5_aresetn;
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
|
393 |
|
|
assign c3_sys_clk_p = 1'b0;
|
394 |
|
|
assign c3_sys_clk_n = 1'b0;
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
|
398 |
|
|
|
399 |
|
|
// Infrastructure-3 instantiation
|
400 |
|
|
infrastructure #
|
401 |
|
|
(
|
402 |
|
|
.C_INCLK_PERIOD (C3_INCLK_PERIOD),
|
403 |
|
|
.C_RST_ACT_LOW (C3_RST_ACT_LOW),
|
404 |
|
|
.C_INPUT_CLK_TYPE (C3_INPUT_CLK_TYPE),
|
405 |
|
|
.C_CLKOUT0_DIVIDE (C3_CLKOUT0_DIVIDE),
|
406 |
|
|
.C_CLKOUT1_DIVIDE (C3_CLKOUT1_DIVIDE),
|
407 |
|
|
.C_CLKOUT2_DIVIDE (C3_CLKOUT2_DIVIDE),
|
408 |
|
|
.C_CLKOUT3_DIVIDE (C3_CLKOUT3_DIVIDE),
|
409 |
|
|
.C_CLKFBOUT_MULT (C3_CLKFBOUT_MULT),
|
410 |
|
|
.C_DIVCLK_DIVIDE (C3_DIVCLK_DIVIDE)
|
411 |
|
|
)
|
412 |
|
|
memc3_infrastructure_inst
|
413 |
|
|
(
|
414 |
|
|
.sys_clk_p (c3_sys_clk_p), // [input] differential p type clock from board
|
415 |
|
|
.sys_clk_n (c3_sys_clk_n), // [input] differential n type clock from board
|
416 |
|
|
.sys_clk (c3_sys_clk), // [input] single ended input clock from board
|
417 |
|
|
.sys_rst_i (c3_sys_rst_i),
|
418 |
|
|
.clk0 (c3_clk0), // [output] user clock which determines the operating frequency of user interface ports
|
419 |
|
|
.rst0 (c3_rst0),
|
420 |
|
|
.async_rst (c3_async_rst),
|
421 |
|
|
.sysclk_2x (c3_sysclk_2x),
|
422 |
|
|
.sysclk_2x_180 (c3_sysclk_2x_180),
|
423 |
|
|
.pll_ce_0 (c3_pll_ce_0),
|
424 |
|
|
.pll_ce_90 (c3_pll_ce_90),
|
425 |
|
|
.pll_lock (c3_pll_lock),
|
426 |
|
|
.mcb_drp_clk (c3_mcb_drp_clk)
|
427 |
|
|
);
|
428 |
|
|
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
// Controller-3 instantiation
|
432 |
|
|
memc_wrapper #
|
433 |
|
|
(
|
434 |
|
|
.C_MEMCLK_PERIOD (C3_MEMCLK_PERIOD),
|
435 |
|
|
.C_CALIB_SOFT_IP (C3_CALIB_SOFT_IP),
|
436 |
|
|
//synthesis translate_off
|
437 |
|
|
.C_SIMULATION (C3_SIMULATION),
|
438 |
|
|
//synthesis translate_on
|
439 |
|
|
.C_ARB_NUM_TIME_SLOTS (C3_ARB_NUM_TIME_SLOTS),
|
440 |
|
|
.C_ARB_TIME_SLOT_0 (C3_ARB_TIME0_SLOT),
|
441 |
|
|
.C_ARB_TIME_SLOT_1 (C3_ARB_TIME1_SLOT),
|
442 |
|
|
.C_ARB_TIME_SLOT_2 (C3_ARB_TIME2_SLOT),
|
443 |
|
|
.C_ARB_TIME_SLOT_3 (C3_ARB_TIME3_SLOT),
|
444 |
|
|
.C_ARB_TIME_SLOT_4 (C3_ARB_TIME4_SLOT),
|
445 |
|
|
.C_ARB_TIME_SLOT_5 (C3_ARB_TIME5_SLOT),
|
446 |
|
|
.C_ARB_TIME_SLOT_6 (C3_ARB_TIME6_SLOT),
|
447 |
|
|
.C_ARB_TIME_SLOT_7 (C3_ARB_TIME7_SLOT),
|
448 |
|
|
.C_ARB_TIME_SLOT_8 (C3_ARB_TIME8_SLOT),
|
449 |
|
|
.C_ARB_TIME_SLOT_9 (C3_ARB_TIME9_SLOT),
|
450 |
|
|
.C_ARB_TIME_SLOT_10 (C3_ARB_TIME10_SLOT),
|
451 |
|
|
.C_ARB_TIME_SLOT_11 (C3_ARB_TIME11_SLOT),
|
452 |
|
|
.C_ARB_ALGORITHM (C3_ARB_ALGORITHM),
|
453 |
|
|
.C_PORT_ENABLE (C3_PORT_ENABLE),
|
454 |
|
|
.C_PORT_CONFIG (C3_PORT_CONFIG),
|
455 |
|
|
.C_MEM_TRAS (C3_MEM_TRAS),
|
456 |
|
|
.C_MEM_TRCD (C3_MEM_TRCD),
|
457 |
|
|
.C_MEM_TREFI (C3_MEM_TREFI),
|
458 |
|
|
.C_MEM_TRFC (C3_MEM_TRFC),
|
459 |
|
|
.C_MEM_TRP (C3_MEM_TRP),
|
460 |
|
|
.C_MEM_TWR (C3_MEM_TWR),
|
461 |
|
|
.C_MEM_TRTP (C3_MEM_TRTP),
|
462 |
|
|
.C_MEM_TWTR (C3_MEM_TWTR),
|
463 |
|
|
.C_MEM_ADDR_ORDER (C3_MEM_ADDR_ORDER),
|
464 |
|
|
.C_NUM_DQ_PINS (C3_NUM_DQ_PINS),
|
465 |
|
|
.C_MEM_TYPE (C3_MEM_TYPE),
|
466 |
|
|
.C_MEM_DENSITY (C3_MEM_DENSITY),
|
467 |
|
|
.C_MEM_BURST_LEN (C3_MEM_BURST_LEN),
|
468 |
|
|
.C_MEM_CAS_LATENCY (C3_MEM_CAS_LATENCY),
|
469 |
|
|
.C_MEM_ADDR_WIDTH (C3_MEM_ADDR_WIDTH),
|
470 |
|
|
.C_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH),
|
471 |
|
|
.C_MEM_NUM_COL_BITS (C3_MEM_NUM_COL_BITS),
|
472 |
|
|
.C_MEM_DDR1_2_ODS (C3_MEM_DDR1_2_ODS),
|
473 |
|
|
.C_MEM_DDR2_RTT (C3_MEM_DDR2_RTT),
|
474 |
|
|
.C_MEM_DDR2_DIFF_DQS_EN (C3_MEM_DDR2_DIFF_DQS_EN),
|
475 |
|
|
.C_MEM_DDR2_3_PA_SR (C3_MEM_DDR2_3_PA_SR),
|
476 |
|
|
.C_MEM_DDR2_3_HIGH_TEMP_SR (C3_MEM_DDR2_3_HIGH_TEMP_SR),
|
477 |
|
|
.C_MEM_DDR3_CAS_LATENCY (C3_MEM_DDR3_CAS_LATENCY),
|
478 |
|
|
.C_MEM_DDR3_ODS (C3_MEM_DDR3_ODS),
|
479 |
|
|
.C_MEM_DDR3_RTT (C3_MEM_DDR3_RTT),
|
480 |
|
|
.C_MEM_DDR3_CAS_WR_LATENCY (C3_MEM_DDR3_CAS_WR_LATENCY),
|
481 |
|
|
.C_MEM_DDR3_AUTO_SR (C3_MEM_DDR3_AUTO_SR),
|
482 |
|
|
.C_MEM_MOBILE_PA_SR (C3_MEM_MOBILE_PA_SR),
|
483 |
|
|
.C_MEM_MDDR_ODS (C3_MEM_MDDR_ODS),
|
484 |
|
|
.C_MC_CALIB_BYPASS (C3_MC_CALIB_BYPASS),
|
485 |
|
|
.C_MC_CALIBRATION_MODE (C3_MC_CALIBRATION_MODE),
|
486 |
|
|
.C_MC_CALIBRATION_DELAY (C3_MC_CALIBRATION_DELAY),
|
487 |
|
|
.C_SKIP_IN_TERM_CAL (C3_SKIP_IN_TERM_CAL),
|
488 |
|
|
.C_SKIP_DYNAMIC_CAL (C3_SKIP_DYNAMIC_CAL),
|
489 |
|
|
.LDQSP_TAP_DELAY_VAL (C3_LDQSP_TAP_DELAY_VAL),
|
490 |
|
|
.UDQSP_TAP_DELAY_VAL (C3_UDQSP_TAP_DELAY_VAL),
|
491 |
|
|
.LDQSN_TAP_DELAY_VAL (C3_LDQSN_TAP_DELAY_VAL),
|
492 |
|
|
.UDQSN_TAP_DELAY_VAL (C3_UDQSN_TAP_DELAY_VAL),
|
493 |
|
|
.DQ0_TAP_DELAY_VAL (C3_DQ0_TAP_DELAY_VAL),
|
494 |
|
|
.DQ1_TAP_DELAY_VAL (C3_DQ1_TAP_DELAY_VAL),
|
495 |
|
|
.DQ2_TAP_DELAY_VAL (C3_DQ2_TAP_DELAY_VAL),
|
496 |
|
|
.DQ3_TAP_DELAY_VAL (C3_DQ3_TAP_DELAY_VAL),
|
497 |
|
|
.DQ4_TAP_DELAY_VAL (C3_DQ4_TAP_DELAY_VAL),
|
498 |
|
|
.DQ5_TAP_DELAY_VAL (C3_DQ5_TAP_DELAY_VAL),
|
499 |
|
|
.DQ6_TAP_DELAY_VAL (C3_DQ6_TAP_DELAY_VAL),
|
500 |
|
|
.DQ7_TAP_DELAY_VAL (C3_DQ7_TAP_DELAY_VAL),
|
501 |
|
|
.DQ8_TAP_DELAY_VAL (C3_DQ8_TAP_DELAY_VAL),
|
502 |
|
|
.DQ9_TAP_DELAY_VAL (C3_DQ9_TAP_DELAY_VAL),
|
503 |
|
|
.DQ10_TAP_DELAY_VAL (C3_DQ10_TAP_DELAY_VAL),
|
504 |
|
|
.DQ11_TAP_DELAY_VAL (C3_DQ11_TAP_DELAY_VAL),
|
505 |
|
|
.DQ12_TAP_DELAY_VAL (C3_DQ12_TAP_DELAY_VAL),
|
506 |
|
|
.DQ13_TAP_DELAY_VAL (C3_DQ13_TAP_DELAY_VAL),
|
507 |
|
|
.DQ14_TAP_DELAY_VAL (C3_DQ14_TAP_DELAY_VAL),
|
508 |
|
|
.DQ15_TAP_DELAY_VAL (C3_DQ15_TAP_DELAY_VAL),
|
509 |
|
|
.C_P0_MASK_SIZE (C3_P0_MASK_SIZE),
|
510 |
|
|
.C_P0_DATA_PORT_SIZE (C3_P0_DATA_PORT_SIZE),
|
511 |
|
|
.C_P1_MASK_SIZE (C3_P1_MASK_SIZE),
|
512 |
|
|
.C_P1_DATA_PORT_SIZE (C3_P1_DATA_PORT_SIZE)
|
513 |
|
|
)
|
514 |
|
|
|
515 |
|
|
memc3_wrapper_inst
|
516 |
|
|
(
|
517 |
|
|
.mcbx_dram_addr (mcb3_dram_a),
|
518 |
|
|
.mcbx_dram_ba (mcb3_dram_ba),
|
519 |
|
|
.mcbx_dram_ras_n (mcb3_dram_ras_n),
|
520 |
|
|
.mcbx_dram_cas_n (mcb3_dram_cas_n),
|
521 |
|
|
.mcbx_dram_we_n (mcb3_dram_we_n),
|
522 |
|
|
.mcbx_dram_cke (mcb3_dram_cke),
|
523 |
|
|
.mcbx_dram_clk (mcb3_dram_ck),
|
524 |
|
|
.mcbx_dram_clk_n (mcb3_dram_ck_n),
|
525 |
|
|
.mcbx_dram_dq (mcb3_dram_dq),
|
526 |
|
|
.mcbx_dram_dqs (mcb3_dram_dqs),
|
527 |
|
|
.mcbx_dram_udqs (mcb3_dram_udqs),
|
528 |
|
|
.mcbx_dram_udm (mcb3_dram_udm),
|
529 |
|
|
.mcbx_dram_ldm (mcb3_dram_dm),
|
530 |
|
|
.mcbx_dram_dqs_n ( ),
|
531 |
|
|
.mcbx_dram_udqs_n ( ),
|
532 |
|
|
.mcbx_dram_odt ( ),
|
533 |
|
|
.mcbx_dram_ddr3_rst ( ),
|
534 |
|
|
.mcbx_rzq (mcb3_rzq),
|
535 |
|
|
.mcbx_zio (mcb3_zio),
|
536 |
|
|
.calib_done (c3_calib_done),
|
537 |
|
|
.async_rst (c3_async_rst),
|
538 |
|
|
.sysclk_2x (c3_sysclk_2x),
|
539 |
|
|
.sysclk_2x_180 (c3_sysclk_2x_180),
|
540 |
|
|
.pll_ce_0 (c3_pll_ce_0),
|
541 |
|
|
.pll_ce_90 (c3_pll_ce_90),
|
542 |
|
|
.pll_lock (c3_pll_lock),
|
543 |
|
|
.mcb_drp_clk (c3_mcb_drp_clk),
|
544 |
|
|
|
545 |
|
|
// The following port map shows all the six logical user ports. However, all
|
546 |
|
|
// of them may not be active in this design. A port should be enabled to
|
547 |
|
|
// validate its port map. If it is not,the complete port is going to float
|
548 |
|
|
// by getting disconnected from the lower level MCB modules. The port enable
|
549 |
|
|
// information of a controller can be obtained from the corresponding local
|
550 |
|
|
// parameter CX_PORT_ENABLE. In such a case, we can simply ignore its port map.
|
551 |
|
|
// The following comments will explain when a port is going to be active.
|
552 |
|
|
// Config-1: Two 32-bit bi-directional and four 32-bit unidirectional ports
|
553 |
|
|
// Config-2: Four 32-bit bi-directional ports
|
554 |
|
|
// Config-3: One 64-bit bi-directional and two 32-bit bi-directional ports
|
555 |
|
|
// Config-4: Two 64-bit bi-directional ports
|
556 |
|
|
// Config-5: One 128-bit bi-directional port
|
557 |
|
|
|
558 |
|
|
// User Port-0 command interface will be active only when the port is enabled in
|
559 |
|
|
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
|
560 |
|
|
.p0_cmd_clk (c3_p0_cmd_clk),
|
561 |
|
|
.p0_cmd_en (c3_p0_cmd_en),
|
562 |
|
|
.p0_cmd_instr (c3_p0_cmd_instr),
|
563 |
|
|
.p0_cmd_bl (c3_p0_cmd_bl),
|
564 |
|
|
.p0_cmd_byte_addr (c3_p0_cmd_byte_addr),
|
565 |
|
|
.p0_cmd_full (c3_p0_cmd_full),
|
566 |
|
|
.p0_cmd_empty (c3_p0_cmd_empty),
|
567 |
|
|
// User Port-0 data write interface will be active only when the port is enabled in
|
568 |
|
|
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
|
569 |
|
|
.p0_wr_clk (c3_p0_wr_clk),
|
570 |
|
|
.p0_wr_en (c3_p0_wr_en),
|
571 |
|
|
.p0_wr_mask (c3_p0_wr_mask),
|
572 |
|
|
.p0_wr_data (c3_p0_wr_data),
|
573 |
|
|
.p0_wr_full (c3_p0_wr_full),
|
574 |
|
|
.p0_wr_count (c3_p0_wr_count),
|
575 |
|
|
.p0_wr_empty (c3_p0_wr_empty),
|
576 |
|
|
.p0_wr_underrun (c3_p0_wr_underrun),
|
577 |
|
|
.p0_wr_error (c3_p0_wr_error),
|
578 |
|
|
// User Port-0 data read interface will be active only when the port is enabled in
|
579 |
|
|
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
|
580 |
|
|
.p0_rd_clk (c3_p0_rd_clk),
|
581 |
|
|
.p0_rd_en (c3_p0_rd_en),
|
582 |
|
|
.p0_rd_data (c3_p0_rd_data),
|
583 |
|
|
.p0_rd_empty (c3_p0_rd_empty),
|
584 |
|
|
.p0_rd_count (c3_p0_rd_count),
|
585 |
|
|
.p0_rd_full (c3_p0_rd_full),
|
586 |
|
|
.p0_rd_overflow (c3_p0_rd_overflow),
|
587 |
|
|
.p0_rd_error (c3_p0_rd_error),
|
588 |
|
|
|
589 |
|
|
// User Port-1 command interface will be active only when the port is enabled in
|
590 |
|
|
// the port configurations Config-1, Config-2, Config-3 and Config-4
|
591 |
|
|
.p1_cmd_clk (c3_p1_cmd_clk),
|
592 |
|
|
.p1_cmd_en (c3_p1_cmd_en),
|
593 |
|
|
.p1_cmd_instr (c3_p1_cmd_instr),
|
594 |
|
|
.p1_cmd_bl (c3_p1_cmd_bl),
|
595 |
|
|
.p1_cmd_byte_addr (c3_p1_cmd_byte_addr),
|
596 |
|
|
.p1_cmd_full (c3_p1_cmd_full),
|
597 |
|
|
.p1_cmd_empty (c3_p1_cmd_empty),
|
598 |
|
|
// User Port-1 data write interface will be active only when the port is enabled in
|
599 |
|
|
// the port configurations Config-1, Config-2, Config-3 and Config-4
|
600 |
|
|
.p1_wr_clk (c3_p1_wr_clk),
|
601 |
|
|
.p1_wr_en (c3_p1_wr_en),
|
602 |
|
|
.p1_wr_mask (c3_p1_wr_mask),
|
603 |
|
|
.p1_wr_data (c3_p1_wr_data),
|
604 |
|
|
.p1_wr_full (c3_p1_wr_full),
|
605 |
|
|
.p1_wr_count (c3_p1_wr_count),
|
606 |
|
|
.p1_wr_empty (c3_p1_wr_empty),
|
607 |
|
|
.p1_wr_underrun (c3_p1_wr_underrun),
|
608 |
|
|
.p1_wr_error (c3_p1_wr_error),
|
609 |
|
|
// User Port-1 data read interface will be active only when the port is enabled in
|
610 |
|
|
// the port configurations Config-1, Config-2, Config-3 and Config-4
|
611 |
|
|
.p1_rd_clk (c3_p1_rd_clk),
|
612 |
|
|
.p1_rd_en (c3_p1_rd_en),
|
613 |
|
|
.p1_rd_data (c3_p1_rd_data),
|
614 |
|
|
.p1_rd_empty (c3_p1_rd_empty),
|
615 |
|
|
.p1_rd_count (c3_p1_rd_count),
|
616 |
|
|
.p1_rd_full (c3_p1_rd_full),
|
617 |
|
|
.p1_rd_overflow (c3_p1_rd_overflow),
|
618 |
|
|
.p1_rd_error (c3_p1_rd_error),
|
619 |
|
|
|
620 |
|
|
// User Port-2 command interface will be active only when the port is enabled in
|
621 |
|
|
// the port configurations Config-1, Config-2 and Config-3
|
622 |
|
|
.p2_cmd_clk (c3_p2_cmd_clk),
|
623 |
|
|
.p2_cmd_en (c3_p2_cmd_en),
|
624 |
|
|
.p2_cmd_instr (c3_p2_cmd_instr),
|
625 |
|
|
.p2_cmd_bl (c3_p2_cmd_bl),
|
626 |
|
|
.p2_cmd_byte_addr (c3_p2_cmd_byte_addr),
|
627 |
|
|
.p2_cmd_full (c3_p2_cmd_full),
|
628 |
|
|
.p2_cmd_empty (c3_p2_cmd_empty),
|
629 |
|
|
// User Port-2 data write interface will be active only when the port is enabled in
|
630 |
|
|
// the port configurations Config-1 write direction, Config-2 and Config-3
|
631 |
|
|
.p2_wr_clk (c3_p2_wr_clk),
|
632 |
|
|
.p2_wr_en (c3_p2_wr_en),
|
633 |
|
|
.p2_wr_mask (c3_p2_wr_mask),
|
634 |
|
|
.p2_wr_data (c3_p2_wr_data),
|
635 |
|
|
.p2_wr_full (c3_p2_wr_full),
|
636 |
|
|
.p2_wr_count (c3_p2_wr_count),
|
637 |
|
|
.p2_wr_empty (c3_p2_wr_empty),
|
638 |
|
|
.p2_wr_underrun (c3_p2_wr_underrun),
|
639 |
|
|
.p2_wr_error (c3_p2_wr_error),
|
640 |
|
|
// User Port-2 data read interface will be active only when the port is enabled in
|
641 |
|
|
// the port configurations Config-1 read direction, Config-2 and Config-3
|
642 |
|
|
.p2_rd_clk (c3_p2_rd_clk),
|
643 |
|
|
.p2_rd_en (c3_p2_rd_en),
|
644 |
|
|
.p2_rd_data (c3_p2_rd_data),
|
645 |
|
|
.p2_rd_empty (c3_p2_rd_empty),
|
646 |
|
|
.p2_rd_count (c3_p2_rd_count),
|
647 |
|
|
.p2_rd_full (c3_p2_rd_full),
|
648 |
|
|
.p2_rd_overflow (c3_p2_rd_overflow),
|
649 |
|
|
.p2_rd_error (c3_p2_rd_error),
|
650 |
|
|
|
651 |
|
|
// User Port-3 command interface will be active only when the port is enabled in
|
652 |
|
|
// the port configurations Config-1 and Config-2
|
653 |
|
|
.p3_cmd_clk (c3_p3_cmd_clk),
|
654 |
|
|
.p3_cmd_en (c3_p3_cmd_en),
|
655 |
|
|
.p3_cmd_instr (c3_p3_cmd_instr),
|
656 |
|
|
.p3_cmd_bl (c3_p3_cmd_bl),
|
657 |
|
|
.p3_cmd_byte_addr (c3_p3_cmd_byte_addr),
|
658 |
|
|
.p3_cmd_full (c3_p3_cmd_full),
|
659 |
|
|
.p3_cmd_empty (c3_p3_cmd_empty),
|
660 |
|
|
// User Port-3 data write interface will be active only when the port is enabled in
|
661 |
|
|
// the port configurations Config-1 write direction and Config-2
|
662 |
|
|
.p3_wr_clk (c3_p3_wr_clk),
|
663 |
|
|
.p3_wr_en (c3_p3_wr_en),
|
664 |
|
|
.p3_wr_mask (c3_p3_wr_mask),
|
665 |
|
|
.p3_wr_data (c3_p3_wr_data),
|
666 |
|
|
.p3_wr_full (c3_p3_wr_full),
|
667 |
|
|
.p3_wr_count (c3_p3_wr_count),
|
668 |
|
|
.p3_wr_empty (c3_p3_wr_empty),
|
669 |
|
|
.p3_wr_underrun (c3_p3_wr_underrun),
|
670 |
|
|
.p3_wr_error (c3_p3_wr_error),
|
671 |
|
|
// User Port-3 data read interface will be active only when the port is enabled in
|
672 |
|
|
// the port configurations Config-1 read direction and Config-2
|
673 |
|
|
.p3_rd_clk (c3_p3_rd_clk),
|
674 |
|
|
.p3_rd_en (c3_p3_rd_en),
|
675 |
|
|
.p3_rd_data (c3_p3_rd_data),
|
676 |
|
|
.p3_rd_empty (c3_p3_rd_empty),
|
677 |
|
|
.p3_rd_count (c3_p3_rd_count),
|
678 |
|
|
.p3_rd_full (c3_p3_rd_full),
|
679 |
|
|
.p3_rd_overflow (c3_p3_rd_overflow),
|
680 |
|
|
.p3_rd_error (c3_p3_rd_error),
|
681 |
|
|
|
682 |
|
|
// User Port-4 command interface will be active only when the port is enabled in
|
683 |
|
|
// the port configuration Config-1
|
684 |
|
|
.p4_cmd_clk (c3_p4_cmd_clk),
|
685 |
|
|
.p4_cmd_en (c3_p4_cmd_en),
|
686 |
|
|
.p4_cmd_instr (c3_p4_cmd_instr),
|
687 |
|
|
.p4_cmd_bl (c3_p4_cmd_bl),
|
688 |
|
|
.p4_cmd_byte_addr (c3_p4_cmd_byte_addr),
|
689 |
|
|
.p4_cmd_full (c3_p4_cmd_full),
|
690 |
|
|
.p4_cmd_empty (c3_p4_cmd_empty),
|
691 |
|
|
// User Port-4 data write interface will be active only when the port is enabled in
|
692 |
|
|
// the port configuration Config-1 write direction
|
693 |
|
|
.p4_wr_clk (c3_p4_wr_clk),
|
694 |
|
|
.p4_wr_en (c3_p4_wr_en),
|
695 |
|
|
.p4_wr_mask (c3_p4_wr_mask),
|
696 |
|
|
.p4_wr_data (c3_p4_wr_data),
|
697 |
|
|
.p4_wr_full (c3_p4_wr_full),
|
698 |
|
|
.p4_wr_count (c3_p4_wr_count),
|
699 |
|
|
.p4_wr_empty (c3_p4_wr_empty),
|
700 |
|
|
.p4_wr_underrun (c3_p4_wr_underrun),
|
701 |
|
|
.p4_wr_error (c3_p4_wr_error),
|
702 |
|
|
// User Port-4 data read interface will be active only when the port is enabled in
|
703 |
|
|
// the port configuration Config-1 read direction
|
704 |
|
|
.p4_rd_clk (c3_p4_rd_clk),
|
705 |
|
|
.p4_rd_en (c3_p4_rd_en),
|
706 |
|
|
.p4_rd_data (c3_p4_rd_data),
|
707 |
|
|
.p4_rd_empty (c3_p4_rd_empty),
|
708 |
|
|
.p4_rd_count (c3_p4_rd_count),
|
709 |
|
|
.p4_rd_full (c3_p4_rd_full),
|
710 |
|
|
.p4_rd_overflow (c3_p4_rd_overflow),
|
711 |
|
|
.p4_rd_error (c3_p4_rd_error),
|
712 |
|
|
|
713 |
|
|
// User Port-5 command interface will be active only when the port is enabled in
|
714 |
|
|
// the port configuration Config-1
|
715 |
|
|
.p5_cmd_clk (c3_p5_cmd_clk),
|
716 |
|
|
.p5_cmd_en (c3_p5_cmd_en),
|
717 |
|
|
.p5_cmd_instr (c3_p5_cmd_instr),
|
718 |
|
|
.p5_cmd_bl (c3_p5_cmd_bl),
|
719 |
|
|
.p5_cmd_byte_addr (c3_p5_cmd_byte_addr),
|
720 |
|
|
.p5_cmd_full (c3_p5_cmd_full),
|
721 |
|
|
.p5_cmd_empty (c3_p5_cmd_empty),
|
722 |
|
|
// User Port-5 data write interface will be active only when the port is enabled in
|
723 |
|
|
// the port configuration Config-1 write direction
|
724 |
|
|
.p5_wr_clk (c3_p5_wr_clk),
|
725 |
|
|
.p5_wr_en (c3_p5_wr_en),
|
726 |
|
|
.p5_wr_mask (c3_p5_wr_mask),
|
727 |
|
|
.p5_wr_data (c3_p5_wr_data),
|
728 |
|
|
.p5_wr_full (c3_p5_wr_full),
|
729 |
|
|
.p5_wr_count (c3_p5_wr_count),
|
730 |
|
|
.p5_wr_empty (c3_p5_wr_empty),
|
731 |
|
|
.p5_wr_underrun (c3_p5_wr_underrun),
|
732 |
|
|
.p5_wr_error (c3_p5_wr_error),
|
733 |
|
|
// User Port-5 data read interface will be active only when the port is enabled in
|
734 |
|
|
// the port configuration Config-1 read direction
|
735 |
|
|
.p5_rd_clk (c3_p5_rd_clk),
|
736 |
|
|
.p5_rd_en (c3_p5_rd_en),
|
737 |
|
|
.p5_rd_data (c3_p5_rd_data),
|
738 |
|
|
.p5_rd_empty (c3_p5_rd_empty),
|
739 |
|
|
.p5_rd_count (c3_p5_rd_count),
|
740 |
|
|
.p5_rd_full (c3_p5_rd_full),
|
741 |
|
|
.p5_rd_overflow (c3_p5_rd_overflow),
|
742 |
|
|
.p5_rd_error (c3_p5_rd_error),
|
743 |
|
|
|
744 |
|
|
.selfrefresh_enter (1'b0),
|
745 |
|
|
.selfrefresh_mode (c3_selfrefresh_mode)
|
746 |
|
|
);
|
747 |
|
|
|
748 |
|
|
|
749 |
|
|
|
750 |
|
|
|
751 |
|
|
|
752 |
|
|
|
753 |
|
|
endmodule
|
754 |
|
|
|
755 |
|
|
|