URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [sim/] [mcb_flow_control.v] - Blame information for rev 2

Details | Compare with Previous | View Log


//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: %version
//  \   \         Application: MIG
//  /   /         Filename: mcb_flow_control.v
// /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:33 $
// \   \  /  \    Date Created: 
//  \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR 
//Purpose: This module is the main flow control between cmd_gen.v, 
//         write_data_path and read_data_path modules.
//Design Name: DDR/DDR2/DDR3/LPDDR 
//Reference:
//Revision History:
//*****************************************************************************
 
`timescale 1ps/1ps
 
module mcb_flow_control #
  (
    parameter TCQ           = 100,
    parameter FAMILY = "SPARTAN6"
  )
  (
   input     clk_i,
   input [9:0]    rst_i,
   // interface to cmd_gen, pipeline inserter
   output  reg     cmd_rdy_o,
   input        cmd_valid_i,
   input [2:0]  cmd_i,
   input [31:0] addr_i,
   input [5:0]  bl_i,
 
 
   // interface to mcb_cmd port
   input                  mcb_cmd_full,
   output reg [2:0]           cmd_o,
   output reg [31:0]          addr_o,
   output reg [5:0]           bl_o,
   output                 cmd_en_o,   // interface to write data path module
   input                  last_word_wr_i,
   input                  wdp_rdy_i,
   output                 wdp_valid_o,
   output                 wdp_validB_o,
   output                 wdp_validC_o,
 
   output  [31:0]          wr_addr_o,
   output  [5:0]           wr_bl_o,
   // interface to read data path module
   input                   last_word_rd_i,
   input                   rdp_rdy_i,
   output                  rdp_valid_o,
   output  [31:0]           rd_addr_o,
   output [5:0]            rd_bl_o
   );
 
   //FSM State Defination
localparam READY    = 5'b00001,
          READ     = 5'b00010,
          WRITE    = 5'b00100,
          CMD_WAIT = 5'b01000,
          REFRESH_ST = 5'b10000;
 
localparam RD     =         3'b001;
localparam RDP    =         3'b011;
localparam WR     =         3'b000;
localparam WRP    =         3'b010;
localparam REFRESH =        3'b100;
localparam NOP     =        3'b101;  // this defination is local to this traffic gen and is not defined
 
 
reg cmd_fifo_rdy;
wire cmd_rd;
wire cmd_wr;         // need equation
wire cmd_others;
reg  push_cmd;
reg  xfer_cmd;
reg  rd_vld  ;
reg  wr_vld;
reg  cmd_rdy;
reg [2:0]   cmd_reg;
reg [31:0]  addr_reg;
reg [5:0]   bl_reg;
 
reg       rdp_valid;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg   wdp_valid,wdp_validB,wdp_validC;
 
reg [4:0] current_state;
reg [4:0] next_state;
reg [3:0] tstpointA;
reg push_cmd_r;
reg wait_done;
reg cmd_en_r1 ;
reg wr_in_progress;
reg tst_cmd_rdy_o;
 
 
 
 
//  mcb_command bus outputs
assign cmd_en_o = cmd_en_r1;
 
always @ (posedge clk_i) begin
 
    cmd_rdy_o <= #TCQ  cmd_rdy;
    tst_cmd_rdy_o <= #TCQ  cmd_rdy;
 
end
 
always @ (posedge clk_i)
begin
if (rst_i[8])
    cmd_en_r1 <= #TCQ  1'b0;
else if ( xfer_cmd)
    cmd_en_r1 <= #TCQ  1'b1;
 else if (!mcb_cmd_full)
    cmd_en_r1 <= #TCQ  1'b0;
 
 end
 
always @ (posedge clk_i)
begin
if (rst_i[9])
    cmd_fifo_rdy <= #TCQ  1'b1;
else if (xfer_cmd)
    cmd_fifo_rdy <= #TCQ  1'b0;
else if (!mcb_cmd_full)
    cmd_fifo_rdy <= #TCQ  1'b1;
end
 
always @ (posedge clk_i)
begin
if (rst_i[9]) begin
    addr_o <= #TCQ  'b0;
    cmd_o  <= #TCQ  'b0;
    bl_o   <= #TCQ  'b0;
end
else if (xfer_cmd ) begin
    addr_o <= #TCQ  addr_reg;
    if (FAMILY == "SPARTAN6")
        cmd_o <= #TCQ  cmd_reg;
    else
        cmd_o  <= #TCQ  {2'b00,cmd_reg[0]};
    bl_o   <= #TCQ  bl_reg;
end
 
end
 
// go directly to wr_datapath and rd_datapath modules 
       assign  wr_addr_o = addr_i;
       assign  rd_addr_o = addr_i;
assign rd_bl_o   = bl_i ;
assign wr_bl_o   = bl_i ;
 
assign wdp_valid_o = wdp_valid;
assign wdp_validB_o = wdp_validB;
assign wdp_validC_o = wdp_validC;
 
assign rdp_valid_o = rdp_valid;
 
 
// internal control siganls
 
always @ (posedge clk_i)
begin
if (rst_i[8])
   wait_done <= #TCQ  1'b1;
else if (push_cmd_r)
   wait_done <=  #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i && FAMILY == "SPARTAN6")
   wait_done <=  #TCQ 1'b0;
 
 
end
 
//  
 
 
always @ (posedge clk_i)
     begin
     push_cmd_r  <= #TCQ push_cmd;
    // push_cmd_r2 <= #TCQ push_cmd_r;
     end
always @ (posedge clk_i)
 if (push_cmd)
   begin
        cmd_reg <=    #TCQ cmd_i;
        addr_reg <= #TCQ addr_i;
        bl_reg   <= #TCQ bl_i - 1;
 
end
 
 
 
//--Command Decodes--
assign  cmd_wr     = ((cmd_i == WR  | cmd_i == WRP) & cmd_valid_i )  ? 1'b1 : 1'b0;
assign  cmd_rd     = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0;
assign  cmd_others = ((cmd_i[2] == 1'b1)& cmd_valid_i && (FAMILY == "SPARTAN6")) ? 1'b1 : 1'b0;
 
 
reg cmd_wr_pending_r1;
reg cmd_rd_pending_r1;
 
always @ (posedge clk_i)
begin
if (rst_i[0])
    cmd_wr_pending_r1 <= #TCQ 1'b0;
 
//else if (current_state == WRITE && last_word_wr_i && !cmd_fifo_rdy)
//else if ( last_word_wr_i && !cmd_fifo_rdy)
else if ( last_word_wr_i )
 
 
    cmd_wr_pending_r1 <= #TCQ 1'b1;
else if (push_cmd)//xfer_cmd)
    cmd_wr_pending_r1 <= #TCQ 1'b0;
end
 
 
// corner case if fixed read command with fixed bl 64
 
always @ (posedge clk_i)
begin
if (cmd_rd & push_cmd)
    cmd_rd_pending_r1 <= #TCQ 1'b1;
else if (xfer_cmd)
    cmd_rd_pending_r1 <= #TCQ 1'b0;
 
end
 
 always @ (posedge clk_i)
 begin
if (rst_i[0])
   wr_in_progress <= #TCQ  1'b0;
else if (last_word_wr_i)
   wr_in_progress <= #TCQ  1'b0;
else if (current_state == WRITE)
   wr_in_progress <= #TCQ  1'b1;
 
 
end
 always @ (posedge clk_i)
 begin
    if (rst_i[0])
        current_state <= #TCQ  4'b0001;
    else
        current_state <= #TCQ next_state;
 end
 
// mcb_flow_control statemachine
always @ (*)
begin
               push_cmd  = 1'b0;
               xfer_cmd = 1'b0;
 
               wdp_valid = 1'b0;
               wdp_validB = 1'b0;
               wdp_validC = 1'b0;
 
               rdp_valid = 1'b0;
               cmd_rdy = 1'b0;
               next_state = current_state;
case(current_state)
   READY:
        begin
         if(rdp_rdy_i & cmd_rd & cmd_fifo_rdy)   //rdp_rdy_i comes from read_data path
 
            begin
              next_state = READ;
              push_cmd = 1'b1;
              xfer_cmd = 1'b0;
              rdp_valid = 1'b1;
 
            end
         else if (wdp_rdy_i & cmd_wr & cmd_fifo_rdy)
             begin
              next_state = WRITE;
               push_cmd = 1'b1;
               wdp_valid     = 1'b1;
               wdp_validB = 1'b1;
               wdp_validC = 1'b1;
 
             end
         else if ( cmd_others & cmd_fifo_rdy)
             begin
              next_state = REFRESH_ST;
               push_cmd = 1'b1;
               xfer_cmd = 1'b0;
 
             end
 
         else
              begin
              next_state = READY;
              push_cmd = 1'b0;
              end
 
 
         if (cmd_fifo_rdy)
             cmd_rdy = 1'b1;
         else
             cmd_rdy = 1'b0;
 
 
         end
 
   REFRESH_ST : begin
 
         if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy  )
            begin
               next_state = READ;
               push_cmd = 1'b1;
               rdp_valid = 1'b1;
               wdp_valid = 1'b0;
               xfer_cmd = 1'b1;
              // tstpointA    = 4'b0101;
 
            end
          else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )
             begin
               next_state = WRITE;
               push_cmd = 1'b1;
               xfer_cmd = 1'b1;
 
               wdp_valid     = 1'b1;
               wdp_validB    = 1'b1;
               wdp_validC    = 1'b1;
 
             //   tstpointA    = 4'b0110;
 
             end
 
          else if (cmd_fifo_rdy && cmd_others)
             begin
               push_cmd = 1'b1;
               xfer_cmd = 1'b1;
             end
          else if (!cmd_fifo_rdy)
 
             begin
               next_state = CMD_WAIT;
               tstpointA    = 4'b1001;
 
             end
          else
               next_state = READ;
 
 
 
          if (cmd_fifo_rdy && ((rdp_rdy_i && cmd_rd) || (wdp_rdy_i && cmd_wr) || (cmd_others)))
              cmd_rdy = 1'b1;
         else
              cmd_rdy = 1'b0;
 
 
 
          end
   READ:  begin
 
         if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy  )
            begin
               next_state = READ;
               push_cmd = 1'b1;
               rdp_valid = 1'b1;
               wdp_valid = 1'b0;
               xfer_cmd = 1'b1;
               tstpointA    = 4'b0101;
 
            end
          else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )
             begin
               next_state = WRITE;
               push_cmd = 1'b1;
               xfer_cmd = 1'b1;
 
               wdp_valid     = 1'b1;
               wdp_validB    = 1'b1;
               wdp_validC    = 1'b1;
 
                tstpointA    = 4'b0110;
 
             end
 
         else if (!rdp_rdy_i )
            begin
               next_state = READ;
               push_cmd  = 1'b0;
                 xfer_cmd  = 1'b0;
 
               tstpointA    = 4'b0111;
 
               wdp_valid = 1'b0;
               wdp_validB = 1'b0;
               wdp_validC    = 1'b0;
               rdp_valid = 1'b0;
            end
          else if (last_word_rd_i && cmd_others && cmd_fifo_rdy )
 
             begin
               next_state = REFRESH_ST;
               push_cmd = 1'b1;
               xfer_cmd = 1'b1;
               wdp_valid = 1'b0;
               wdp_validB = 1'b0;
               wdp_validC    = 1'b0;
               rdp_valid = 1'b0;
               tstpointA    = 4'b1000;
 
             end
          else if (!cmd_fifo_rdy || !wdp_rdy_i)
 
             begin
               next_state = CMD_WAIT;
               tstpointA    = 4'b1001;
 
             end
          else
               next_state = READ;
 
 
 
          if ((rdp_rdy_i && cmd_rd || cmd_wr && wdp_rdy_i || cmd_others) && cmd_fifo_rdy)
             cmd_rdy = wait_done;//1'b1;
         else
              cmd_rdy = 1'b0;
 
 
        end
   WRITE: begin  // for write, always wait until the last_word_wr 
         if (cmd_fifo_rdy &&  cmd_rd && rdp_rdy_i && last_word_wr_i)
               begin
               next_state = READ;
               push_cmd = 1'b1;
               xfer_cmd = 1'b1;
               rdp_valid     = 1'b1;
               tstpointA    = 4'b0000;
               end
          else if (!wdp_rdy_i || (wdp_rdy_i && cmd_wr && cmd_fifo_rdy && last_word_wr_i) )
               begin
               next_state = WRITE;
               tstpointA    = 4'b0001;
 
               if (cmd_wr && last_word_wr_i) begin
                  wdp_valid     = 1'b1;
                  wdp_validB = 1'b1;
                  wdp_validC    = 1'b1;
 
               end
               else begin
                  wdp_valid     = 1'b0;
                  wdp_validB = 1'b0;
               wdp_validC    = 1'b0;
 
               end
 
               if (last_word_wr_i ) begin
                  push_cmd = 1'b1;
                  xfer_cmd = 1'b1;
               end
               else begin
                  push_cmd = 1'b0;
                  xfer_cmd = 1'b0;
               end
 
               end
          else if (last_word_wr_i && cmd_others && cmd_fifo_rdy)
             begin
               next_state = REFRESH_ST;
               push_cmd = 1'b1;
               xfer_cmd = 1'b1;
               tstpointA    = 4'b0010;
 
               wdp_valid = 1'b0;
               wdp_validB = 1'b0;
               wdp_validC    = 1'b0;
 
               rdp_valid = 1'b0;
 
             end
 
          else if (!cmd_fifo_rdy && last_word_wr_i || !rdp_rdy_i || (!cmd_valid_i && wait_done) )
 
               begin
               next_state = CMD_WAIT;
               push_cmd = 1'b0;
               xfer_cmd = 1'b0;
               tstpointA    = 4'b0011;
 
               end
 
          else begin
                  next_state = WRITE;
               tstpointA    = 4'b0100;
 
               end
 
         // need to include rdp_rdy_i to prevent sending read command if
         // read_data_port fifo is full in MCB
   if (last_word_wr_i && (cmd_others || rdp_rdy_i && cmd_rd || cmd_wr && wdp_rdy_i) && cmd_fifo_rdy)
             cmd_rdy = wait_done;//1'b1;
         else
             cmd_rdy = 1'b0;
 
 
         end
 
 
 
 
 
   CMD_WAIT: if (!cmd_fifo_rdy || wr_in_progress)
               begin
               next_state = CMD_WAIT;
               cmd_rdy = 1'b0;
               tstpointA    = 4'b1010;
 
               end
             else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd)
               begin
               next_state = READ;
               push_cmd = 1'b1;
               xfer_cmd = 1'b1;
               cmd_rdy = 1'b1;
               rdp_valid     = 1'b1;
 
               tstpointA    = 4'b1011;
               end
             else if (cmd_fifo_rdy  && cmd_wr && (wait_done || cmd_wr_pending_r1))
 
               begin
               next_state = WRITE;
               push_cmd = 1'b1;
               xfer_cmd = 1'b1;
               wdp_valid     = 1'b1;
               wdp_validB = 1'b1;
               wdp_validC    = 1'b1;
 
               cmd_rdy = 1'b1;
               tstpointA    = 4'b1100;
 
               end
             else if (cmd_fifo_rdy &&  cmd_others)
               begin
               next_state = REFRESH_ST;
               push_cmd = 1'b1;  /////////////////
               xfer_cmd = 1'b1;
               tstpointA    = 4'b1101;
               cmd_rdy = 1'b1;
 
               end
             else
               begin
               next_state = CMD_WAIT;
               tstpointA    = 4'b1110;
 
               if ((wdp_rdy_i && rdp_rdy_i))
                  cmd_rdy = 1'b1;
               else
                  cmd_rdy = 1'b0;
 
 
               end
 
 
   default:
          begin
           push_cmd = 1'b0;
           xfer_cmd = 1'b0;
 
           wdp_valid = 1'b0;
           wdp_validB = 1'b0;
           wdp_validC    = 1'b0;
           next_state = READY;
         //  cmd_rdy = 1'b0;
 
 
 
         end
 
 endcase
 end
 
endmodule

Browse

Tools

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [sim/] [mcb_flow_control.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`//*****************************************************************************`
2			`// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.`
3			`//`
4			`// This file contains confidential and proprietary information`
5			`// of Xilinx, Inc. and is protected under U.S. and`
6			`// international copyright and other intellectual property`
7			`// laws.`
8			`//`
9			`// DISCLAIMER`
10			`// This disclaimer is not a license and does not grant any`
11			`// rights to the materials distributed herewith. Except as`
12			`// otherwise provided in a valid license issued to you by`
13			`// Xilinx, and to the maximum extent permitted by applicable`
14			`// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND`
15			`// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES`
16			`// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING`
17			`// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-`
18			`// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and`
19			`// (2) Xilinx shall not be liable (whether in contract or tort,`
20			`// including negligence, or under any other theory of`
21			`// liability) for any loss or damage of any kind or nature`
22			`// related to, arising under or in connection with these`
23			`// materials, including for any direct, or any indirect,`
24			`// special, incidental, or consequential loss or damage`
25			`// (including loss of data, profits, goodwill, or any type of`
26			`// loss or damage suffered as a result of any action brought`
27			`// by a third party) even if such damage or loss was`
28			`// reasonably foreseeable or Xilinx had been advised of the`
29			`// possibility of the same.`
30			`//`
31			`// CRITICAL APPLICATIONS`
32			`// Xilinx products are not designed or intended to be fail-`
33			`// safe, or for use in any application requiring fail-safe`
34			`// performance, such as life-support or safety devices or`
35			`// systems, Class III medical devices, nuclear facilities,`
36			`// applications related to the deployment of airbags, or any`
37			`// other applications that could lead to death, personal`
38			`// injury, or severe property or environmental damage`
39			`// (individually and collectively, "Critical`
40			`// Applications"). Customer assumes the sole risk and`
41			`// liability of any use of Xilinx products in Critical`
42			`// Applications, subject only to applicable laws and`
43			`// regulations governing limitations on product liability.`
44			`//`
45			`// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS`
46			`// PART OF THIS FILE AT ALL TIMES.`
47			`//`
48			`//*****************************************************************************`
49			`// ____ ____`
50			`// / /\/ /`
51			`// /___/ \ / Vendor: Xilinx`
52			`// \ \ \/ Version: %version`
53			`// \ \ Application: MIG`
54			`// / / Filename: mcb_flow_control.v`
55			`// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:33 $`
56			`// \ \ / \ Date Created:`
57			`// \___\/\___\`
58			`//`
59			`//Device: Spartan6`
60			`//Design Name: DDR/DDR2/DDR3/LPDDR`
61			`//Purpose: This module is the main flow control between cmd_gen.v,`
62			`// write_data_path and read_data_path modules.`
63			`//Design Name: DDR/DDR2/DDR3/LPDDR`
64			`//Reference:`
65			`//Revision History:`
66			`//*****************************************************************************`
67
68			`timescale 1ps/1ps
69
70			`module mcb_flow_control #`
71			`(`
72			`parameter TCQ = 100,`
73			`parameter FAMILY = "SPARTAN6"`
74			`)`
75			`(`
76			`input clk_i,`
77			`input [9:0] rst_i,`
78			`// interface to cmd_gen, pipeline inserter`
79			`output reg cmd_rdy_o,`
80			`input cmd_valid_i,`
81			`input [2:0] cmd_i,`
82			`input [31:0] addr_i,`
83			`input [5:0] bl_i,`
84
85
86			`// interface to mcb_cmd port`
87			`input mcb_cmd_full,`
88			`output reg [2:0] cmd_o,`
89			`output reg [31:0] addr_o,`
90			`output reg [5:0] bl_o,`
91			`output cmd_en_o, // interface to write data path module`
92			`input last_word_wr_i,`
93			`input wdp_rdy_i,`
94			`output wdp_valid_o,`
95			`output wdp_validB_o,`
96			`output wdp_validC_o,`
97
98			`output [31:0] wr_addr_o,`
99			`output [5:0] wr_bl_o,`
100			`// interface to read data path module`
101			`input last_word_rd_i,`
102			`input rdp_rdy_i,`
103			`output rdp_valid_o,`
104			`output [31:0] rd_addr_o,`
105			`output [5:0] rd_bl_o`
106			`);`
107
108			`//FSM State Defination`
109			`localparam READY = 5'b00001,`
110			`READ = 5'b00010,`
111			`WRITE = 5'b00100,`
112			`CMD_WAIT = 5'b01000,`
113			`REFRESH_ST = 5'b10000;`
114
115			`localparam RD = 3'b001;`
116			`localparam RDP = 3'b011;`
117			`localparam WR = 3'b000;`
118			`localparam WRP = 3'b010;`
119			`localparam REFRESH = 3'b100;`
120			`localparam NOP = 3'b101; // this defination is local to this traffic gen and is not defined`
121
122
123			`reg cmd_fifo_rdy;`
124			`wire cmd_rd;`
125			`wire cmd_wr; // need equation`
126			`wire cmd_others;`
127			`reg push_cmd;`
128			`reg xfer_cmd;`
129			`reg rd_vld ;`
130			`reg wr_vld;`
131			`reg cmd_rdy;`
132			`reg [2:0] cmd_reg;`
133			`reg [31:0] addr_reg;`
134			`reg [5:0] bl_reg;`
135
136			`reg rdp_valid;`
137			`(EQUIVALENT_REGISTER_REMOVAL="NO") reg wdp_valid,wdp_validB,wdp_validC;`
138
139			`reg [4:0] current_state;`
140			`reg [4:0] next_state;`
141			`reg [3:0] tstpointA;`
142			`reg push_cmd_r;`
143			`reg wait_done;`
144			`reg cmd_en_r1 ;`
145			`reg wr_in_progress;`
146			`reg tst_cmd_rdy_o;`
147
148
149
150
151			`// mcb_command bus outputs`
152			`assign cmd_en_o = cmd_en_r1;`
153
154			`always @ (posedge clk_i) begin`
155
156			`cmd_rdy_o <= #TCQ cmd_rdy;`
157			`tst_cmd_rdy_o <= #TCQ cmd_rdy;`
158
159			`end`
160
161			`always @ (posedge clk_i)`
162			`begin`
163			`if (rst_i[8])`
164			`cmd_en_r1 <= #TCQ 1'b0;`
165			`else if ( xfer_cmd)`
166			`cmd_en_r1 <= #TCQ 1'b1;`
167			`else if (!mcb_cmd_full)`
168			`cmd_en_r1 <= #TCQ 1'b0;`
169
170			`end`
171
172			`always @ (posedge clk_i)`
173			`begin`
174			`if (rst_i[9])`
175			`cmd_fifo_rdy <= #TCQ 1'b1;`
176			`else if (xfer_cmd)`
177			`cmd_fifo_rdy <= #TCQ 1'b0;`
178			`else if (!mcb_cmd_full)`
179			`cmd_fifo_rdy <= #TCQ 1'b1;`
180			`end`
181
182			`always @ (posedge clk_i)`
183			`begin`
184			`if (rst_i[9]) begin`
185			`addr_o <= #TCQ 'b0;`
186			`cmd_o <= #TCQ 'b0;`
187			`bl_o <= #TCQ 'b0;`
188			`end`
189			`else if (xfer_cmd ) begin`
190			`addr_o <= #TCQ addr_reg;`
191			`if (FAMILY == "SPARTAN6")`
192			`cmd_o <= #TCQ cmd_reg;`
193			`else`
194			`cmd_o <= #TCQ {2'b00,cmd_reg[0]};`
195			`bl_o <= #TCQ bl_reg;`
196			`end`
197
198			`end`
199
200			`// go directly to wr_datapath and rd_datapath modules`
201			`assign wr_addr_o = addr_i;`
202			`assign rd_addr_o = addr_i;`
203			`assign rd_bl_o = bl_i ;`
204			`assign wr_bl_o = bl_i ;`
205
206			`assign wdp_valid_o = wdp_valid;`
207			`assign wdp_validB_o = wdp_validB;`
208			`assign wdp_validC_o = wdp_validC;`
209
210			`assign rdp_valid_o = rdp_valid;`
211
212
213			`// internal control siganls`
214
215			`always @ (posedge clk_i)`
216			`begin`
217			`if (rst_i[8])`
218			`wait_done <= #TCQ 1'b1;`
219			`else if (push_cmd_r)`
220			`wait_done <= #TCQ 1'b1;`
221			`else if (cmd_rdy_o && cmd_valid_i && FAMILY == "SPARTAN6")`
222			`wait_done <= #TCQ 1'b0;`
223
224
225			`end`
226
227			`//`
228
229
230			`always @ (posedge clk_i)`
231			`begin`
232			`push_cmd_r <= #TCQ push_cmd;`
233			`// push_cmd_r2 <= #TCQ push_cmd_r;`
234			`end`
235			`always @ (posedge clk_i)`
236			`if (push_cmd)`
237			`begin`
238			`cmd_reg <= #TCQ cmd_i;`
239			`addr_reg <= #TCQ addr_i;`
240			`bl_reg <= #TCQ bl_i - 1;`
241
242			`end`
243
244
245
246			`//--Command Decodes--`
247			`assign cmd_wr = ((cmd_i == WR \| cmd_i == WRP) & cmd_valid_i ) ? 1'b1 : 1'b0;`
248			`assign cmd_rd = ((cmd_i == RD \| cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0;`
249			`assign cmd_others = ((cmd_i[2] == 1'b1)& cmd_valid_i && (FAMILY == "SPARTAN6")) ? 1'b1 : 1'b0;`
250
251
252			`reg cmd_wr_pending_r1;`
253			`reg cmd_rd_pending_r1;`
254
255			`always @ (posedge clk_i)`
256			`begin`
257			`if (rst_i[0])`
258			`cmd_wr_pending_r1 <= #TCQ 1'b0;`
259
260			`//else if (current_state == WRITE && last_word_wr_i && !cmd_fifo_rdy)`
261			`//else if ( last_word_wr_i && !cmd_fifo_rdy)`
262			`else if ( last_word_wr_i )`
263
264
265			`cmd_wr_pending_r1 <= #TCQ 1'b1;`
266			`else if (push_cmd)//xfer_cmd)`
267			`cmd_wr_pending_r1 <= #TCQ 1'b0;`
268			`end`
269
270
271			`// corner case if fixed read command with fixed bl 64`
272
273			`always @ (posedge clk_i)`
274			`begin`
275			`if (cmd_rd & push_cmd)`
276			`cmd_rd_pending_r1 <= #TCQ 1'b1;`
277			`else if (xfer_cmd)`
278			`cmd_rd_pending_r1 <= #TCQ 1'b0;`
279
280			`end`
281
282			`always @ (posedge clk_i)`
283			`begin`
284			`if (rst_i[0])`
285			`wr_in_progress <= #TCQ 1'b0;`
286			`else if (last_word_wr_i)`
287			`wr_in_progress <= #TCQ 1'b0;`
288			`else if (current_state == WRITE)`
289			`wr_in_progress <= #TCQ 1'b1;`
290
291
292			`end`
293			`always @ (posedge clk_i)`
294			`begin`
295			`if (rst_i[0])`
296			`current_state <= #TCQ 4'b0001;`
297			`else`
298			`current_state <= #TCQ next_state;`
299			`end`
300
301			`// mcb_flow_control statemachine`
302			`always @ (*)`
303			`begin`
304			`push_cmd = 1'b0;`
305			`xfer_cmd = 1'b0;`
306
307			`wdp_valid = 1'b0;`
308			`wdp_validB = 1'b0;`
309			`wdp_validC = 1'b0;`
310
311			`rdp_valid = 1'b0;`
312			`cmd_rdy = 1'b0;`
313			`next_state = current_state;`
314			`case(current_state)`
315			`READY:`
316			`begin`
317			`if(rdp_rdy_i & cmd_rd & cmd_fifo_rdy) //rdp_rdy_i comes from read_data path`
318
319			`begin`
320			`next_state = READ;`
321			`push_cmd = 1'b1;`
322			`xfer_cmd = 1'b0;`
323			`rdp_valid = 1'b1;`
324
325			`end`
326			`else if (wdp_rdy_i & cmd_wr & cmd_fifo_rdy)`
327			`begin`
328			`next_state = WRITE;`
329			`push_cmd = 1'b1;`
330			`wdp_valid = 1'b1;`
331			`wdp_validB = 1'b1;`
332			`wdp_validC = 1'b1;`
333
334			`end`
335			`else if ( cmd_others & cmd_fifo_rdy)`
336			`begin`
337			`next_state = REFRESH_ST;`
338			`push_cmd = 1'b1;`
339			`xfer_cmd = 1'b0;`
340
341			`end`
342
343			`else`
344			`begin`
345			`next_state = READY;`
346			`push_cmd = 1'b0;`
347			`end`
348
349
350			`if (cmd_fifo_rdy)`
351			`cmd_rdy = 1'b1;`
352			`else`
353			`cmd_rdy = 1'b0;`
354
355
356			`end`
357
358			`REFRESH_ST : begin`
359
360			`if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy )`
361			`begin`
362			`next_state = READ;`
363			`push_cmd = 1'b1;`
364			`rdp_valid = 1'b1;`
365			`wdp_valid = 1'b0;`
366			`xfer_cmd = 1'b1;`
367			`// tstpointA = 4'b0101;`
368
369			`end`
370			`else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )`
371			`begin`
372			`next_state = WRITE;`
373			`push_cmd = 1'b1;`
374			`xfer_cmd = 1'b1;`
375
376			`wdp_valid = 1'b1;`
377			`wdp_validB = 1'b1;`
378			`wdp_validC = 1'b1;`
379
380			`// tstpointA = 4'b0110;`
381
382			`end`
383
384			`else if (cmd_fifo_rdy && cmd_others)`
385			`begin`
386			`push_cmd = 1'b1;`
387			`xfer_cmd = 1'b1;`
388			`end`
389			`else if (!cmd_fifo_rdy)`
390
391			`begin`
392			`next_state = CMD_WAIT;`
393			`tstpointA = 4'b1001;`
394
395			`end`
396			`else`
397			`next_state = READ;`
398
399
400
401			`if (cmd_fifo_rdy && ((rdp_rdy_i && cmd_rd) \|\| (wdp_rdy_i && cmd_wr) \|\| (cmd_others)))`
402			`cmd_rdy = 1'b1;`
403			`else`
404			`cmd_rdy = 1'b0;`
405
406
407
408			`end`
409			`READ: begin`
410
411			`if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy )`
412			`begin`
413			`next_state = READ;`
414			`push_cmd = 1'b1;`
415			`rdp_valid = 1'b1;`
416			`wdp_valid = 1'b0;`
417			`xfer_cmd = 1'b1;`
418			`tstpointA = 4'b0101;`
419
420			`end`
421			`else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )`
422			`begin`
423			`next_state = WRITE;`
424			`push_cmd = 1'b1;`
425			`xfer_cmd = 1'b1;`
426
427			`wdp_valid = 1'b1;`
428			`wdp_validB = 1'b1;`
429			`wdp_validC = 1'b1;`
430
431			`tstpointA = 4'b0110;`
432
433			`end`
434
435			`else if (!rdp_rdy_i )`
436			`begin`
437			`next_state = READ;`
438			`push_cmd = 1'b0;`
439			`xfer_cmd = 1'b0;`
440
441			`tstpointA = 4'b0111;`
442
443			`wdp_valid = 1'b0;`
444			`wdp_validB = 1'b0;`
445			`wdp_validC = 1'b0;`
446			`rdp_valid = 1'b0;`
447			`end`
448			`else if (last_word_rd_i && cmd_others && cmd_fifo_rdy )`
449
450			`begin`
451			`next_state = REFRESH_ST;`
452			`push_cmd = 1'b1;`
453			`xfer_cmd = 1'b1;`
454			`wdp_valid = 1'b0;`
455			`wdp_validB = 1'b0;`
456			`wdp_validC = 1'b0;`
457			`rdp_valid = 1'b0;`
458			`tstpointA = 4'b1000;`
459
460			`end`
461			`else if (!cmd_fifo_rdy \|\| !wdp_rdy_i)`
462
463			`begin`
464			`next_state = CMD_WAIT;`
465			`tstpointA = 4'b1001;`
466
467			`end`
468			`else`
469			`next_state = READ;`
470
471
472
473			`if ((rdp_rdy_i && cmd_rd \|\| cmd_wr && wdp_rdy_i \|\| cmd_others) && cmd_fifo_rdy)`
474			`cmd_rdy = wait_done;//1'b1;`
475			`else`
476			`cmd_rdy = 1'b0;`
477
478
479			`end`
480			`WRITE: begin // for write, always wait until the last_word_wr`
481			`if (cmd_fifo_rdy && cmd_rd && rdp_rdy_i && last_word_wr_i)`
482			`begin`
483			`next_state = READ;`
484			`push_cmd = 1'b1;`
485			`xfer_cmd = 1'b1;`
486			`rdp_valid = 1'b1;`
487			`tstpointA = 4'b0000;`
488			`end`
489			`else if (!wdp_rdy_i \|\| (wdp_rdy_i && cmd_wr && cmd_fifo_rdy && last_word_wr_i) )`
490			`begin`
491			`next_state = WRITE;`
492			`tstpointA = 4'b0001;`
493
494			`if (cmd_wr && last_word_wr_i) begin`
495			`wdp_valid = 1'b1;`
496			`wdp_validB = 1'b1;`
497			`wdp_validC = 1'b1;`
498
499			`end`
500			`else begin`
501			`wdp_valid = 1'b0;`
502			`wdp_validB = 1'b0;`
503			`wdp_validC = 1'b0;`
504
505			`end`
506
507			`if (last_word_wr_i ) begin`
508			`push_cmd = 1'b1;`
509			`xfer_cmd = 1'b1;`
510			`end`
511			`else begin`
512			`push_cmd = 1'b0;`
513			`xfer_cmd = 1'b0;`
514			`end`
515
516			`end`
517			`else if (last_word_wr_i && cmd_others && cmd_fifo_rdy)`
518			`begin`
519			`next_state = REFRESH_ST;`
520			`push_cmd = 1'b1;`
521			`xfer_cmd = 1'b1;`
522			`tstpointA = 4'b0010;`
523
524			`wdp_valid = 1'b0;`
525			`wdp_validB = 1'b0;`
526			`wdp_validC = 1'b0;`
527
528			`rdp_valid = 1'b0;`
529
530			`end`
531
532			`else if (!cmd_fifo_rdy && last_word_wr_i \|\| !rdp_rdy_i \|\| (!cmd_valid_i && wait_done) )`
533
534			`begin`
535			`next_state = CMD_WAIT;`
536			`push_cmd = 1'b0;`
537			`xfer_cmd = 1'b0;`
538			`tstpointA = 4'b0011;`
539
540			`end`
541
542			`else begin`
543			`next_state = WRITE;`
544			`tstpointA = 4'b0100;`
545
546			`end`
547
548			`// need to include rdp_rdy_i to prevent sending read command if`
549			`// read_data_port fifo is full in MCB`
550			`if (last_word_wr_i && (cmd_others \|\| rdp_rdy_i && cmd_rd \|\| cmd_wr && wdp_rdy_i) && cmd_fifo_rdy)`
551			`cmd_rdy = wait_done;//1'b1;`
552			`else`
553			`cmd_rdy = 1'b0;`
554
555
556			`end`
557
558
559
560
561
562			`CMD_WAIT: if (!cmd_fifo_rdy \|\| wr_in_progress)`
563			`begin`
564			`next_state = CMD_WAIT;`
565			`cmd_rdy = 1'b0;`
566			`tstpointA = 4'b1010;`
567
568			`end`
569			`else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd)`
570			`begin`
571			`next_state = READ;`
572			`push_cmd = 1'b1;`
573			`xfer_cmd = 1'b1;`
574			`cmd_rdy = 1'b1;`
575			`rdp_valid = 1'b1;`
576
577			`tstpointA = 4'b1011;`
578			`end`
579			`else if (cmd_fifo_rdy && cmd_wr && (wait_done \|\| cmd_wr_pending_r1))`
580
581			`begin`
582			`next_state = WRITE;`
583			`push_cmd = 1'b1;`
584			`xfer_cmd = 1'b1;`
585			`wdp_valid = 1'b1;`
586			`wdp_validB = 1'b1;`
587			`wdp_validC = 1'b1;`
588
589			`cmd_rdy = 1'b1;`
590			`tstpointA = 4'b1100;`
591
592			`end`
593			`else if (cmd_fifo_rdy && cmd_others)`
594			`begin`
595			`next_state = REFRESH_ST;`
596			`push_cmd = 1'b1; /////////////////`
597			`xfer_cmd = 1'b1;`
598			`tstpointA = 4'b1101;`
599			`cmd_rdy = 1'b1;`
600
601			`end`
602			`else`
603			`begin`
604			`next_state = CMD_WAIT;`
605			`tstpointA = 4'b1110;`
606
607			`if ((wdp_rdy_i && rdp_rdy_i))`
608			`cmd_rdy = 1'b1;`
609			`else`
610			`cmd_rdy = 1'b0;`
611
612
613			`end`
614
615
616			`default:`
617			`begin`
618			`push_cmd = 1'b0;`
619			`xfer_cmd = 1'b0;`
620
621			`wdp_valid = 1'b0;`
622			`wdp_validB = 1'b0;`
623			`wdp_validC = 1'b0;`
624			`next_state = READY;`
625			`// cmd_rdy = 1'b0;`
626
627
628
629			`end`
630
631			`endcase`
632			`end`
633
634			`endmodule`