Subversion Repositories usb_fpga_2_14

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//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version: %version

//  \   \         Application: MIG

//  /   /         Filename: data_gen.v

// /___/   /\     Date Last Modified: 

// \   \  /  \    Date Created: 

//  \___\/\___\

//

//Device: Virtex6

//Design Name: DDR2/DDR3/QDDR 

//Purpose: This module generates different data pattern as described in 

//         parameter DATA_PATTERN and is set up for Virtex 6 family.

//Reference:            

//Revision History:  18/7/2011  Fixed DGEN_NEIGHBOR in generate statement .

//*****************************************************************************

`timescale 1ps/1ps

`ifndef TCQ

 `define TCQ 100

`endif

module v6_data_gen #

(  parameter TCQ        = 100,

   parameter EYE_TEST   = "FALSE",

   parameter ADDR_WIDTH = 32,

   parameter MEM_BURST_LEN = 8,

   parameter BL_WIDTH = 6,

   parameter DWIDTH = 32,

   parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  

   parameter NUM_DQ_PINS   = 8,

   parameter COLUMN_WIDTH = 10,

   parameter SEL_VICTIM_LINE = 3  // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern

//   parameter [287:0] ALL_1 = {288{1'b1}},

//   parameter [287:0] ALL_0 = {288{1'b0}}

 )

 (

   input   clk_i,                 //

   input   rst_i,

   input [31:0] prbs_fseed_i,

   input [3:0]  data_mode_i,   // "00" = bram; 

   input        data_rdy_i,

   input   cmd_startA,

   input   cmd_startB,

   input   cmd_startC,

   input   cmd_startD,

   input   cmd_startE,

   input [ADDR_WIDTH-1:0]  m_addr_i,          // generated address used to determine data pattern.

   input [DWIDTH-1:0]     fixed_data_i,

   input [ADDR_WIDTH-1:0]  addr_i,          // generated address used to determine data pattern.

   input [6:0]    user_burst_cnt,   // generated burst length for control the burst data

   input   fifo_rdy_i,           // connect from mcb_wr_full when used as wr_data_gen

                                 // connect from mcb_rd_empty when used as rd_data_gen

                                 // When both data_rdy and data_valid is asserted, the ouput data is valid.

   output  [NUM_DQ_PINS*4-1:0] data_o   // generated data pattern   

);

// 

wire [31:0]       prbs_data;

reg [35:0] acounts;

wire [NUM_DQ_PINS*4-1:0]        adata;

reg [NUM_DQ_PINS*4-1:0]        hdata;

reg [NUM_DQ_PINS*4-1:0]        hdata_c;

reg [NUM_DQ_PINS*4-1:0]        ndata;

reg [NUM_DQ_PINS*4-1:0]  w1data;

reg [NUM_DQ_PINS*4-1:0]  w1trash;

reg [NUM_DQ_PINS*4-1:0]        w0data;

reg [NUM_DQ_PINS*4-1:0] data;

reg burst_count_reached2;

reg               data_valid;

reg [2:0] walk_cnt;

reg [ADDR_WIDTH-1:0] user_address;

reg sel_w1gen_logic;

wire [4*NUM_DQ_PINS -1 :0] ZEROS;

wire [4*NUM_DQ_PINS -1 :0] ONES;

reg [7:0] BLANK;

reg [7:0] SHIFT_0;

reg [7:0] SHIFT_1;

reg [7:0] SHIFT_2;

reg [7:0] SHIFT_3;

reg [7:0] SHIFT_4;

reg [7:0] SHIFT_5;

reg [7:0] SHIFT_6;

reg [7:0] SHIFT_7;

reg [4*NUM_DQ_PINS -1 :0] sel_victimline_r;

wire data_clk_en;

wire [NUM_DQ_PINS*4-1:0] full_prbs_data;

reg [NUM_DQ_PINS*4-1:0] h_prbsdata;

//wire [4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] ALL_1 = 

assign ZEROS = 'b0;

assign ONES = 'b1;

integer i,j,k;

reg [BL_WIDTH-1:0] user_bl;

//*********************************************************************************************

localparam BRAM_DATAL_MODE       =    4'b0000;

localparam FIXED_DATA_MODE       =    4'b0001;

localparam ADDR_DATA_MODE        =    4'b0010;

localparam HAMMER_DATA_MODE      =    4'b0011;

localparam NEIGHBOR_DATA_MODE    =    4'b0100;

localparam WALKING1_DATA_MODE    =    4'b0101;

localparam WALKING0_DATA_MODE    =    4'b0110;

localparam PRBS_DATA_MODE        =    4'b0111;

assign data_o = data;

//assign full_prbs_data = {prbs_data,prbs_data,prbs_data,prbs_data,prbs_data,prbs_data,prbs_data,prbs_data,prbs_data};

assign full_prbs_data = {DWIDTH/32{prbs_data}};

reg [3:0] data_mode_rr_a;

reg [3:0] data_mode_rr_b;

reg [3:0] data_mode_rr_c;

always @ (posedge clk_i)

begin

  data_mode_rr_a <= #TCQ data_mode_i;

  data_mode_rr_b <= #TCQ data_mode_i;

  data_mode_rr_c <= #TCQ data_mode_i;

end

always @ (data_mode_i,rst_i) begin

  if (data_mode_i == 3'b101 || data_mode_i == 3'b100  || rst_i) begin // WALKING ONE

    BLANK   = 8'h00;

    SHIFT_0 = 8'h01;

    SHIFT_1 = 8'h02;

    SHIFT_2 = 8'h04;

    SHIFT_3 = 8'h08;

    SHIFT_4 = 8'h10;

    SHIFT_5 = 8'h20;

    SHIFT_6 = 8'h40;

    SHIFT_7 = 8'h80;

    end

    else  begin  // WALKING ZERO

    BLANK   = 8'hff;

    SHIFT_0 = 8'hfe;

    SHIFT_1 = 8'hfd;

    SHIFT_2 = 8'hfb;

    SHIFT_3 = 8'hf7;

    SHIFT_4 = 8'hef;

    SHIFT_5 = 8'hdf;

    SHIFT_6 = 8'hbf;

    SHIFT_7 = 8'h7f;

    end

end

always @ (data_mode_rr_a,fixed_data_i,h_prbsdata,adata,hdata,ndata,w1data,full_prbs_data)

begin

   case(data_mode_rr_a)

         4'b0000: data = h_prbsdata;

         4'b0001: data = fixed_data_i;   //  "000" = address as data    

         4'b0010: data = adata;   //  "000" = address as data 

         4'b0011: data = hdata;   //  "001" = hammer

         4'b0100: data = ndata;   //  "010" = neighbour

         4'b0101: data = w1data;    //  "100" = walking 0's 

         4'b0110: data = w1data;  // /"101" = walking 1's

         4'b0111: data = full_prbs_data;//{prbs_data,prbs_data,prbs_data,prbs_data};   //  "011" = prbs         

         default : data = 'b0;

   endcase

end

//always @ (data_mode_rr_a,fixed_data_i,h_prbsdata,adata,hdata,ndata,w1data,full_prbs_data)

//begin

//

// data = w1data;

//end

function [4*NUM_DQ_PINS-1:0] Data_Gen (input integer i );

 integer j;

  begin

    j = i/2;

    Data_Gen = {4*NUM_DQ_PINS{1'b0}};

        if(i %2) begin

             Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;

             Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;

             Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;

             Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;

        end else begin

            Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;

            Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;

            Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;

            Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;

        end

  end

endfunction

/*

function [4*NUM_DQ_PINS-1:0] Data_Gen (input integer i,

                                       input [3:0] data_mode);

 integer j;

  begin

    j = i/2;

    Data_Gen = {4*NUM_DQ_PINS{1'b0}};

      if(data_mode == 4'b0101) begin // Walking 1 pattern

        if(i %2) begin

             Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;

             Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;

             Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;

             Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;

        end else begin

            Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;

            Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;

            Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;

            Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;

        end

      end else begin // Walking 0 pattern

        if(i %2) begin

             Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;

             Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;

             Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;

             Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;

        end else begin

            Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;

            Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;

            Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;

            Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;

        end

      end

   end

endfunction

*/

function [4*NUM_DQ_PINS-1:0] Data_GenW0 (input integer i);

 integer j;

  begin

    j = i/2;

    Data_GenW0 = {4*NUM_DQ_PINS{1'b1}};

        if(i %2) begin

             Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;

             Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;

             Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;

             Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;

        end else begin

            Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;

            Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;

            Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;

            Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;

        end

  end

endfunction

always @ (posedge clk_i) begin

 if (data_mode_rr_c[2:0] == 3'b101  || data_mode_rr_c[2:0] == 3'b100 || data_mode_rr_c[2:0] == 3'b110)   // WALKING ONES

     sel_w1gen_logic <= #TCQ 1'b1;

 else

     sel_w1gen_logic <= #TCQ 1'b0;

end

// WALKING ONES, WALKING ZEROS; HAMMER GENERATION

generate

if (NUM_DQ_PINS == 8 && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0"  || DATA_PATTERN == "DGEN_ALL"))  begin : WALKING_ONE_8_PATTERN

always @ (posedge clk_i)

begin

if( (fifo_rdy_i ) || cmd_startC )

 if (cmd_startC )

    begin

    if (sel_w1gen_logic) begin  // 1b WALKING ONES

 //******************  (NUM_DQ_PINS == 8)

            // first 8 pins

             case (addr_i[3])

                 0: begin

                    if (data_mode_i == 4'b0101)

                    w1data <= #TCQ Data_Gen(0);

                    else

                    w1data <= #TCQ Data_GenW0(0);

                    end

                 1:  begin

                    if (data_mode_i == 4'b0101)

                    w1data <= #TCQ Data_Gen(1);

                    else

                    w1data <= #TCQ Data_GenW0(1);

                    end

                 default :begin

                    w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0;

                    end

             endcase

     end //  1b data_mode WALKING ONE

   end // 1c 

   else if( MEM_BURST_LEN == 8)  begin

              w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS  ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};

              w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS  ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};

              w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS  ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};

              w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS  ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};

               end

  end  // always

end //  endgenerate

endgenerate  // NUM_DQ_PINS == 8

generate

if (NUM_DQ_PINS == 16 && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL"))  begin : WALKING_ONE_16_PATTERN

always @ (posedge clk_i)

begin

if( (fifo_rdy_i ) || cmd_startC )

 if (cmd_startC )

    begin

    if (sel_w1gen_logic) begin  // 1a  WALKING ONES

             case (addr_i[4:3])

                 0: begin // 8 pins

                    if (data_mode_i == 4'b0101)

                    w1data <= #TCQ Data_Gen(0);

                    else

                    w1data <= #TCQ Data_GenW0(0);

                    end

                 1:  begin

                    if (data_mode_i == 4'b0101)

                    w1data <= #TCQ Data_Gen(1);

                    else

                    w1data <= #TCQ Data_GenW0(1);

                    end

                  2: begin // 16 pins 

                    if (data_mode_i == 4'b0101)

                    w1data <= #TCQ Data_Gen(2);

                    else

                    w1data <= #TCQ Data_GenW0(2);

                    end

                 3:  begin

                    if (data_mode_i == 4'b0101)

                    w1data <= #TCQ Data_Gen(3);

                    else

                    w1data <= #TCQ Data_GenW0(3);

                    end

                   default :begin

                    w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0;

                    end

             endcase

     end // 1a data_mode WALKING ONE

   end // 1b StartC   

   else if( MEM_BURST_LEN == 8) begin

              w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS  ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};

              w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS  ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};

              w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS  ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};

              w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS  ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};

               end

  end

end   //1d

endgenerate // NUM_DQ_PINS == 16

  generate

    if ((NUM_DQ_PINS == 24 ) && (DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_NEIGHBOR"

                                || DATA_PATTERN == "DGEN_ALL"))  begin : WALKING_ONE_24_PATTERN

      always @ (posedge clk_i) begin

        if( (fifo_rdy_i ) || cmd_startC )

          if (cmd_startC ) begin

            if (sel_w1gen_logic) begin

               case (addr_i[7:3])

                 0, 6, 12,

                 18, 24, 30 :

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(0);

                              else

                                  w1data <= #TCQ Data_GenW0(0);

                 1, 7, 13,

                 19, 25, 31 :

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(1);

                              else

                                  w1data <= #TCQ Data_GenW0(1);

                 2,8,14,20,26         :

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(2);

                              else

                                  w1data <= #TCQ Data_GenW0(2);

                 3,9,15,21,27         :

                                 if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(3);

                                 else

                                  w1data <=#TCQ  Data_GenW0(3);

                4, 10,

                16, 22, 28 :

                           if (data_mode_i == 4'b0101)

                               w1data <= #TCQ  Data_Gen(4);

                           else

                               w1data <= #TCQ Data_GenW0(4);

                 5, 11,

                 17, 23, 29 :

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(5);

                              else

                                  w1data <= #TCQ Data_GenW0(5);

                 default :

                    w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0;

            endcase

       end

     end

   else if ( MEM_BURST_LEN == 8)  begin

              w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS  ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};

              w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS  ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};

              w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS  ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};

              w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS  ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};

        end

      end

    end

  endgenerate

  generate

    if (NUM_DQ_PINS == 32 && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL"))  begin : WALKING_ONE_32_PATTERN

      always @ (posedge clk_i) begin

         if( (fifo_rdy_i ) || cmd_startC )

           if (cmd_startC ) begin

             if (sel_w1gen_logic) begin

               case (addr_i[6:4])

                 0:

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(0);

                              else

                                  w1data <= #TCQ Data_GenW0(0);

                 1:

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(1);

                              else

                                  w1data <= #TCQ Data_GenW0(1);

                 2:

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(2);

                              else

                                  w1data <= #TCQ Data_GenW0(2);

                 3:

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(3);

                              else

                                  w1data <= #TCQ Data_GenW0(3);

                 4:

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(4);

                              else

                                  w1data <= #TCQ Data_GenW0(4);

                 5:

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(5);

                              else

                                  w1data <= #TCQ Data_GenW0(5);

                 6:

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(6);

                              else

                                  w1data <= #TCQ Data_GenW0(6);

                 7:

                              if (data_mode_i == 4'b0101)

                                  w1data <= #TCQ Data_Gen(7);

                              else

                                  w1data <= #TCQ Data_GenW0(7);

           endcase

       end

     end

   else if ( MEM_BURST_LEN == 8)  begin

              w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS  ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};

              w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS  ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};

              w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS  ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};

              w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS  ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};