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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [synth/] [mem_interface_top_synp.sdc] - Blame information for rev 2

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1 2 ZTEX
# Synplicity, Inc. constraint file
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# Written on Mon Jun 27 15:50:39 2005
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define_attribute          {v:work.infrastructure} syn_hier {hard}
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define_attribute          {v:work.mem0} syn_hier {hard}
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define_attribute          {v:work.memc_wrapper} syn_hier {hard}
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define_attribute          {v:work.iodrp_controller} syn_hier {hard}
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define_attribute          {v:work.iodrp_mcb_controller} syn_hier {hard}
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define_attribute          {v:work.mcb_raw_wrapper} syn_hier {hard}
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define_attribute          {v:work.mcb_soft_calibration} syn_hier {hard}
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define_attribute          {v:work.mcb_soft_calibration_top} syn_hier {hard}
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define_attribute          {v:work.mcb_ui_top} syn_hier {hard}
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# clock Constraints
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define_clock -disable -name {memc3_infrastructure_inst} -period 5000 -clockgroup default_clkgroup_1
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define_clock          -name {memc3_infrastructure_inst.SYS_CLK_INST} -period 5000 -clockgroup default_clkgroup_2
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define_clock -disable -name {memc3_infrastructure_inst.u_pll_adv} -period 5000 -clockgroup default_clkgroup_3
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