URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [synth/] [script_synp.tcl] - Blame information for rev 2

Details | Compare with Previous | View Log


project -new
add_file -verilog "../rtl/infrastructure.v"
add_file -verilog "../rtl/mem0.v"
add_file -verilog "../rtl/memc_wrapper.v"
add_file -verilog "../rtl/mcb_controller/iodrp_controller.v"
add_file -verilog "../rtl/mcb_controller/iodrp_mcb_controller.v"
add_file -verilog "../rtl/mcb_controller/mcb_raw_wrapper.v"
add_file -verilog "../rtl/mcb_controller/mcb_soft_calibration.v"
add_file -verilog "../rtl/mcb_controller/mcb_soft_calibration_top.v"
add_file -verilog "../rtl/mcb_controller/mcb_ui_top.v"
add_file -constraint "../synth/mem_interface_top_synp.sdc"
impl -add rev_1
set_option -technology spartan6
set_option -part xc6slx16
set_option -package ftg256
set_option -speed_grade -2
set_option -default_enum_encoding default
#AXI_ENABLE synp definition is not required for user_design
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 0
set_option -use_fsm_explorer 0
set_option -top_module "mem0"
set_option -frequency 200
set_option -fanout_limit 1000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -fixgatedclocks 0
set_option -retiming 0
set_option -modular 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -write_apr_constraint 0
project -result_file "../synth/rev_1/mem0.edf"
set_option -vlog_std v2001
set_option -auto_constrain_io 0
impl -active "../synth/rev_1"
project -run
project -save
 

Line No.	Rev	Author	Line
1	2	ZTEX	`project -new`
2			`add_file -verilog "../rtl/infrastructure.v"`
3			`add_file -verilog "../rtl/mem0.v"`
4			`add_file -verilog "../rtl/memc_wrapper.v"`
5			`add_file -verilog "../rtl/mcb_controller/iodrp_controller.v"`
6			`add_file -verilog "../rtl/mcb_controller/iodrp_mcb_controller.v"`
7			`add_file -verilog "../rtl/mcb_controller/mcb_raw_wrapper.v"`
8			`add_file -verilog "../rtl/mcb_controller/mcb_soft_calibration.v"`
9			`add_file -verilog "../rtl/mcb_controller/mcb_soft_calibration_top.v"`
10			`add_file -verilog "../rtl/mcb_controller/mcb_ui_top.v"`
11			`add_file -constraint "../synth/mem_interface_top_synp.sdc"`
12			`impl -add rev_1`
13			`set_option -technology spartan6`
14			`set_option -part xc6slx16`
15			`set_option -package ftg256`
16			`set_option -speed_grade -2`
17			`set_option -default_enum_encoding default`
18			`#AXI_ENABLE synp definition is not required for user_design`
19			`set_option -symbolic_fsm_compiler 1`
20			`set_option -resource_sharing 0`
21			`set_option -use_fsm_explorer 0`
22			`set_option -top_module "mem0"`
23			`set_option -frequency 200`
24			`set_option -fanout_limit 1000`
25			`set_option -disable_io_insertion 0`
26			`set_option -pipe 1`
27			`set_option -fixgatedclocks 0`
28			`set_option -retiming 0`
29			`set_option -modular 0`
30			`set_option -update_models_cp 0`
31			`set_option -verification_mode 0`
32			`set_option -write_verilog 0`
33			`set_option -write_vhdl 0`
34			`set_option -write_apr_constraint 0`
35			`project -result_file "../synth/rev_1/mem0.edf"`
36			`set_option -vlog_std v2001`
37			`set_option -auto_constrain_io 0`
38			`impl -active "../synth/rev_1"`
39			`project -run`
40			`project -save`
41

Browse

Tools

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [ipcore_dir/] [mem0/] [user_design/] [synth/] [script_synp.tcl] - Blame information for rev 2