URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [memfifo.vhd] - Blame information for rev 2

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library ieee;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Library UNISIM;
use UNISIM.vcomponents.all;
 
-- 
--   Top level module: glues everything together.    
--  
 
entity memfifo is
     port (
        fxclk_in : in std_logic;
        ifclk_in : in std_logic;
        reset    : in std_logic;
        mode     : in std_logic_vector(1 downto 0);
        -- debug
        led1 : out std_logic_vector(9 downto 0);
        led2 : out std_logic_vector(13 downto 0);
        SW8  : in std_logic;
        SW10 : in std_logic;
        -- ddr pins
        ddr_dram_dq    : inout std_logic_vector(15 downto 0);
        ddr_rzq        : inout std_logic;
        ddr_zio        : inout std_logic;
        ddr_dram_udqs  : inout std_logic;
        ddr_dram_dqs   : inout std_logic;
        ddr_dram_a     : out std_logic_vector(12 downto 0);
        ddr_dram_ba    : out std_logic_vector(1 downto 0);
        ddr_dram_cke   : out std_logic;
        ddr_dram_ras_n : out std_logic;
        ddr_dram_cas_n : out std_logic;
        ddr_dram_we_n  : out std_logic;
        ddr_dram_dm    : out std_logic;
        ddr_dram_udm   : out std_logic;
        ddr_dram_ck    : out std_logic;
        ddr_dram_ck_n  : out std_logic;
        -- ez-usb
        fd        : inout std_logic_vector(15 downto 0);
        SLWR      : out std_logic;
        SLRD      : out std_logic;
        SLOE      : out std_logic;
        FIFOADDR0 : out std_logic;
        FIFOADDR1 : out std_logic;
        PKTEND    : out std_logic;
        FLAGA     : in std_logic;
        FLAGB     : in std_logic
    );
end memfifo;
 
 
architecture RTL of memfifo is
 
component dram_fifo
    generic (
        CLKOUT_DIVIDE : INTEGER := 2    -- (2, 4, 8, 16, 32), see clkout
    );
    port (
        fxclk_in  : in std_logic;       -- 48 MHz input clock pin
        reset     : in std_logic;       -- reset in
        reset_out : out std_logic;      -- reset output
        clkout    : out std_logic;      -- clock output 200MHz/CLKOUT_DIVIDE
        -- ddr pins
        ddr_dram_dq    : inout std_logic_vector(15 downto 0);
        ddr_rzq        : inout std_logic;
        ddr_zio        : inout std_logic;
        ddr_dram_udqs  : inout std_logic;
        ddr_dram_dqs   : inout std_logic;
        ddr_dram_a     : out std_logic_vector(12 downto 0);
        ddr_dram_ba    : out std_logic_vector(1 downto 0);
        ddr_dram_cke   : out std_logic;
        ddr_dram_ras_n : out std_logic;
        ddr_dram_cas_n : out std_logic;
        ddr_dram_we_n  : out std_logic;
        ddr_dram_dm    : out std_logic;
        ddr_dram_udm   : out std_logic;
        ddr_dram_ck    : out std_logic;
        ddr_dram_ck_n  : out std_logic;
 
        -- FIFO protocol equal to FWFT FIFO in "7 Series Memory Resources" user guide (ug743)
        -- input fifo interface
        DI          : in std_logic_vector(31  downto 0);     -- must be hold while FULL is asserted
        FULL        : out std_logic;                         -- 1-bit output: Full flag
        WRERR       : out std_logic;                         -- 1-bit output: Write error
        WRCLK       : in std_logic;                          -- 1-bit input: Rising edge write clock.
        WREN        : in std_logic;                          -- 1-bit input: Write enable
 
        -- output fifo interface                             
        DO           : out std_logic_vector(31  downto 0);
        EMPTY        : out std_logic;                        -- 1-bit output: Empty flag, can be used as data valid indicator
        RDERR        : out std_logic;                        -- 1-bit output: Read error
        RDCLK        : in std_logic;                         -- 1-bit input: Read clock
        RDEN         : in std_logic;                         -- 1-bit input: Read enable                                     
 
        -- free memory
        mem_free_out : out std_logic_vector(17 downto 0);
 
        -- for debugging
        status       : out std_logic_vector(9  downto 0)
    );
end component;
 
component ezusb_io
    generic (
        OUTEP : INTEGER := 2;                                 -- EP for FPGA -> EZ-USB transfers
        INEP  : INTEGER := 6                                  -- EP for EZ-USB -> FPGA transfers 
    );
    port (
        ifclk     : out std_logic;
        reset     : in std_logic;                             -- asynchronous reset input
        reset_out : out std_logic;                            -- synchronous reset output
        -- pins                                               
        ifclk_in   : in std_logic;
        fd         : inout std_logic_vector(15  downto 0);
        SLWR       : out std_logic;
        PKTEND     : out std_logic;
        SLRD       : out std_logic;
        SLOE       : out std_logic;
        FIFOADDR   : out std_logic_vector(1  downto 0);
        EMPTY_FLAG : in std_logic;
        FULL_FLAG  : in std_logic;
        -- signals for FPGA -> EZ-USB transfer                 
        DI        : in std_logic_vector(15  downto 0);         -- data written to EZ-USB
        DI_valid  : in std_logic;                              -- 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0
        DI_ready  : out std_logic;                             -- 1 if new data are accepted
        DI_enable : in std_logic;                              -- setting to 0 disables FPGA -> EZ-USB transfers
        pktend_timeout : in std_logic_vector(15  downto 0);    -- timeout in multiples of 65536 clocks before a short packet committed
                                                               -- setting to 0 disables this feature
        -- signals for EZ-USB -> FPGA transfer                                                                                                                                          
        DO       : out std_logic_vector(15  downto 0);         -- data read from EZ-USB
        DO_valid : out std_logic;                              -- 1 indicated valid data
        DO_ready : in std_logic;                               -- setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0  
                                                               -- set to 0 to disable data reads                                                                        
        -- debug output
        status : out std_logic_vector(3  downto 0)
    );
end component;
 
 
signal reset2      : std_logic;
signal reset_mem   : std_logic;
signal reset_usb   : std_logic;
signal ifclk       : std_logic;
signal reset_ifclk : std_logic;
signal mem_free    : std_logic_vector(17 downto 0);
signal status      : std_logic_vector(9 downto 0);
signal if_status   : std_logic_vector(3 downto 0);
signal mode_buf    : std_logic_vector(1 downto 0);
 
-- input fifo
signal DI           : std_logic_vector(31 downto 0);
signal FULL         : std_logic;
signal WRERR        : std_logic;
signal USB_DO_valid : std_logic;
signal DO_ready     : std_logic;
signal WREN         : std_logic;
signal wrerr_buf    : std_logic;
signal USB_DO       : std_logic_vector(15 downto 0);
signal in_data      : std_logic_vector(31 downto 0);
signal wr_cnt       : std_logic_vector(3 downto 0);
signal test_cnt     : std_logic_vector(6 downto 0);
signal test_cs      : std_logic_vector(13 downto 0);
signal in_valid     : std_logic;
signal test_sync    : std_logic;
signal clk_div      : std_logic_vector(1 downto 0);
 
-- output fifo
signal DO           : std_logic_vector(31 downto 0);
signal EMPTY        : std_logic;
signal RDERR        : std_logic;
signal USB_DI_ready : std_logic;
signal RDEN         : std_logic;
signal rderr_buf    : std_logic;
signal USB_DI_valid : std_logic;
signal rd_buf       : std_logic_vector(31 downto 0);
signal rd_cnt       : std_logic;
 
 
begin
    dram_fifo_inst : dram_fifo
    port map (
        fxclk_in  => fxclk_in,         -- 48 MHz input clock pin            
        reset     => reset2,           -- reset in
        reset_out => reset_mem,        -- reset output
        clkout    => open,             -- clock output 200MHz/CLKOUT_DIVIDE
        -- ddr pins
        ddr_dram_dq    => ddr_dram_dq,
        ddr_rzq        => ddr_rzq,
        ddr_zio        => ddr_zio,
        ddr_dram_udqs  => ddr_dram_udqs,
        ddr_dram_dqs   => ddr_dram_dqs,
        ddr_dram_a     => ddr_dram_a,
        ddr_dram_ba    => ddr_dram_ba,
        ddr_dram_cke   => ddr_dram_cke,
        ddr_dram_ras_n => ddr_dram_ras_n,
        ddr_dram_cas_n => ddr_dram_cas_n,
        ddr_dram_we_n  => ddr_dram_we_n,
        ddr_dram_dm    => ddr_dram_dm,
        ddr_dram_udm   => ddr_dram_udm,
        ddr_dram_ck    => ddr_dram_ck,
        ddr_dram_ck_n  => ddr_dram_ck_n,
        -- input fifo interface, see "7 Series Memory Resources" user guide (ug743)
        DI          => DI,
        FULL        => FULL,           -- 1-bit output: Full flag
        WRERR       => WRERR,          -- 1-bit output: Write error
        WREN        => WREN,           -- 1-bit input: Write enable
        WRCLK       => ifclk,          -- 1-bit input: Rising edge write clock.
        -- output fifo interface, see "7 Series Memory Resources" user guide (ug743)
        DO           => DO,
        EMPTY        => EMPTY,         -- 1-bit output: Empty flag
        RDERR        => RDERR,         -- 1-bit output: Read error
        RDCLK        => ifclk,         -- 1-bit input: Read clock
        RDEN         => RDEN,          -- 1-bit input: Read enable
        -- free memory
        mem_free_out => mem_free,
        -- for debugging
        status       => status
    );
 
    ezusb_io_inst : ezusb_io
    generic map (
        OUTEP => 2,                     -- EP for FPGA -> EZ-USB transfers
        INEP  => 6                      -- EP for EZ-USB -> FPGA transfers 
    )
    port map (
        ifclk     => ifclk,
        reset     => reset,             -- asynchronous reset input
        reset_out => reset_usb,         -- synchronous reset output
        -- pins
        ifclk_in   => ifclk_in,
        fd         => fd,
        SLWR       => SLWR,
        SLRD       => SLRD,
        SLOE       => SLOE,
        PKTEND     => PKTEND,
        FIFOADDR(0)=> FIFOADDR0,
        FIFOADDR(1)=> FIFOADDR1,
        EMPTY_FLAG => FLAGA,
        FULL_FLAG  => FLAGB,
        -- signals for FPGA -> EZ-USB transfer
        DI             => rd_buf(15 downto 0),   -- data written to EZ-USB
        DI_valid       => USB_DI_valid,         -- 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0
        DI_ready       => USB_DI_ready,         -- 1 if new data are accepted
        DI_enable      => '1',                  -- setting to 0 disables FPGA -> EZ-USB transfers
        pktend_timeout => conv_std_logic_vector(90,16),         -- timeout in multiples of 65536 clocks (approx. 0.1s @ 48 MHz) before a short packet committed
                                                -- setting to 0 disables this feature
        -- signals for EZ-USB -> FPGA transfer
        DO       => USB_DO,                     -- data read from EZ-USB
        DO_valid => USB_DO_valid,               -- 1 indicated valid data
        DO_ready => DO_ready,                   -- setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0
        -- debug output
        status   => if_status
    );
 
    reset2 <= reset or reset_usb;
    DO_ready <= '1' when ( (mode_buf="00") and (reset_ifclk='0') and (FULL='0') ) else '0';
 
    -- debug board LEDs    
    led1 <= status when (SW10='1') else (EMPTY & FULL & wrerr_buf & rderr_buf & if_status & FLAGB & FLAGA);
 
    led2(0) <= '1' when mem_free(17 downto 13) = conv_std_logic_vector(31,5) else '0';
    led2(1) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(30,5) else '0';
    led2(2) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(27,5) else '0';
    led2(3) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(25,5) else '0';
    led2(4) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(22,5) else '0';
    led2(5) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(20,5) else '0';
    led2(6) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(17,5) else '0';
    led2(7) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(15,5) else '0';
    led2(8) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(12,5) else '0';
    led2(9) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(10,5) else '0';
    led2(10) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(7,5) else '0';
    led2(11) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(5,5) else '0';
    led2(12) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(2,5) else '0';
    led2(13) <= '1' when mem_free = conv_std_logic_vector(0,18) else '0';
 
    test_sync <= '1' when ( (wr_cnt="1110") or (wr_cnt(0)='1') ) else '0';
 
    dpifclk: process
    begin
        wait until ( ifclk'EVENT and (ifclk = '1') );
 
        -- reset
        reset_ifclk <= (reset or reset_usb) or reset_mem;
        if ( reset_ifclk = '1' ) then
            rderr_buf <= '0';
            wrerr_buf <= '0';
        else
            rderr_buf <= rderr_buf or RDERR;
            wrerr_buf <= wrerr_buf or WRERR;
        end if;
 
        -- FPGA -> EZ-USB FIFO
        if ( reset_ifclk = '1' ) then
            rd_cnt <= '0';
            USB_DI_valid <= '0';
        else
            if ( USB_DI_ready = '1' ) then
                USB_DI_valid <= not EMPTY;
                if ( EMPTY = '0' ) then
                    if ( rd_cnt = '0' ) then
                        rd_buf <= DO;
                    else
                        rd_buf(15 downto 0) <= rd_buf(31 downto 16);
                    end if;
                    rd_cnt <= not rd_cnt;
                end if;
            end if;
        end if;
 
        if ( (reset_ifclk = '0') and (USB_DI_ready = '1') and (EMPTY = '0') and (rd_cnt = '0')) then
            RDEN <= '1';
        else
            RDEN <= '0';
        end if;
 
        -- data source
        if ( reset_ifclk = '1' ) then
            in_data <= (others => '0');
            in_valid <= '0';
            wr_cnt <= (others => '0');
            test_cnt <=(others => '0');
            test_cs <= conv_std_logic_vector(47,14);
            WREN <= '0';
            clk_div <= "11";
        else
            if ( FULL = '0' ) then
                if ( in_valid = '1' ) then
                    DI <= in_data;
                end if;
                if ( mode_buf = "00" ) then
                    if ( USB_DO_valid = '1' ) then
                        in_data <= USB_DO & in_data(31  downto 16);
                        in_valid <= wr_cnt(0);
                        wr_cnt <= wr_cnt + 1;
                    else
                        in_valid <= '0';
                    end if;
                else
                    if ( clk_div = "00" ) then
                        if ( ( wr_cnt = "1111"  )  ) then
                            test_cs <= conv_std_logic_vector(47,14);
                            in_data(30 downto 24) <= test_cs(6 downto 0) xor test_cs(13 downto 7);
                        else
                            test_cnt <= test_cnt + conv_std_logic_vector(111,7);
                            test_cs <= test_cs + ( test_sync & test_cnt );
                            in_data(30 downto 24 ) <= test_cnt;
                        end if;
                        in_data(31) <= test_sync;
                        in_data(23 downto 0) <= in_data(31 downto 8);
                        in_valid <= wr_cnt(0) and wr_cnt(1);
                        wr_cnt <= wr_cnt + 1;
                    else
                        in_valid <= '0';
                    end if;
                end if;
                if ( (mode_buf = "01") or ( (mode_buf = "11") and (SW8='1') ) ) then
                    clk_div <= "00";
                else
                    clk_div <= clk_div + 1;
                end if;
            end if;
        end if;
        if ( (reset_ifclk ='0') and (in_valid = '1') and (FULL='0') ) then
            WREN <='1';
        else
            WREN <='0';
        end if;
        mode_buf <= mode;
    end process dpifclk;
 
end RTL;
 

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Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.04b/] [memfifo.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ZTEX	`library ieee;`
2			`use IEEE.std_logic_1164.all;`
3			`use IEEE.std_logic_arith.all;`
4			`use IEEE.std_logic_unsigned.all;`
5			`Library UNISIM;`
6			`use UNISIM.vcomponents.all;`
7
8			`--`
9			`-- Top level module: glues everything together.`
10			`--`
11
12			`entity memfifo is`
13			`port (`
14			`fxclk_in : in std_logic;`
15			`ifclk_in : in std_logic;`
16			`reset : in std_logic;`
17			`mode : in std_logic_vector(1 downto 0);`
18			`-- debug`
19			`led1 : out std_logic_vector(9 downto 0);`
20			`led2 : out std_logic_vector(13 downto 0);`
21			`SW8 : in std_logic;`
22			`SW10 : in std_logic;`
23			`-- ddr pins`
24			`ddr_dram_dq : inout std_logic_vector(15 downto 0);`
25			`ddr_rzq : inout std_logic;`
26			`ddr_zio : inout std_logic;`
27			`ddr_dram_udqs : inout std_logic;`
28			`ddr_dram_dqs : inout std_logic;`
29			`ddr_dram_a : out std_logic_vector(12 downto 0);`
30			`ddr_dram_ba : out std_logic_vector(1 downto 0);`
31			`ddr_dram_cke : out std_logic;`
32			`ddr_dram_ras_n : out std_logic;`
33			`ddr_dram_cas_n : out std_logic;`
34			`ddr_dram_we_n : out std_logic;`
35			`ddr_dram_dm : out std_logic;`
36			`ddr_dram_udm : out std_logic;`
37			`ddr_dram_ck : out std_logic;`
38			`ddr_dram_ck_n : out std_logic;`
39			`-- ez-usb`
40			`fd : inout std_logic_vector(15 downto 0);`
41			`SLWR : out std_logic;`
42			`SLRD : out std_logic;`
43			`SLOE : out std_logic;`
44			`FIFOADDR0 : out std_logic;`
45			`FIFOADDR1 : out std_logic;`
46			`PKTEND : out std_logic;`
47			`FLAGA : in std_logic;`
48			`FLAGB : in std_logic`
49			`);`
50			`end memfifo;`
51
52
53			`architecture RTL of memfifo is`
54
55			`component dram_fifo`
56			`generic (`
57			`CLKOUT_DIVIDE : INTEGER := 2 -- (2, 4, 8, 16, 32), see clkout`
58			`);`
59			`port (`
60			`fxclk_in : in std_logic; -- 48 MHz input clock pin`
61			`reset : in std_logic; -- reset in`
62			`reset_out : out std_logic; -- reset output`
63			`clkout : out std_logic; -- clock output 200MHz/CLKOUT_DIVIDE`
64			`-- ddr pins`
65			`ddr_dram_dq : inout std_logic_vector(15 downto 0);`
66			`ddr_rzq : inout std_logic;`
67			`ddr_zio : inout std_logic;`
68			`ddr_dram_udqs : inout std_logic;`
69			`ddr_dram_dqs : inout std_logic;`
70			`ddr_dram_a : out std_logic_vector(12 downto 0);`
71			`ddr_dram_ba : out std_logic_vector(1 downto 0);`
72			`ddr_dram_cke : out std_logic;`
73			`ddr_dram_ras_n : out std_logic;`
74			`ddr_dram_cas_n : out std_logic;`
75			`ddr_dram_we_n : out std_logic;`
76			`ddr_dram_dm : out std_logic;`
77			`ddr_dram_udm : out std_logic;`
78			`ddr_dram_ck : out std_logic;`
79			`ddr_dram_ck_n : out std_logic;`
80
81			`-- FIFO protocol equal to FWFT FIFO in "7 Series Memory Resources" user guide (ug743)`
82			`-- input fifo interface`
83			`DI : in std_logic_vector(31 downto 0); -- must be hold while FULL is asserted`
84			`FULL : out std_logic; -- 1-bit output: Full flag`
85			`WRERR : out std_logic; -- 1-bit output: Write error`
86			`WRCLK : in std_logic; -- 1-bit input: Rising edge write clock.`
87			`WREN : in std_logic; -- 1-bit input: Write enable`
88
89			`-- output fifo interface`
90			`DO : out std_logic_vector(31 downto 0);`
91			`EMPTY : out std_logic; -- 1-bit output: Empty flag, can be used as data valid indicator`
92			`RDERR : out std_logic; -- 1-bit output: Read error`
93			`RDCLK : in std_logic; -- 1-bit input: Read clock`
94			`RDEN : in std_logic; -- 1-bit input: Read enable`
95
96			`-- free memory`
97			`mem_free_out : out std_logic_vector(17 downto 0);`
98
99			`-- for debugging`
100			`status : out std_logic_vector(9 downto 0)`
101			`);`
102			`end component;`
103
104			`component ezusb_io`
105			`generic (`
106			`OUTEP : INTEGER := 2; -- EP for FPGA -> EZ-USB transfers`
107			`INEP : INTEGER := 6 -- EP for EZ-USB -> FPGA transfers`
108			`);`
109			`port (`
110			`ifclk : out std_logic;`
111			`reset : in std_logic; -- asynchronous reset input`
112			`reset_out : out std_logic; -- synchronous reset output`
113			`-- pins`
114			`ifclk_in : in std_logic;`
115			`fd : inout std_logic_vector(15 downto 0);`
116			`SLWR : out std_logic;`
117			`PKTEND : out std_logic;`
118			`SLRD : out std_logic;`
119			`SLOE : out std_logic;`
120			`FIFOADDR : out std_logic_vector(1 downto 0);`
121			`EMPTY_FLAG : in std_logic;`
122			`FULL_FLAG : in std_logic;`
123			`-- signals for FPGA -> EZ-USB transfer`
124			`DI : in std_logic_vector(15 downto 0); -- data written to EZ-USB`
125			`DI_valid : in std_logic; -- 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0`
126			`DI_ready : out std_logic; -- 1 if new data are accepted`
127			`DI_enable : in std_logic; -- setting to 0 disables FPGA -> EZ-USB transfers`
128			`pktend_timeout : in std_logic_vector(15 downto 0); -- timeout in multiples of 65536 clocks before a short packet committed`
129			`-- setting to 0 disables this feature`
130			`-- signals for EZ-USB -> FPGA transfer`
131			`DO : out std_logic_vector(15 downto 0); -- data read from EZ-USB`
132			`DO_valid : out std_logic; -- 1 indicated valid data`
133			`DO_ready : in std_logic; -- setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0`
134			`-- set to 0 to disable data reads`
135			`-- debug output`
136			`status : out std_logic_vector(3 downto 0)`
137			`);`
138			`end component;`
139
140
141			`signal reset2 : std_logic;`
142			`signal reset_mem : std_logic;`
143			`signal reset_usb : std_logic;`
144			`signal ifclk : std_logic;`
145			`signal reset_ifclk : std_logic;`
146			`signal mem_free : std_logic_vector(17 downto 0);`
147			`signal status : std_logic_vector(9 downto 0);`
148			`signal if_status : std_logic_vector(3 downto 0);`
149			`signal mode_buf : std_logic_vector(1 downto 0);`
150
151			`-- input fifo`
152			`signal DI : std_logic_vector(31 downto 0);`
153			`signal FULL : std_logic;`
154			`signal WRERR : std_logic;`
155			`signal USB_DO_valid : std_logic;`
156			`signal DO_ready : std_logic;`
157			`signal WREN : std_logic;`
158			`signal wrerr_buf : std_logic;`
159			`signal USB_DO : std_logic_vector(15 downto 0);`
160			`signal in_data : std_logic_vector(31 downto 0);`
161			`signal wr_cnt : std_logic_vector(3 downto 0);`
162			`signal test_cnt : std_logic_vector(6 downto 0);`
163			`signal test_cs : std_logic_vector(13 downto 0);`
164			`signal in_valid : std_logic;`
165			`signal test_sync : std_logic;`
166			`signal clk_div : std_logic_vector(1 downto 0);`
167
168			`-- output fifo`
169			`signal DO : std_logic_vector(31 downto 0);`
170			`signal EMPTY : std_logic;`
171			`signal RDERR : std_logic;`
172			`signal USB_DI_ready : std_logic;`
173			`signal RDEN : std_logic;`
174			`signal rderr_buf : std_logic;`
175			`signal USB_DI_valid : std_logic;`
176			`signal rd_buf : std_logic_vector(31 downto 0);`
177			`signal rd_cnt : std_logic;`
178
179
180			`begin`
181			`dram_fifo_inst : dram_fifo`
182			`port map (`
183			`fxclk_in => fxclk_in, -- 48 MHz input clock pin`
184			`reset => reset2, -- reset in`
185			`reset_out => reset_mem, -- reset output`
186			`clkout => open, -- clock output 200MHz/CLKOUT_DIVIDE`
187			`-- ddr pins`
188			`ddr_dram_dq => ddr_dram_dq,`
189			`ddr_rzq => ddr_rzq,`
190			`ddr_zio => ddr_zio,`
191			`ddr_dram_udqs => ddr_dram_udqs,`
192			`ddr_dram_dqs => ddr_dram_dqs,`
193			`ddr_dram_a => ddr_dram_a,`
194			`ddr_dram_ba => ddr_dram_ba,`
195			`ddr_dram_cke => ddr_dram_cke,`
196			`ddr_dram_ras_n => ddr_dram_ras_n,`
197			`ddr_dram_cas_n => ddr_dram_cas_n,`
198			`ddr_dram_we_n => ddr_dram_we_n,`
199			`ddr_dram_dm => ddr_dram_dm,`
200			`ddr_dram_udm => ddr_dram_udm,`
201			`ddr_dram_ck => ddr_dram_ck,`
202			`ddr_dram_ck_n => ddr_dram_ck_n,`
203			`-- input fifo interface, see "7 Series Memory Resources" user guide (ug743)`
204			`DI => DI,`
205			`FULL => FULL, -- 1-bit output: Full flag`
206			`WRERR => WRERR, -- 1-bit output: Write error`
207			`WREN => WREN, -- 1-bit input: Write enable`
208			`WRCLK => ifclk, -- 1-bit input: Rising edge write clock.`
209			`-- output fifo interface, see "7 Series Memory Resources" user guide (ug743)`
210			`DO => DO,`
211			`EMPTY => EMPTY, -- 1-bit output: Empty flag`
212			`RDERR => RDERR, -- 1-bit output: Read error`
213			`RDCLK => ifclk, -- 1-bit input: Read clock`
214			`RDEN => RDEN, -- 1-bit input: Read enable`
215			`-- free memory`
216			`mem_free_out => mem_free,`
217			`-- for debugging`
218			`status => status`
219			`);`
220
221			`ezusb_io_inst : ezusb_io`
222			`generic map (`
223			`OUTEP => 2, -- EP for FPGA -> EZ-USB transfers`
224			`INEP => 6 -- EP for EZ-USB -> FPGA transfers`
225			`)`
226			`port map (`
227			`ifclk => ifclk,`
228			`reset => reset, -- asynchronous reset input`
229			`reset_out => reset_usb, -- synchronous reset output`
230			`-- pins`
231			`ifclk_in => ifclk_in,`
232			`fd => fd,`
233			`SLWR => SLWR,`
234			`SLRD => SLRD,`
235			`SLOE => SLOE,`
236			`PKTEND => PKTEND,`
237			`FIFOADDR(0)=> FIFOADDR0,`
238			`FIFOADDR(1)=> FIFOADDR1,`
239			`EMPTY_FLAG => FLAGA,`
240			`FULL_FLAG => FLAGB,`
241			`-- signals for FPGA -> EZ-USB transfer`
242			`DI => rd_buf(15 downto 0), -- data written to EZ-USB`
243			`DI_valid => USB_DI_valid, -- 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0`
244			`DI_ready => USB_DI_ready, -- 1 if new data are accepted`
245			`DI_enable => '1', -- setting to 0 disables FPGA -> EZ-USB transfers`
246			`pktend_timeout => conv_std_logic_vector(90,16), -- timeout in multiples of 65536 clocks (approx. 0.1s @ 48 MHz) before a short packet committed`
247			`-- setting to 0 disables this feature`
248			`-- signals for EZ-USB -> FPGA transfer`
249			`DO => USB_DO, -- data read from EZ-USB`
250			`DO_valid => USB_DO_valid, -- 1 indicated valid data`
251			`DO_ready => DO_ready, -- setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0`
252			`-- debug output`
253			`status => if_status`
254			`);`
255
256			`reset2 <= reset or reset_usb;`
257			`DO_ready <= '1' when ( (mode_buf="00") and (reset_ifclk='0') and (FULL='0') ) else '0';`
258
259			`-- debug board LEDs`
260			`led1 <= status when (SW10='1') else (EMPTY & FULL & wrerr_buf & rderr_buf & if_status & FLAGB & FLAGA);`
261
262			`led2(0) <= '1' when mem_free(17 downto 13) = conv_std_logic_vector(31,5) else '0';`
263			`led2(1) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(30,5) else '0';`
264			`led2(2) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(27,5) else '0';`
265			`led2(3) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(25,5) else '0';`
266			`led2(4) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(22,5) else '0';`
267			`led2(5) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(20,5) else '0';`
268			`led2(6) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(17,5) else '0';`
269			`led2(7) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(15,5) else '0';`
270			`led2(8) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(12,5) else '0';`
271			`led2(9) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(10,5) else '0';`
272			`led2(10) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(7,5) else '0';`
273			`led2(11) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(5,5) else '0';`
274			`led2(12) <= '1' when mem_free(17 downto 13) < conv_std_logic_vector(2,5) else '0';`
275			`led2(13) <= '1' when mem_free = conv_std_logic_vector(0,18) else '0';`
276
277			`test_sync <= '1' when ( (wr_cnt="1110") or (wr_cnt(0)='1') ) else '0';`
278
279			`dpifclk: process`
280			`begin`
281			`wait until ( ifclk'EVENT and (ifclk = '1') );`
282
283			`-- reset`
284			`reset_ifclk <= (reset or reset_usb) or reset_mem;`
285			`if ( reset_ifclk = '1' ) then`
286			`rderr_buf <= '0';`
287			`wrerr_buf <= '0';`
288			`else`
289			`rderr_buf <= rderr_buf or RDERR;`
290			`wrerr_buf <= wrerr_buf or WRERR;`
291			`end if;`
292
293			`-- FPGA -> EZ-USB FIFO`
294			`if ( reset_ifclk = '1' ) then`
295			`rd_cnt <= '0';`
296			`USB_DI_valid <= '0';`
297			`else`
298			`if ( USB_DI_ready = '1' ) then`
299			`USB_DI_valid <= not EMPTY;`
300			`if ( EMPTY = '0' ) then`
301			`if ( rd_cnt = '0' ) then`
302			`rd_buf <= DO;`
303			`else`
304			`rd_buf(15 downto 0) <= rd_buf(31 downto 16);`
305			`end if;`
306			`rd_cnt <= not rd_cnt;`
307			`end if;`
308			`end if;`
309			`end if;`
310
311			`if ( (reset_ifclk = '0') and (USB_DI_ready = '1') and (EMPTY = '0') and (rd_cnt = '0')) then`
312			`RDEN <= '1';`
313			`else`
314			`RDEN <= '0';`
315			`end if;`
316
317			`-- data source`
318			`if ( reset_ifclk = '1' ) then`
319			`in_data <= (others => '0');`
320			`in_valid <= '0';`
321			`wr_cnt <= (others => '0');`
322			`test_cnt <=(others => '0');`
323			`test_cs <= conv_std_logic_vector(47,14);`
324			`WREN <= '0';`
325			`clk_div <= "11";`
326			`else`
327			`if ( FULL = '0' ) then`
328			`if ( in_valid = '1' ) then`
329			`DI <= in_data;`
330			`end if;`
331			`if ( mode_buf = "00" ) then`
332			`if ( USB_DO_valid = '1' ) then`
333			`in_data <= USB_DO & in_data(31 downto 16);`
334			`in_valid <= wr_cnt(0);`
335			`wr_cnt <= wr_cnt + 1;`
336			`else`
337			`in_valid <= '0';`
338			`end if;`
339			`else`
340			`if ( clk_div = "00" ) then`
341			`if ( ( wr_cnt = "1111" ) ) then`
342			`test_cs <= conv_std_logic_vector(47,14);`
343			`in_data(30 downto 24) <= test_cs(6 downto 0) xor test_cs(13 downto 7);`
344			`else`
345			`test_cnt <= test_cnt + conv_std_logic_vector(111,7);`
346			`test_cs <= test_cs + ( test_sync & test_cnt );`
347			`in_data(30 downto 24 ) <= test_cnt;`
348			`end if;`
349			`in_data(31) <= test_sync;`
350			`in_data(23 downto 0) <= in_data(31 downto 8);`
351			`in_valid <= wr_cnt(0) and wr_cnt(1);`
352			`wr_cnt <= wr_cnt + 1;`
353			`else`
354			`in_valid <= '0';`
355			`end if;`
356			`end if;`
357			`if ( (mode_buf = "01") or ( (mode_buf = "11") and (SW8='1') ) ) then`
358			`clk_div <= "00";`
359			`else`
360			`clk_div <= clk_div + 1;`
361			`end if;`
362			`end if;`
363			`end if;`
364			`if ( (reset_ifclk ='0') and (in_valid = '1') and (FULL='0') ) then`
365			`WREN <='1';`
366			`else`
367			`WREN <='0';`
368			`end if;`
369			`mode_buf <= mode;`
370			`end process dpifclk;`
371
372			`end RTL;`
373