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ZTEX |
############################################################################
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## Memory Controller 3
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## Memory Device: DDR_SDRAM->MT46V32M16XX-5B-IT
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## Frequency: 200 MHz
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## Time Period: 5000 ps
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## Supported Part Numbers: MT46V32M16BN-5B-IT
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############################################################################
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############################################################################
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## I/O TERMINATION
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############################################################################
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NET "ddr_dram_dq[*]" IN_TERM = UNTUNED_SPLIT_50;
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NET "ddr_dram_dqs" IN_TERM = UNTUNED_SPLIT_50;
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NET "ddr_dram_udqs" IN_TERM = UNTUNED_SPLIT_50;
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NET "ddr_dram_a[*]" OUT_TERM = UNTUNED_50;
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NET "ddr_dram_ba[*]" OUT_TERM = UNTUNED_50;
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NET "ddr_dram_ck" OUT_TERM = UNTUNED_50;
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NET "ddr_dram_ck_n" OUT_TERM = UNTUNED_50;
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NET "ddr_dram_cke" OUT_TERM = UNTUNED_50;
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NET "ddr_dram_ras_n" OUT_TERM = UNTUNED_50;
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NET "ddr_dram_cas_n" OUT_TERM = UNTUNED_50;
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NET "ddr_dram_we_n" OUT_TERM = UNTUNED_50;
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NET "ddr_dram_dm" OUT_TERM = UNTUNED_50;
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NET "ddr_dram_udm" OUT_TERM = UNTUNED_50;
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############################################################################
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# I/O STANDARDS
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############################################################################
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NET "ddr_dram_dq[*]" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_dqs" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_udqs" IOSTANDARD = SSTL2_II;
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NET "ddr_rzq" IOSTANDARD = SSTL2_II;
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NET "ddr_zio" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_a[*]" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_ba[*]" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_ck" IOSTANDARD = DIFF_SSTL2_II;
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NET "ddr_dram_ck_n" IOSTANDARD = DIFF_SSTL2_II;
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NET "ddr_dram_cke" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_ras_n" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_cas_n" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_we_n" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_dm" IOSTANDARD = SSTL2_II;
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NET "ddr_dram_udm" IOSTANDARD = SSTL2_II;
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############################################################################
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# MCB 3
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# Pin Location Constraints for Clock, Masks, Address, and Controls
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############################################################################
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NET "ddr_dram_dq[4]" LOC = "F2" ;
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NET "ddr_dram_dq[5]" LOC = "F1" ;
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NET "ddr_dram_dq[6]" LOC = "G3" ;
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NET "ddr_dram_dq[7]" LOC = "G1" ;
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NET "ddr_dram_dq[2]" LOC = "J3" ;
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NET "ddr_dram_dq[3]" LOC = "J1" ;
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NET "ddr_dram_dq[0]" LOC = "K2" ;
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NET "ddr_dram_dq[1]" LOC = "K1" ;
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NET "ddr_dram_dq[8]" LOC = "L3" ;
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NET "ddr_dram_dq[9]" LOC = "L1" ;
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NET "ddr_dram_dq[10]" LOC = "M2" ;
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NET "ddr_dram_dq[11]" LOC = "M1" ;
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NET "ddr_dram_dq[12]" LOC = "P2" ;
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NET "ddr_dram_dq[13]" LOC = "P1" ;
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NET "ddr_dram_dq[14]" LOC = "R2" ;
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NET "ddr_dram_dq[15]" LOC = "R1" ;
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NET "ddr_dram_dqs" LOC = "H2" ;
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NET "ddr_dram_udqs" LOC = "N3" ;
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NET "ddr_dram_ba[0]" LOC = "C3" ;
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NET "ddr_dram_ba[1]" LOC = "C2" ;
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NET "ddr_dram_a[0]" LOC = "K5" ;
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NET "ddr_dram_a[1]" LOC = "K6" ;
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NET "ddr_dram_a[2]" LOC = "D1" ;
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NET "ddr_dram_a[3]" LOC = "L4" ;
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NET "ddr_dram_a[4]" LOC = "G5" ;
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NET "ddr_dram_a[5]" LOC = "H4" ;
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NET "ddr_dram_a[6]" LOC = "H3" ;
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NET "ddr_dram_a[7]" LOC = "D3" ;
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NET "ddr_dram_a[8]" LOC = "B2" ;
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NET "ddr_dram_a[9]" LOC = "A2" ;
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NET "ddr_dram_a[10]" LOC = "G6" ;
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NET "ddr_dram_a[11]" LOC = "E3" ;
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NET "ddr_dram_a[12]" LOC = "F3" ;
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NET "ddr_dram_dm" LOC = "J4" ;
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NET "ddr_dram_udm" LOC = "K3" ;
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NET "ddr_dram_ras_n" LOC = "J6" ;
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NET "ddr_dram_cas_n" LOC = "H5" ;
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NET "ddr_dram_we_n" LOC = "C1" ;
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NET "ddr_dram_ck" LOC = "E2" ;
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NET "ddr_dram_ck_n" LOC = "E1" ;
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NET "ddr_dram_cke" LOC = "F4" ;
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# NC pins
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NET "ddr_rzq" LOC = "M4" ;
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NET "ddr_zio" LOC = "M5" ;
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NET "*memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
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NET "*c?_pll_lock" TIG;
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INST "*memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
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#Please uncomment the below TIG if used in a design which enables self-refresh mode
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#NET "*memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
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