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ZTEX |
##################################################################################################
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##
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## Xilinx, Inc. 2010 www.xilinx.com
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## Mi. Mrz 2 01:33:28 2016
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## Generated by MIG Version 2.3
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##
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##################################################################################################
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## File name : mig_7series_0.sdc
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## Details : Constraints file
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## FPGA Family: ARTIX7
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## FPGA Part: XC7A75TCSG324_PKG
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## Speedgrade: -2
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## Design Entry: VERILOG
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## Frequency: 0 MHz
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## Time Period: 2500 ps
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##################################################################################################
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##################################################################################################
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## Controller 0
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## Memory Device: DDR3_SDRAM->Components->MT41J128M16XX-125
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## Data Width: 16
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## Time Period: 2500
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## Data Mask: 1
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##################################################################################################
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#create_clock -period 2.5 [get_ports sys_clk_i]
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#set_propagated_clock sys_clk_i
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#create_clock -period 5 [get_ports clk_ref_i]
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#set_propagated_clock clk_ref_i
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############## NET - IOSTANDARD ##################
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# PadFunction: IO_L17P_T2_35
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set_property SLEW FAST [get_ports {ddr3_dq[0]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
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set_property PACKAGE_PIN H1 [get_ports {ddr3_dq[0]}]
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# PadFunction: IO_L18P_T2_35
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set_property SLEW FAST [get_ports {ddr3_dq[1]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
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set_property PACKAGE_PIN F1 [get_ports {ddr3_dq[1]}]
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# PadFunction: IO_L14P_T2_SRCC_35
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set_property SLEW FAST [get_ports {ddr3_dq[2]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
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set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[2]}]
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# PadFunction: IO_L18N_T2_35
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set_property SLEW FAST [get_ports {ddr3_dq[3]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
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set_property PACKAGE_PIN E1 [get_ports {ddr3_dq[3]}]
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# PadFunction: IO_L13P_T2_MRCC_35
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set_property SLEW FAST [get_ports {ddr3_dq[4]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
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set_property PACKAGE_PIN F4 [get_ports {ddr3_dq[4]}]
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# PadFunction: IO_L16N_T2_35
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set_property SLEW FAST [get_ports {ddr3_dq[5]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
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set_property PACKAGE_PIN C1 [get_ports {ddr3_dq[5]}]
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# PadFunction: IO_L13N_T2_MRCC_35
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set_property SLEW FAST [get_ports {ddr3_dq[6]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
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set_property PACKAGE_PIN F3 [get_ports {ddr3_dq[6]}]
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# PadFunction: IO_L14N_T2_SRCC_35
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set_property SLEW FAST [get_ports {ddr3_dq[7]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
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set_property PACKAGE_PIN D2 [get_ports {ddr3_dq[7]}]
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# PadFunction: IO_L20P_T3_35
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set_property SLEW FAST [get_ports {ddr3_dq[8]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
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set_property PACKAGE_PIN G4 [get_ports {ddr3_dq[8]}]
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# PadFunction: IO_L24N_T3_35
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set_property SLEW FAST [get_ports {ddr3_dq[9]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
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set_property PACKAGE_PIN H5 [get_ports {ddr3_dq[9]}]
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# PadFunction: IO_L20N_T3_35
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set_property SLEW FAST [get_ports {ddr3_dq[10]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
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set_property PACKAGE_PIN G3 [get_ports {ddr3_dq[10]}]
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# PadFunction: IO_L24P_T3_35
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set_property SLEW FAST [get_ports {ddr3_dq[11]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
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set_property PACKAGE_PIN H6 [get_ports {ddr3_dq[11]}]
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# PadFunction: IO_L22N_T3_35
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set_property SLEW FAST [get_ports {ddr3_dq[12]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
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set_property PACKAGE_PIN J2 [get_ports {ddr3_dq[12]}]
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# PadFunction: IO_L22P_T3_35
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set_property SLEW FAST [get_ports {ddr3_dq[13]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
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set_property PACKAGE_PIN J3 [get_ports {ddr3_dq[13]}]
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# PadFunction: IO_L23N_T3_35
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set_property SLEW FAST [get_ports {ddr3_dq[14]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
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set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[14]}]
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# PadFunction: IO_L23P_T3_35
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set_property SLEW FAST [get_ports {ddr3_dq[15]}]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
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set_property PACKAGE_PIN K2 [get_ports {ddr3_dq[15]}]
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# PadFunction: IO_L2P_T0_AD12P_35
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set_property SLEW FAST [get_ports {ddr3_addr[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
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set_property PACKAGE_PIN B7 [get_ports {ddr3_addr[13]}]
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# PadFunction: IO_L10P_T1_AD15P_35
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set_property SLEW FAST [get_ports {ddr3_addr[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
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set_property PACKAGE_PIN B3 [get_ports {ddr3_addr[12]}]
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# PadFunction: IO_L3N_T0_DQS_AD5N_35
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set_property SLEW FAST [get_ports {ddr3_addr[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
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set_property PACKAGE_PIN A5 [get_ports {ddr3_addr[11]}]
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# PadFunction: IO_L10N_T1_AD15N_35
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set_property SLEW FAST [get_ports {ddr3_addr[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
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set_property PACKAGE_PIN B2 [get_ports {ddr3_addr[10]}]
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# PadFunction: IO_L4P_T0_35
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set_property SLEW FAST [get_ports {ddr3_addr[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
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set_property PACKAGE_PIN D8 [get_ports {ddr3_addr[9]}]
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# PadFunction: IO_L3P_T0_DQS_AD5P_35
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set_property SLEW FAST [get_ports {ddr3_addr[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
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set_property PACKAGE_PIN A6 [get_ports {ddr3_addr[8]}]
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# PadFunction: IO_L1P_T0_AD4P_35
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set_property SLEW FAST [get_ports {ddr3_addr[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
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set_property PACKAGE_PIN C6 [get_ports {ddr3_addr[7]}]
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# PadFunction: IO_L8P_T1_AD14P_35
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set_property SLEW FAST [get_ports {ddr3_addr[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
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set_property PACKAGE_PIN A4 [get_ports {ddr3_addr[6]}]
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# PadFunction: IO_L6P_T0_35
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set_property SLEW FAST [get_ports {ddr3_addr[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
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set_property PACKAGE_PIN E7 [get_ports {ddr3_addr[5]}]
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# PadFunction: IO_L8N_T1_AD14N_35
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set_property SLEW FAST [get_ports {ddr3_addr[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
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set_property PACKAGE_PIN A3 [get_ports {ddr3_addr[4]}]
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# PadFunction: IO_L11P_T1_SRCC_35
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set_property SLEW FAST [get_ports {ddr3_addr[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
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set_property PACKAGE_PIN D5 [get_ports {ddr3_addr[3]}]
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# PadFunction: IO_L4N_T0_35
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set_property SLEW FAST [get_ports {ddr3_addr[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
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set_property PACKAGE_PIN C7 [get_ports {ddr3_addr[2]}]
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# PadFunction: IO_L2N_T0_AD12N_35
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set_property SLEW FAST [get_ports {ddr3_addr[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
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set_property PACKAGE_PIN B6 [get_ports {ddr3_addr[1]}]
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# PadFunction: IO_L1N_T0_AD4N_35
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set_property SLEW FAST [get_ports {ddr3_addr[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
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set_property PACKAGE_PIN C5 [get_ports {ddr3_addr[0]}]
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# PadFunction: IO_L5P_T0_AD13P_35
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set_property SLEW FAST [get_ports {ddr3_ba[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
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set_property PACKAGE_PIN E6 [get_ports {ddr3_ba[2]}]
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| 206 |
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# PadFunction: IO_L9N_T1_DQS_AD7N_35
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set_property SLEW FAST [get_ports {ddr3_ba[1]}]
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| 208 |
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
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| 209 |
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set_property PACKAGE_PIN A1 [get_ports {ddr3_ba[1]}]
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| 210 |
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| 211 |
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# PadFunction: IO_L5N_T0_AD13N_35
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| 212 |
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set_property SLEW FAST [get_ports {ddr3_ba[0]}]
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| 213 |
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
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| 214 |
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set_property PACKAGE_PIN E5 [get_ports {ddr3_ba[0]}]
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| 216 |
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# PadFunction: IO_L12P_T1_MRCC_35
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| 217 |
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set_property SLEW FAST [get_ports {ddr3_ras_n}]
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| 218 |
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
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| 219 |
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set_property PACKAGE_PIN E3 [get_ports {ddr3_ras_n}]
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| 220 |
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| 221 |
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# PadFunction: IO_L12N_T1_MRCC_35
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| 222 |
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set_property SLEW FAST [get_ports {ddr3_cas_n}]
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| 223 |
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
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| 224 |
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set_property PACKAGE_PIN D3 [get_ports {ddr3_cas_n}]
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| 225 |
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| 226 |
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# PadFunction: IO_L11N_T1_SRCC_35
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| 227 |
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set_property SLEW FAST [get_ports {ddr3_we_n}]
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| 228 |
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
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| 229 |
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set_property PACKAGE_PIN D4 [get_ports {ddr3_we_n}]
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| 230 |
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| 231 |
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# PadFunction: IO_25_35
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| 232 |
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set_property SLEW FAST [get_ports {ddr3_reset_n}]
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| 233 |
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set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]
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| 234 |
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set_property PACKAGE_PIN J5 [get_ports {ddr3_reset_n}]
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| 235 |
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| 236 |
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# PadFunction: IO_L9P_T1_DQS_AD7P_35
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| 237 |
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set_property SLEW FAST [get_ports {ddr3_cke[0]}]
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| 238 |
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
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| 239 |
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set_property PACKAGE_PIN B1 [get_ports {ddr3_cke[0]}]
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| 240 |
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| 241 |
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# PadFunction: IO_0_35
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| 242 |
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set_property SLEW FAST [get_ports {ddr3_odt[0]}]
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| 243 |
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
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| 244 |
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set_property PACKAGE_PIN F5 [get_ports {ddr3_odt[0]}]
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| 245 |
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| 246 |
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# PadFunction: IO_L17N_T2_35
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| 247 |
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set_property SLEW FAST [get_ports {ddr3_dm[0]}]
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| 248 |
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
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| 249 |
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set_property PACKAGE_PIN G1 [get_ports {ddr3_dm[0]}]
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| 250 |
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| 251 |
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# PadFunction: IO_L19P_T3_35
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| 252 |
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set_property SLEW FAST [get_ports {ddr3_dm[1]}]
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| 253 |
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
|
| 254 |
|
|
set_property PACKAGE_PIN G6 [get_ports {ddr3_dm[1]}]
|
| 255 |
|
|
|
| 256 |
|
|
# PadFunction: IO_L15P_T2_DQS_35
|
| 257 |
|
|
set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
|
| 258 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[0]}]
|
| 259 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]
|
| 260 |
|
|
set_property PACKAGE_PIN H2 [get_ports {ddr3_dqs_p[0]}]
|
| 261 |
|
|
|
| 262 |
|
|
# PadFunction: IO_L15N_T2_DQS_35
|
| 263 |
|
|
set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
|
| 264 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[0]}]
|
| 265 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
|
| 266 |
|
|
set_property PACKAGE_PIN G2 [get_ports {ddr3_dqs_n[0]}]
|
| 267 |
|
|
|
| 268 |
|
|
# PadFunction: IO_L21P_T3_DQS_35
|
| 269 |
|
|
set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
|
| 270 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_p[1]}]
|
| 271 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]
|
| 272 |
|
|
set_property PACKAGE_PIN J4 [get_ports {ddr3_dqs_p[1]}]
|
| 273 |
|
|
|
| 274 |
|
|
# PadFunction: IO_L21N_T3_DQS_35
|
| 275 |
|
|
set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
|
| 276 |
|
|
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddr3_dqs_n[1]}]
|
| 277 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
|
| 278 |
|
|
set_property PACKAGE_PIN H4 [get_ports {ddr3_dqs_n[1]}]
|
| 279 |
|
|
|
| 280 |
|
|
# PadFunction: IO_L7P_T1_AD6P_35
|
| 281 |
|
|
set_property SLEW FAST [get_ports {ddr3_ck_p[0]}]
|
| 282 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p[0]}]
|
| 283 |
|
|
set_property PACKAGE_PIN C4 [get_ports {ddr3_ck_p[0]}]
|
| 284 |
|
|
|
| 285 |
|
|
# PadFunction: IO_L7N_T1_AD6N_35
|
| 286 |
|
|
set_property SLEW FAST [get_ports {ddr3_ck_n[0]}]
|
| 287 |
|
|
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n[0]}]
|
| 288 |
|
|
set_property PACKAGE_PIN B4 [get_ports {ddr3_ck_n[0]}]
|
| 289 |
|
|
|
| 290 |
|
|
|
| 291 |
|
|
|
| 292 |
|
|
set_property LOC PHASER_OUT_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
|
| 293 |
|
|
set_property LOC PHASER_OUT_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
|
| 294 |
|
|
set_property LOC PHASER_OUT_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
|
| 295 |
|
|
set_property LOC PHASER_OUT_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]
|
| 296 |
|
|
|
| 297 |
|
|
## set_property LOC PHASER_IN_PHY_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
|
| 298 |
|
|
## set_property LOC PHASER_IN_PHY_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
|
| 299 |
|
|
set_property LOC PHASER_IN_PHY_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
|
| 300 |
|
|
set_property LOC PHASER_IN_PHY_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]
|
| 301 |
|
|
|
| 302 |
|
|
|
| 303 |
|
|
|
| 304 |
|
|
set_property LOC OUT_FIFO_X1Y11 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
|
| 305 |
|
|
set_property LOC OUT_FIFO_X1Y10 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
|
| 306 |
|
|
set_property LOC OUT_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
|
| 307 |
|
|
set_property LOC OUT_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]
|
| 308 |
|
|
|
| 309 |
|
|
set_property LOC IN_FIFO_X1Y9 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]
|
| 310 |
|
|
set_property LOC IN_FIFO_X1Y8 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]
|
| 311 |
|
|
|
| 312 |
|
|
set_property LOC PHY_CONTROL_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]
|
| 313 |
|
|
|
| 314 |
|
|
set_property LOC PHASER_REF_X1Y2 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]
|
| 315 |
|
|
|
| 316 |
|
|
set_property LOC OLOGIC_X1Y119 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]
|
| 317 |
|
|
set_property LOC OLOGIC_X1Y107 [get_cells -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]
|
| 318 |
|
|
|
| 319 |
|
|
set_property LOC PLLE2_ADV_X1Y2 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]
|
| 320 |
|
|
set_property LOC MMCME2_ADV_X1Y2 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
|
| 324 |
|
|
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
|
| 325 |
|
|
-setup 6
|
| 326 |
|
|
|
| 327 |
|
|
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
|
| 328 |
|
|
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
|
| 329 |
|
|
-hold 5
|
| 330 |
|
|
|
| 331 |
|
|
#set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r*}] \
|
| 332 |
|
|
# -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
|
| 333 |
|
|
# -setup 6
|
| 334 |
|
|
|
| 335 |
|
|
#set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r*}] \
|
| 336 |
|
|
# -to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
|
| 337 |
|
|
# -hold 5
|
| 338 |
|
|
|
| 339 |
|
|
#set_max_delay -from [get_cells -hier -filter {NAME =~ */u_phase_detector && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *pos_edge_samp*}] 2.500000
|
| 340 |
|
|
#set_max_delay -from [get_cells -hier -filter {NAME =~ */u_phase_detector && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *neg_edge_samp*}] 2.500000
|
| 341 |
|
|
|
| 342 |
|
|
set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]
|
| 343 |
|
|
|
| 344 |
|
|
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start
|
| 345 |
|
|
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start
|
| 346 |
|
|
|
| 347 |
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
|
| 348 |
|
|
set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5
|
| 349 |
|
|
#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
|
| 350 |
|
|
#set_max_delay -from [get_cells -hier rstdiv0_sync_r1*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5
|
| 351 |
|
|
|
| 352 |
|
|
set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20
|
| 353 |
|
|
#set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/*rst_r1*}] 20
|
| 354 |
|
|
|
