Subversion Repositories usb_fpga_2_14

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//*****************************************************************************

//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version:%version

//  \   \         Application: MIG

//  /   /         Filename: clk_ibuf.v

// /___/   /\     Date Last Modified: $Date: 2011/06/02 08:34:56 $

// \   \  /  \    Date Created:Mon Aug 3 2009

//  \___\/\___\

//

//Device: Virtex-6

//Design Name: DDR3 SDRAM

//Purpose:

//   Clock generation/distribution and reset synchronization

//Reference:

//Revision History:

//*****************************************************************************

`timescale 1ns/1ps

module mig_7series_v2_3_clk_ibuf #

  (

   parameter SYSCLK_TYPE      = "DIFFERENTIAL",

                                // input clock type

   parameter DIFF_TERM_SYSCLK = "TRUE"

                                // Differential Termination

   )

  (

   // Clock inputs

   input  sys_clk_p,          // System clock diff input

   input  sys_clk_n,

   input  sys_clk_i,

   output mmcm_clk

   );

   (* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;

  generate

    if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk

      //***********************************************************************

      // Differential input clock input buffers

      //***********************************************************************

      IBUFGDS #

        (

         .DIFF_TERM    (DIFF_TERM_SYSCLK),

         .IBUF_LOW_PWR ("FALSE")

         )

        u_ibufg_sys_clk

          (

           .I  (sys_clk_p),

           .IB (sys_clk_n),

           .O  (sys_clk_ibufg)

           );

    end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk

      //***********************************************************************

      // SINGLE_ENDED input clock input buffers

      //***********************************************************************

      IBUFG #

        (

         .IBUF_LOW_PWR ("FALSE")

         )

        u_ibufg_sys_clk

          (

           .I  (sys_clk_i),

           .O  (sys_clk_ibufg)

           );

    end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk

      //***********************************************************************

      // System clock is driven from FPGA internal clock (clock from fabric)

      //***********************************************************************

      assign sys_clk_ibufg = sys_clk_i;

   end

  endgenerate

  assign mmcm_clk = sys_clk_ibufg;

endmodule