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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : bank_cntrl.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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// Structural block instantiating the three sub blocks that make up
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// a bank machine.
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`timescale 1ps/1ps
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module mig_7series_v2_3_bank_cntrl #
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(
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parameter TCQ = 100,
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parameter ADDR_CMD_MODE = "1T",
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parameter BANK_WIDTH = 3,
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parameter BM_CNT_WIDTH = 2,
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parameter BURST_MODE = "8",
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parameter COL_WIDTH = 12,
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parameter CWL = 5,
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parameter DATA_BUF_ADDR_WIDTH = 8,
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parameter DRAM_TYPE = "DDR3",
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parameter ECC = "OFF",
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parameter ID = 4,
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parameter nBANK_MACHS = 4,
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parameter nCK_PER_CLK = 2,
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parameter nOP_WAIT = 0,
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parameter nRAS_CLKS = 10,
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parameter nRCD = 5,
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parameter nRTP = 4,
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parameter nRP = 10,
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parameter nWTP_CLKS = 5,
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parameter ORDERING = "NORM",
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parameter RANK_WIDTH = 2,
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parameter RANKS = 4,
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parameter RAS_TIMER_WIDTH = 5,
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parameter ROW_WIDTH = 16,
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parameter STARVE_LIMIT = 2
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)
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(/*AUTOARG*/
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// Outputs
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wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc,
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row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
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req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
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rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
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ordered_issued, op_exit_req, end_rtp, demand_priority,
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demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
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req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
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rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
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// Inputs
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was_wr, was_priority, use_addr, start_rcd_in,
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size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row,
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req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
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rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
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periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
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order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r,
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maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr,
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rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority,
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dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in,
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data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
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accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full,
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phy_mc_cmd_full, phy_mc_data_full
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input accept_internal_r; // To bank_queue0 of bank_queue.v
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input accept_req; // To bank_queue0 of bank_queue.v
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input adv_order_q; // To bank_queue0 of bank_queue.v
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input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
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input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
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input clk; // To bank_compare0 of bank_compare.v, ...
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input [2:0] cmd; // To bank_compare0 of bank_compare.v
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input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
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input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
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input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
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input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
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input phy_rddata_valid; // To bank_state0 of bank_state.v
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input dq_busy_data; // To bank_state0 of bank_state.v
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input hi_priority; // To bank_compare0 of bank_compare.v
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input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
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input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
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input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v
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input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v
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input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v
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input rnk_config_strobe; // To bank_state0 of bank_state.v
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input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v
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input rnk_config_valid_r; // To bank_state0 of bank_state.v
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input low_idle_cnt_r; // To bank_state0 of bank_state.v
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input maint_idle; // To bank_queue0 of bank_queue.v
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input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
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input maint_req_r; // To bank_queue0 of bank_queue.v
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input maint_zq_r; // To bank_compare0 of bank_compare.v
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input maint_sre_r; // To bank_compare0 of bank_compare.v
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input op_exit_grant; // To bank_state0 of bank_state.v
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input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
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input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
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input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
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input periodic_rd_insert; // To bank_compare0 of bank_compare.v
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input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
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input phy_mc_ctl_full;
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input phy_mc_cmd_full;
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input phy_mc_data_full;
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input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
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input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
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input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
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input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
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input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
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input rd_rmw; // To bank_state0 of bank_state.v
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input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
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input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
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input rst; // To bank_state0 of bank_state.v, ...
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input sending_col; // To bank_compare0 of bank_compare.v, ...
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input sending_row; // To bank_state0 of bank_state.v
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input sending_pre;
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input sent_col; // To bank_state0 of bank_state.v
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input sent_row; // To bank_state0 of bank_state.v
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input size; // To bank_compare0 of bank_compare.v
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input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
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input use_addr; // To bank_queue0 of bank_queue.v
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input was_priority; // To bank_queue0 of bank_queue.v
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input was_wr; // To bank_queue0 of bank_queue.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
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output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
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output col_rdy_wr; // From bank_state0 of bank_state.v
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output demand_act_priority; // From bank_state0 of bank_state.v
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output demand_priority; // From bank_state0 of bank_state.v
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output end_rtp; // From bank_state0 of bank_state.v
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output op_exit_req; // From bank_state0 of bank_state.v
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output ordered_issued; // From bank_queue0 of bank_queue.v
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output ordered_r; // From bank_queue0 of bank_queue.v
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output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
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output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
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output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
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output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
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output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
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output req_cas; // From bank_compare0 of bank_compare.v
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output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
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output req_ras; // From bank_compare0 of bank_compare.v
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output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
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output req_size_r; // From bank_compare0 of bank_compare.v
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output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
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output row_cmd_wr; // From bank_compare0 of bank_compare.v
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output rtc; // From bank_state0 of bank_state.v
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output rts_col; // From bank_state0 of bank_state.v
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output rts_row; // From bank_state0 of bank_state.v
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output rts_pre;
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output start_pre_wait; // From bank_state0 of bank_state.v
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output start_rcd; // From bank_state0 of bank_state.v
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output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire act_wait_r; // From bank_state0 of bank_state.v
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wire allow_auto_pre; // From bank_state0 of bank_state.v
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wire auto_pre_r; // From bank_queue0 of bank_queue.v
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wire bank_wait_in_progress; // From bank_state0 of bank_state.v
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wire order_q_zero; // From bank_queue0 of bank_queue.v
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wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
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wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
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wire pre_wait_r; // From bank_state0 of bank_state.v
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wire precharge_bm_end; // From bank_state0 of bank_state.v
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wire q_has_priority; // From bank_queue0 of bank_queue.v
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wire q_has_rd; // From bank_queue0 of bank_queue.v
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wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
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wire rcv_open_bank; // From bank_queue0 of bank_queue.v
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wire rd_half_rmw; // From bank_state0 of bank_state.v
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wire req_priority_r; // From bank_compare0 of bank_compare.v
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wire row_hit_r; // From bank_compare0 of bank_compare.v
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wire tail_r; // From bank_queue0 of bank_queue.v
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wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
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// End of automatics
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output idle_ns;
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output req_wr_r;
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output rd_wr_r;
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output bm_end;
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output idle_r;
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output head_r;
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output [RANK_WIDTH-1:0] req_rank_r;
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output rb_hit_busy_r;
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output passing_open_bank;
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output maint_hit;
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output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
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mig_7series_v2_3_bank_compare #
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(/*AUTOINSTPARAM*/
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// Parameters
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.BANK_WIDTH (BANK_WIDTH),
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.TCQ (TCQ),
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.BURST_MODE (BURST_MODE),
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.COL_WIDTH (COL_WIDTH),
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.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
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.ECC (ECC),
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.RANK_WIDTH (RANK_WIDTH),
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.RANKS (RANKS),
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.ROW_WIDTH (ROW_WIDTH))
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bank_compare0
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(/*AUTOINST*/
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// Outputs
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| 264 |
|
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.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
|
| 265 |
|
|
.req_periodic_rd_r (req_periodic_rd_r),
|
| 266 |
|
|
.req_size_r (req_size_r),
|
| 267 |
|
|
.rd_wr_r (rd_wr_r),
|
| 268 |
|
|
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
|
| 269 |
|
|
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
|
| 270 |
|
|
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
|
| 271 |
|
|
.req_wr_r (req_wr_r),
|
| 272 |
|
|
.req_priority_r (req_priority_r),
|
| 273 |
|
|
.rb_hit_busy_r (rb_hit_busy_r),
|
| 274 |
|
|
.rb_hit_busy_ns (rb_hit_busy_ns),
|
| 275 |
|
|
.row_hit_r (row_hit_r),
|
| 276 |
|
|
.maint_hit (maint_hit),
|
| 277 |
|
|
.col_addr (col_addr[ROW_WIDTH-1:0]),
|
| 278 |
|
|
.req_ras (req_ras),
|
| 279 |
|
|
.req_cas (req_cas),
|
| 280 |
|
|
.row_cmd_wr (row_cmd_wr),
|
| 281 |
|
|
.row_addr (row_addr[ROW_WIDTH-1:0]),
|
| 282 |
|
|
.rank_busy_r (rank_busy_r[RANKS-1:0]),
|
| 283 |
|
|
// Inputs
|
| 284 |
|
|
.clk (clk),
|
| 285 |
|
|
.idle_ns (idle_ns),
|
| 286 |
|
|
.idle_r (idle_r),
|
| 287 |
|
|
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
|
| 288 |
|
|
.periodic_rd_insert (periodic_rd_insert),
|
| 289 |
|
|
.size (size),
|
| 290 |
|
|
.cmd (cmd[2:0]),
|
| 291 |
|
|
.sending_col (sending_col),
|
| 292 |
|
|
.rank (rank[RANK_WIDTH-1:0]),
|
| 293 |
|
|
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
|
| 294 |
|
|
.bank (bank[BANK_WIDTH-1:0]),
|
| 295 |
|
|
.row (row[ROW_WIDTH-1:0]),
|
| 296 |
|
|
.col (col[COL_WIDTH-1:0]),
|
| 297 |
|
|
.hi_priority (hi_priority),
|
| 298 |
|
|
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
|
| 299 |
|
|
.maint_zq_r (maint_zq_r),
|
| 300 |
|
|
.maint_sre_r (maint_sre_r),
|
| 301 |
|
|
.auto_pre_r (auto_pre_r),
|
| 302 |
|
|
.rd_half_rmw (rd_half_rmw),
|
| 303 |
|
|
.act_wait_r (act_wait_r));
|
| 304 |
|
|
|
| 305 |
|
|
mig_7series_v2_3_bank_state #
|
| 306 |
|
|
(/*AUTOINSTPARAM*/
|
| 307 |
|
|
// Parameters
|
| 308 |
|
|
.TCQ (TCQ),
|
| 309 |
|
|
.ADDR_CMD_MODE (ADDR_CMD_MODE),
|
| 310 |
|
|
.BM_CNT_WIDTH (BM_CNT_WIDTH),
|
| 311 |
|
|
.BURST_MODE (BURST_MODE),
|
| 312 |
|
|
.CWL (CWL),
|
| 313 |
|
|
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
|
| 314 |
|
|
.DRAM_TYPE (DRAM_TYPE),
|
| 315 |
|
|
.ECC (ECC),
|
| 316 |
|
|
.ID (ID),
|
| 317 |
|
|
.nBANK_MACHS (nBANK_MACHS),
|
| 318 |
|
|
.nCK_PER_CLK (nCK_PER_CLK),
|
| 319 |
|
|
.nOP_WAIT (nOP_WAIT),
|
| 320 |
|
|
.nRAS_CLKS (nRAS_CLKS),
|
| 321 |
|
|
.nRP (nRP),
|
| 322 |
|
|
.nRTP (nRTP),
|
| 323 |
|
|
.nRCD (nRCD),
|
| 324 |
|
|
.nWTP_CLKS (nWTP_CLKS),
|
| 325 |
|
|
.ORDERING (ORDERING),
|
| 326 |
|
|
.RANKS (RANKS),
|
| 327 |
|
|
.RANK_WIDTH (RANK_WIDTH),
|
| 328 |
|
|
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
|
| 329 |
|
|
.STARVE_LIMIT (STARVE_LIMIT))
|
| 330 |
|
|
bank_state0
|
| 331 |
|
|
(/*AUTOINST*/
|
| 332 |
|
|
// Outputs
|
| 333 |
|
|
.start_rcd (start_rcd),
|
| 334 |
|
|
.act_wait_r (act_wait_r),
|
| 335 |
|
|
.rd_half_rmw (rd_half_rmw),
|
| 336 |
|
|
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
|
| 337 |
|
|
.end_rtp (end_rtp),
|
| 338 |
|
|
.bank_wait_in_progress (bank_wait_in_progress),
|
| 339 |
|
|
.start_pre_wait (start_pre_wait),
|
| 340 |
|
|
.op_exit_req (op_exit_req),
|
| 341 |
|
|
.pre_wait_r (pre_wait_r),
|
| 342 |
|
|
.allow_auto_pre (allow_auto_pre),
|
| 343 |
|
|
.precharge_bm_end (precharge_bm_end),
|
| 344 |
|
|
.demand_act_priority (demand_act_priority),
|
| 345 |
|
|
.rts_row (rts_row),
|
| 346 |
|
|
.rts_pre (rts_pre),
|
| 347 |
|
|
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
|
| 348 |
|
|
.demand_priority (demand_priority),
|
| 349 |
|
|
.col_rdy_wr (col_rdy_wr),
|
| 350 |
|
|
.rts_col (rts_col),
|
| 351 |
|
|
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
|
| 352 |
|
|
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
|
| 353 |
|
|
// Inputs
|
| 354 |
|
|
.clk (clk),
|
| 355 |
|
|
.rst (rst),
|
| 356 |
|
|
.bm_end (bm_end),
|
| 357 |
|
|
.pass_open_bank_r (pass_open_bank_r),
|
| 358 |
|
|
.sending_row (sending_row),
|
| 359 |
|
|
.sending_pre (sending_pre),
|
| 360 |
|
|
.rcv_open_bank (rcv_open_bank),
|
| 361 |
|
|
.sending_col (sending_col),
|
| 362 |
|
|
.rd_wr_r (rd_wr_r),
|
| 363 |
|
|
.req_wr_r (req_wr_r),
|
| 364 |
|
|
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
|
| 365 |
|
|
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
|
| 366 |
|
|
.phy_rddata_valid (phy_rddata_valid),
|
| 367 |
|
|
.rd_rmw (rd_rmw),
|
| 368 |
|
|
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
|
| 369 |
|
|
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
|
| 370 |
|
|
.idle_r (idle_r),
|
| 371 |
|
|
.passing_open_bank (passing_open_bank),
|
| 372 |
|
|
.low_idle_cnt_r (low_idle_cnt_r),
|
| 373 |
|
|
.op_exit_grant (op_exit_grant),
|
| 374 |
|
|
.tail_r (tail_r),
|
| 375 |
|
|
.auto_pre_r (auto_pre_r),
|
| 376 |
|
|
.pass_open_bank_ns (pass_open_bank_ns),
|
| 377 |
|
|
.phy_mc_cmd_full (phy_mc_cmd_full),
|
| 378 |
|
|
.phy_mc_ctl_full (phy_mc_ctl_full),
|
| 379 |
|
|
.phy_mc_data_full (phy_mc_data_full),
|
| 380 |
|
|
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
|
| 381 |
|
|
.rnk_config_strobe (rnk_config_strobe),
|
| 382 |
|
|
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
|
| 383 |
|
|
.rnk_config_valid_r (rnk_config_valid_r),
|
| 384 |
|
|
.rtc (rtc),
|
| 385 |
|
|
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
|
| 386 |
|
|
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
|
| 387 |
|
|
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
|
| 388 |
|
|
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
|
| 389 |
|
|
.wait_for_maint_r (wait_for_maint_r),
|
| 390 |
|
|
.head_r (head_r),
|
| 391 |
|
|
.sent_row (sent_row),
|
| 392 |
|
|
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
|
| 393 |
|
|
.order_q_zero (order_q_zero),
|
| 394 |
|
|
.sent_col (sent_col),
|
| 395 |
|
|
.q_has_rd (q_has_rd),
|
| 396 |
|
|
.q_has_priority (q_has_priority),
|
| 397 |
|
|
.req_priority_r (req_priority_r),
|
| 398 |
|
|
.idle_ns (idle_ns),
|
| 399 |
|
|
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
|
| 400 |
|
|
.inhbt_rd (inhbt_rd[RANKS-1:0]),
|
| 401 |
|
|
.inhbt_wr (inhbt_wr[RANKS-1:0]),
|
| 402 |
|
|
.dq_busy_data (dq_busy_data));
|
| 403 |
|
|
|
| 404 |
|
|
mig_7series_v2_3_bank_queue #
|
| 405 |
|
|
(/*AUTOINSTPARAM*/
|
| 406 |
|
|
// Parameters
|
| 407 |
|
|
.TCQ (TCQ),
|
| 408 |
|
|
.BM_CNT_WIDTH (BM_CNT_WIDTH),
|
| 409 |
|
|
.nBANK_MACHS (nBANK_MACHS),
|
| 410 |
|
|
.ORDERING (ORDERING),
|
| 411 |
|
|
.ID (ID))
|
| 412 |
|
|
bank_queue0
|
| 413 |
|
|
(/*AUTOINST*/
|
| 414 |
|
|
// Outputs
|
| 415 |
|
|
.head_r (head_r),
|
| 416 |
|
|
.tail_r (tail_r),
|
| 417 |
|
|
.idle_ns (idle_ns),
|
| 418 |
|
|
.idle_r (idle_r),
|
| 419 |
|
|
.pass_open_bank_ns (pass_open_bank_ns),
|
| 420 |
|
|
.pass_open_bank_r (pass_open_bank_r),
|
| 421 |
|
|
.auto_pre_r (auto_pre_r),
|
| 422 |
|
|
.bm_end (bm_end),
|
| 423 |
|
|
.passing_open_bank (passing_open_bank),
|
| 424 |
|
|
.ordered_issued (ordered_issued),
|
| 425 |
|
|
.ordered_r (ordered_r),
|
| 426 |
|
|
.order_q_zero (order_q_zero),
|
| 427 |
|
|
.rcv_open_bank (rcv_open_bank),
|
| 428 |
|
|
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
|
| 429 |
|
|
.q_has_rd (q_has_rd),
|
| 430 |
|
|
.q_has_priority (q_has_priority),
|
| 431 |
|
|
.wait_for_maint_r (wait_for_maint_r),
|
| 432 |
|
|
// Inputs
|
| 433 |
|
|
.clk (clk),
|
| 434 |
|
|
.rst (rst),
|
| 435 |
|
|
.accept_internal_r (accept_internal_r),
|
| 436 |
|
|
.use_addr (use_addr),
|
| 437 |
|
|
.periodic_rd_ack_r (periodic_rd_ack_r),
|
| 438 |
|
|
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
|
| 439 |
|
|
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
|
| 440 |
|
|
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
|
| 441 |
|
|
.accept_req (accept_req),
|
| 442 |
|
|
.rb_hit_busy_r (rb_hit_busy_r),
|
| 443 |
|
|
.maint_idle (maint_idle),
|
| 444 |
|
|
.maint_hit (maint_hit),
|
| 445 |
|
|
.row_hit_r (row_hit_r),
|
| 446 |
|
|
.pre_wait_r (pre_wait_r),
|
| 447 |
|
|
.allow_auto_pre (allow_auto_pre),
|
| 448 |
|
|
.sending_col (sending_col),
|
| 449 |
|
|
.req_wr_r (req_wr_r),
|
| 450 |
|
|
.rd_wr_r (rd_wr_r),
|
| 451 |
|
|
.bank_wait_in_progress (bank_wait_in_progress),
|
| 452 |
|
|
.precharge_bm_end (precharge_bm_end),
|
| 453 |
|
|
.adv_order_q (adv_order_q),
|
| 454 |
|
|
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
|
| 455 |
|
|
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
|
| 456 |
|
|
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
|
| 457 |
|
|
.was_wr (was_wr),
|
| 458 |
|
|
.maint_req_r (maint_req_r),
|
| 459 |
|
|
.was_priority (was_priority));
|
| 460 |
|
|
|
| 461 |
|
|
endmodule // bank_cntrl
|
