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//*****************************************************************************
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// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : %version
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// \ \ Application : MIG
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// / / Filename : ecc_dec_fix.v
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// /___/ /\ Date Last Modified : $date$
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// \ \ / \ Date Created : Tue Jun 30 2009
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// \___\/\___\
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//
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//Device : 7-Series
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//Design Name : DDR3 SDRAM
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//Purpose :
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//Reference :
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//Revision History :
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ecc_dec_fix
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#(
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parameter TCQ = 100,
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parameter PAYLOAD_WIDTH = 64,
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parameter CODE_WIDTH = 72,
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parameter DATA_WIDTH = 64,
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parameter DQ_WIDTH = 72,
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parameter ECC_WIDTH = 8,
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parameter nCK_PER_CLK = 4
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)
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(
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/*AUTOARG*/
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// Outputs
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rd_data, ecc_single, ecc_multiple,
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// Inputs
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clk, rst, h_rows, phy_rddata, correct_en, ecc_status_valid
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);
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input clk;
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input rst;
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// Compute syndromes.
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input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
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input [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rddata;
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wire [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_ns;
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genvar k;
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genvar m;
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generate
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for (k=0; k<2*nCK_PER_CLK; k=k+1) begin : ecc_word
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for (m=0; m<ECC_WIDTH; m=m+1) begin : ecc_bit
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assign syndrome_ns[k*ECC_WIDTH+m] =
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^(phy_rddata[k*DQ_WIDTH+:CODE_WIDTH] & h_rows[m*CODE_WIDTH+:CODE_WIDTH]);
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end
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end
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endgenerate
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reg [2*nCK_PER_CLK*ECC_WIDTH-1:0] syndrome_r;
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always @(posedge clk) syndrome_r <= #TCQ syndrome_ns;
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// Extract payload bits from raw DRAM bits and register.
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wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_ns;
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genvar i;
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generate
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for (i=0; i<2*nCK_PER_CLK; i=i+1) begin : extract_payload
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assign ecc_rddata_ns[i*PAYLOAD_WIDTH+:PAYLOAD_WIDTH] =
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phy_rddata[i*DQ_WIDTH+:PAYLOAD_WIDTH];
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end
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endgenerate
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reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] ecc_rddata_r;
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always @(posedge clk) ecc_rddata_r <= #TCQ ecc_rddata_ns;
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// Regenerate h_matrix from h_rows leaving out the identity part
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// since we're not going to correct the ECC bits themselves.
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genvar n;
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genvar p;
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wire [ECC_WIDTH-1:0] h_matrix [DATA_WIDTH-1:0];
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generate
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for (n=0; n<DATA_WIDTH; n=n+1) begin : h_col
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for (p=0; p<ECC_WIDTH; p=p+1) begin : h_bit
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assign h_matrix [n][p] = h_rows [p*CODE_WIDTH+n];
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end
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end
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endgenerate
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// Compute flip bits.
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wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] flip_bits;
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genvar q;
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genvar r;
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generate
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for (q=0; q<2*nCK_PER_CLK; q=q+1) begin : flip_word
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for (r=0; r<DATA_WIDTH; r=r+1) begin : flip_bit
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assign flip_bits[q*DATA_WIDTH+r] =
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h_matrix[r] == syndrome_r[q*ECC_WIDTH+:ECC_WIDTH];
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end
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end
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endgenerate
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// Correct data.
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output reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
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input correct_en;
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integer s;
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always @(/*AS*/correct_en or ecc_rddata_r or flip_bits)
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for (s=0; s<2*nCK_PER_CLK; s=s+1)
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if (correct_en)
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rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
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ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH] ^
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flip_bits[s*DATA_WIDTH+:DATA_WIDTH];
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else rd_data[s*PAYLOAD_WIDTH+:DATA_WIDTH] =
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ecc_rddata_r[s*PAYLOAD_WIDTH+:DATA_WIDTH];
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// Copy raw payload bits if ECC_TEST is ON.
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localparam RAW_BIT_WIDTH = PAYLOAD_WIDTH - DATA_WIDTH;
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genvar t;
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generate
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if (RAW_BIT_WIDTH > 0)
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for (t=0; t<2*nCK_PER_CLK; t=t+1) begin : copy_raw_bits
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always @(/*AS*/ecc_rddata_r)
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rd_data[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH] =
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ecc_rddata_r[(t+1)*PAYLOAD_WIDTH-1-:RAW_BIT_WIDTH];
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end
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endgenerate
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// Generate status information.
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input ecc_status_valid;
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output wire [2*nCK_PER_CLK-1:0] ecc_single;
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output wire [2*nCK_PER_CLK-1:0] ecc_multiple;
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genvar v;
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generate
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for (v=0; v<2*nCK_PER_CLK; v=v+1) begin : compute_status
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wire zero = ~|syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
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wire odd = ^syndrome_r[v*ECC_WIDTH+:ECC_WIDTH];
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assign ecc_single[v] = ecc_status_valid && ~zero && odd;
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assign ecc_multiple[v] = ecc_status_valid && ~zero && ~odd;
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end
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endgenerate
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endmodule
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