Subversion Repositories usb_fpga_2_14

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//

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//

//

//  Owner:        Gary Martin

//  Revision:     $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $

//                $Author: gary $

//                $DateTime: 2010/05/11 18:05:17 $

//                $Change: 490882 $

//  Description:

//    This verilog file is the parameterizable 4-byte lane phy primitive top

//    This module may be ganged to create an N-lane phy.

//

//  History:

//  Date        Engineer    Description

//  04/01/2010  G. Martin   Initial Checkin.

//

///////////////////////////////////////////////////////////

**********************************************************/

`timescale 1ps/1ps

`define  PC_DATA_OFFSET_RANGE 22:17

module mig_7series_v2_3_ddr_phy_4lanes #(

parameter  GENERATE_IDELAYCTRL  = "TRUE",

parameter  IODELAY_GRP          = "IODELAY_MIG",

parameter  FPGA_SPEED_GRADE     = 1,

parameter  BANK_TYPE            = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"

parameter  BYTELANES_DDR_CK     = 24'b0010_0010_0010_0010_0010_0010,

parameter  NUM_DDR_CK           = 1,

// next three parameter fields correspond to byte lanes for lane order DCBA

parameter  BYTE_LANES           = 4'b1111, // lane existence, one per lane

parameter  DATA_CTL_N           = 4'b1111, // data or control, per lane

parameter  BITLANES             = 48'hffff_ffff_ffff,

parameter  BITLANES_OUTONLY     = 48'h0000_0000_0000,

parameter  LANE_REMAP           = 16'h3210,// 4-bit index

                                        // used to rewire to one of four

                                        // input/output buss lanes

                                        // example: 0321 remaps lanes as:

                                        //  D->A

                                        //  C->D

                                        //  B->C

                                        //  A->B

parameter   LAST_BANK              = "FALSE",

parameter   USE_PRE_POST_FIFO      = "FALSE",

parameter   RCLK_SELECT_LANE       = "B",

parameter   real  TCK              = 0.00,

parameter   SYNTHESIS              = "FALSE",

parameter   PO_CTL_COARSE_BYPASS   = "FALSE",

parameter   PO_FINE_DELAY          = 0,

parameter   PI_SEL_CLK_OFFSET      = 0,

// phy_control paramter used in other paramsters

parameter   PC_CLK_RATIO           = 4,

//phaser_in parameters

parameter  A_PI_FREQ_REF_DIV       = "NONE",

parameter  A_PI_CLKOUT_DIV         = 2,

parameter  A_PI_BURST_MODE         = "TRUE",

parameter  A_PI_OUTPUT_CLK_SRC     = "DELAYED_REF" , //"DELAYED_REF",

parameter  A_PI_FINE_DELAY         = 60,

parameter  A_PI_SYNC_IN_DIV_RST    = "TRUE",

parameter  B_PI_FREQ_REF_DIV       = A_PI_FREQ_REF_DIV,

parameter  B_PI_CLKOUT_DIV         = A_PI_CLKOUT_DIV,

parameter  B_PI_BURST_MODE         = A_PI_BURST_MODE,

parameter  B_PI_OUTPUT_CLK_SRC     = A_PI_OUTPUT_CLK_SRC,

parameter  B_PI_FINE_DELAY         = A_PI_FINE_DELAY,

parameter  B_PI_SYNC_IN_DIV_RST    = A_PI_SYNC_IN_DIV_RST,

parameter  C_PI_FREQ_REF_DIV       = A_PI_FREQ_REF_DIV,

parameter  C_PI_CLKOUT_DIV         = A_PI_CLKOUT_DIV,

parameter  C_PI_BURST_MODE         = A_PI_BURST_MODE,

parameter  C_PI_OUTPUT_CLK_SRC     = A_PI_OUTPUT_CLK_SRC,

parameter  C_PI_FINE_DELAY         = 0,

parameter  C_PI_SYNC_IN_DIV_RST    = A_PI_SYNC_IN_DIV_RST,

parameter  D_PI_FREQ_REF_DIV       = A_PI_FREQ_REF_DIV,

parameter  D_PI_CLKOUT_DIV         = A_PI_CLKOUT_DIV,

parameter  D_PI_BURST_MODE         = A_PI_BURST_MODE,

parameter  D_PI_OUTPUT_CLK_SRC     = A_PI_OUTPUT_CLK_SRC,

parameter  D_PI_FINE_DELAY         = 0,

parameter  D_PI_SYNC_IN_DIV_RST    = A_PI_SYNC_IN_DIV_RST,

//phaser_out parameters

parameter  A_PO_CLKOUT_DIV         = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO :  2,

parameter  A_PO_FINE_DELAY         = PO_FINE_DELAY,

parameter  A_PO_COARSE_DELAY       = 0,

parameter  A_PO_OCLK_DELAY         = 0,

parameter  A_PO_OCLKDELAY_INV      = "FALSE",

parameter  A_PO_OUTPUT_CLK_SRC     = "DELAYED_REF",

parameter  A_PO_SYNC_IN_DIV_RST    = "TRUE",

//parameter  A_PO_SYNC_IN_DIV_RST    = "FALSE",

parameter  B_PO_CLKOUT_DIV         = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO :  2,

parameter  B_PO_FINE_DELAY         = PO_FINE_DELAY,

parameter  B_PO_COARSE_DELAY       = A_PO_COARSE_DELAY,

parameter  B_PO_OCLK_DELAY         = A_PO_OCLK_DELAY,

parameter  B_PO_OCLKDELAY_INV      = A_PO_OCLKDELAY_INV,

parameter  B_PO_OUTPUT_CLK_SRC     = A_PO_OUTPUT_CLK_SRC,

parameter  B_PO_SYNC_IN_DIV_RST    = A_PO_SYNC_IN_DIV_RST,

parameter  C_PO_CLKOUT_DIV         = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO :  2,

parameter  C_PO_FINE_DELAY         = PO_FINE_DELAY,

parameter  C_PO_COARSE_DELAY       = A_PO_COARSE_DELAY,

parameter  C_PO_OCLK_DELAY         = A_PO_OCLK_DELAY,

parameter  C_PO_OCLKDELAY_INV      = A_PO_OCLKDELAY_INV,

parameter  C_PO_OUTPUT_CLK_SRC     = A_PO_OUTPUT_CLK_SRC,

parameter  C_PO_SYNC_IN_DIV_RST    = A_PO_SYNC_IN_DIV_RST,

parameter  D_PO_CLKOUT_DIV         = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO :  2,

parameter  D_PO_FINE_DELAY         = PO_FINE_DELAY,

parameter  D_PO_COARSE_DELAY       = A_PO_COARSE_DELAY,

parameter  D_PO_OCLK_DELAY         = A_PO_OCLK_DELAY,

parameter  D_PO_OCLKDELAY_INV      = A_PO_OCLKDELAY_INV,

parameter  D_PO_OUTPUT_CLK_SRC     = A_PO_OUTPUT_CLK_SRC,

parameter  D_PO_SYNC_IN_DIV_RST    = A_PO_SYNC_IN_DIV_RST,

parameter  A_IDELAYE2_IDELAY_TYPE  = "VARIABLE",

parameter  A_IDELAYE2_IDELAY_VALUE = 00,

parameter  B_IDELAYE2_IDELAY_TYPE  = A_IDELAYE2_IDELAY_TYPE,

parameter  B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,

parameter  C_IDELAYE2_IDELAY_TYPE  = A_IDELAYE2_IDELAY_TYPE,

parameter  C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,

parameter  D_IDELAYE2_IDELAY_TYPE  = A_IDELAYE2_IDELAY_TYPE,

parameter  D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,

// phy_control parameters

parameter PC_BURST_MODE           = "TRUE",

parameter PC_DATA_CTL_N           = DATA_CTL_N,

parameter PC_CMD_OFFSET           = 0,

parameter PC_RD_CMD_OFFSET_0      = 0,

parameter PC_RD_CMD_OFFSET_1      = 0,

parameter PC_RD_CMD_OFFSET_2      = 0,

parameter PC_RD_CMD_OFFSET_3      = 0,

parameter PC_CO_DURATION          = 1,

parameter PC_DI_DURATION          = 1,

parameter PC_DO_DURATION          = 1,

parameter PC_RD_DURATION_0        = 0,

parameter PC_RD_DURATION_1        = 0,

parameter PC_RD_DURATION_2        = 0,

parameter PC_RD_DURATION_3        = 0,

parameter PC_WR_CMD_OFFSET_0      = 5,

parameter PC_WR_CMD_OFFSET_1      = 5,

parameter PC_WR_CMD_OFFSET_2      = 5,

parameter PC_WR_CMD_OFFSET_3      = 5,

parameter PC_WR_DURATION_0        = 6,

parameter PC_WR_DURATION_1        = 6,

parameter PC_WR_DURATION_2        = 6,

parameter PC_WR_DURATION_3        = 6,

parameter PC_AO_WRLVL_EN          = 0,

parameter PC_AO_TOGGLE            = 4'b0101, // odd bits are toggle (CKE)

parameter PC_FOUR_WINDOW_CLOCKS   = 63,

parameter PC_EVENTS_DELAY         = 18,

parameter PC_PHY_COUNT_EN         = "TRUE",

parameter PC_SYNC_MODE            = "TRUE",

parameter PC_DISABLE_SEQ_MATCH    = "TRUE",

parameter PC_MULTI_REGION         = "FALSE",

// io fifo parameters

parameter  A_OF_ARRAY_MODE        = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" :  "ARRAY_MODE_4_X_4",

parameter  B_OF_ARRAY_MODE        = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" :  "ARRAY_MODE_4_X_4",

parameter  C_OF_ARRAY_MODE        = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" :  "ARRAY_MODE_4_X_4",

parameter  D_OF_ARRAY_MODE        = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" :  "ARRAY_MODE_4_X_4",

parameter  OF_ALMOST_EMPTY_VALUE  = 1,

parameter  OF_ALMOST_FULL_VALUE   = 1,

parameter  OF_OUTPUT_DISABLE      = "TRUE",

parameter  OF_SYNCHRONOUS_MODE    = PC_SYNC_MODE,

parameter  A_OS_DATA_RATE           = "DDR",

parameter  A_OS_DATA_WIDTH          = 4,

parameter  B_OS_DATA_RATE           = A_OS_DATA_RATE,

parameter  B_OS_DATA_WIDTH          = A_OS_DATA_WIDTH,

parameter  C_OS_DATA_RATE           = A_OS_DATA_RATE,

parameter  C_OS_DATA_WIDTH          = A_OS_DATA_WIDTH,

parameter  D_OS_DATA_RATE           = A_OS_DATA_RATE,

parameter  D_OS_DATA_WIDTH          = A_OS_DATA_WIDTH,

parameter  A_IF_ARRAY_MODE          = "ARRAY_MODE_4_X_8",

parameter  B_IF_ARRAY_MODE          = A_IF_ARRAY_MODE,

parameter  C_IF_ARRAY_MODE          = A_IF_ARRAY_MODE,

parameter  D_IF_ARRAY_MODE          = A_IF_ARRAY_MODE,

parameter  IF_ALMOST_EMPTY_VALUE  =  1,

parameter  IF_ALMOST_FULL_VALUE   =  1,

parameter  IF_SYNCHRONOUS_MODE    = PC_SYNC_MODE,

// this is used locally, not for external pushdown

// NOTE: the 0+ is needed in each to coerce to integer for addition.

// otherwise 4x 1'b values are added producing a 1'b value.

parameter HIGHEST_LANE  =  LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),

parameter  N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),

parameter  N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),

parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,

// assume odt per rank + any declared cke's

parameter  AUXOUT_WIDTH = 4,

parameter LP_DDR_CK_WIDTH = 2

,parameter CKE_ODT_AUX = "FALSE"

)

(

//`include "phy.vh"

      input                       rst,

      input                       phy_clk,

      input                       phy_ctl_clk,

      input                       freq_refclk,

      input                       mem_refclk,

      input                       mem_refclk_div4,

      input                       pll_lock,

      input                       sync_pulse,

      input                       idelayctrl_refclk,

      input [HIGHEST_LANE*80-1:0] phy_dout,

      input                       phy_cmd_wr_en,

      input                       phy_data_wr_en,

      input                       phy_rd_en,

      input                       phy_ctl_mstr_empty,

      input [31:0]                phy_ctl_wd,

      input [`PC_DATA_OFFSET_RANGE] data_offset,

      input                       phy_ctl_wr,

      input                       if_empty_def,

      input                       phyGo,

      input                       input_sink,

      output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk,  // to memory

      output                      rclk,

      output                      if_a_empty,

      output                      if_empty,

      output                      byte_rd_en,

      output                      if_empty_or,

      output                      if_empty_and,

      output                      of_ctl_a_full,

      output                      of_data_a_full,

      output                      of_ctl_full,

      output                      of_data_full,

      output                      pre_data_a_full,

      output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus

      output                      phy_ctl_empty,

      output                      phy_ctl_a_full,

      output                      phy_ctl_full,

      output [HIGHEST_LANE*12-1:0]mem_dq_out,

      output [HIGHEST_LANE*12-1:0]mem_dq_ts,

      input  [HIGHEST_LANE*10-1:0]mem_dq_in,

      output [HIGHEST_LANE-1:0]   mem_dqs_out,

      output [HIGHEST_LANE-1:0]   mem_dqs_ts,

      input  [HIGHEST_LANE-1:0]   mem_dqs_in,

      input [1:0]                 byte_rd_en_oth_banks,

      output     [AUXOUT_WIDTH-1:0] aux_out,

      output reg                   rst_out = 0,

      output reg                   mcGo=0,

      output                       phy_ctl_ready,

      output                       ref_dll_lock,

      input                        if_rst,

      input                        phy_read_calib,

      input                        phy_write_calib,

      input                        idelay_inc,

      input                        idelay_ce,

      input                        idelay_ld,

      input  [2:0]                 calib_sel,

      input                        calib_zero_ctrl,

      input  [HIGHEST_LANE-1:0]    calib_zero_lanes,

      input                        calib_in_common,

      input                        po_fine_enable,

      input                        po_coarse_enable,

      input                        po_fine_inc,

      input                        po_coarse_inc,

      input                        po_counter_load_en,

      input                        po_counter_read_en,

      input  [8:0]                 po_counter_load_val,

      input                        po_sel_fine_oclk_delay,

      output reg                   po_coarse_overflow,

      output reg                   po_fine_overflow,

      output reg [8:0]             po_counter_read_val,

      input                        pi_rst_dqs_find,

      input                        pi_fine_enable,

      input                        pi_fine_inc,

      input                        pi_counter_load_en,

      input                        pi_counter_read_en,

      input  [5:0]                 pi_counter_load_val,

      output reg                   pi_fine_overflow,

      output reg [5:0]             pi_counter_read_val,

      output reg                   pi_dqs_found,

      output                       pi_dqs_found_all,

      output                       pi_dqs_found_any,

      output [HIGHEST_LANE-1:0]    pi_phase_locked_lanes,

      output [HIGHEST_LANE-1:0]    pi_dqs_found_lanes,

      output reg                   pi_dqs_out_of_range,

      output reg                   pi_phase_locked,

      output                       pi_phase_locked_all,

      input [29:0]                 fine_delay,

      input                        fine_delay_sel

);

localparam  DATA_CTL_A       = (~DATA_CTL_N[0]);

localparam  DATA_CTL_B       = (~DATA_CTL_N[1]);

localparam  DATA_CTL_C       = (~DATA_CTL_N[2]);

localparam  DATA_CTL_D       = (~DATA_CTL_N[3]);

localparam  PRESENT_CTL_A    = BYTE_LANES[0] && ! DATA_CTL_N[0];

localparam  PRESENT_CTL_B    = BYTE_LANES[1] && ! DATA_CTL_N[1];

localparam  PRESENT_CTL_C    = BYTE_LANES[2] && ! DATA_CTL_N[2];

localparam  PRESENT_CTL_D    = BYTE_LANES[3] && ! DATA_CTL_N[3];

localparam  PRESENT_DATA_A   = BYTE_LANES[0] &&  DATA_CTL_N[0];

localparam  PRESENT_DATA_B   = BYTE_LANES[1] &&  DATA_CTL_N[1];

localparam  PRESENT_DATA_C   = BYTE_LANES[2] &&  DATA_CTL_N[2];

localparam  PRESENT_DATA_D   = BYTE_LANES[3] &&  DATA_CTL_N[3];

localparam  PC_DATA_CTL_A    = (DATA_CTL_A) ? "FALSE" : "TRUE";

localparam  PC_DATA_CTL_B    = (DATA_CTL_B) ? "FALSE" : "TRUE";

localparam  PC_DATA_CTL_C    = (DATA_CTL_C) ? "FALSE" : "TRUE";

localparam  PC_DATA_CTL_D    = (DATA_CTL_D) ? "FALSE" : "TRUE";

localparam  A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE";

localparam  B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE";

localparam  C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE";

localparam  D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE";

localparam  IO_A_START = 41;

localparam  IO_A_END   = 40;

localparam  IO_B_START = 43;

localparam  IO_B_END   = 42;

localparam  IO_C_START = 45;

localparam  IO_C_END   = 44;

localparam  IO_D_START = 47;

localparam  IO_D_END   = 46;

localparam  IO_A_X_START = (HIGHEST_LANE * 10) + 1;

localparam  IO_A_X_END   = (IO_A_X_START-1);

localparam  IO_B_X_START = (IO_A_X_START + 2);

localparam  IO_B_X_END   = (IO_B_X_START -1);

localparam  IO_C_X_START = (IO_B_X_START + 2);

localparam  IO_C_X_END   = (IO_C_X_START -1);

localparam  IO_D_X_START = (IO_C_X_START + 2);

localparam  IO_D_X_END   = (IO_D_X_START -1);

localparam MSB_BURST_PEND_PO             =  3;

localparam MSB_BURST_PEND_PI             =  7;

localparam MSB_RANK_SEL_I                =  MSB_BURST_PEND_PI + 8;

localparam PHASER_CTL_BUS_WIDTH          =  MSB_RANK_SEL_I + 1;

wire [1:0]  oserdes_dqs;

wire [1:0]  oserdes_dqs_ts;

wire [1:0]  oserdes_dq_ts;

wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;

wire [7:0]  in_rank;

wire [11:0] IO_A;

wire [11:0] IO_B;

wire [11:0] IO_C;

wire [11:0] IO_D;

wire [319:0] phy_din_remap;

reg        A_po_counter_read_en;

wire [8:0] A_po_counter_read_val;

reg        A_pi_counter_read_en;

wire [5:0] A_pi_counter_read_val;

wire       A_pi_fine_overflow;

wire       A_po_coarse_overflow;

wire       A_po_fine_overflow;

wire       A_pi_dqs_found;

wire       A_pi_dqs_out_of_range;

wire       A_pi_phase_locked;

wire       A_pi_iserdes_rst;

reg        A_pi_fine_enable;

reg        A_pi_fine_inc;

reg        A_pi_counter_load_en;

reg [5:0]  A_pi_counter_load_val;

reg        A_pi_rst_dqs_find;

reg        A_po_fine_enable;

reg        A_po_coarse_enable;

 reg        A_po_fine_inc /* synthesis syn_maxfan = 3 */;

reg        A_po_sel_fine_oclk_delay;

reg        A_po_coarse_inc;

reg        A_po_counter_load_en;

reg [8:0]  A_po_counter_load_val;

wire       A_rclk;

reg        A_idelay_ce;

reg        A_idelay_ld;

reg [29:0] A_fine_delay;

reg        A_fine_delay_sel;

reg        B_po_counter_read_en;

wire [8:0] B_po_counter_read_val;

reg        B_pi_counter_read_en;

wire [5:0] B_pi_counter_read_val;

wire       B_pi_fine_overflow;

wire       B_po_coarse_overflow;

wire       B_po_fine_overflow;

wire       B_pi_phase_locked;

wire       B_pi_iserdes_rst;

wire       B_pi_dqs_found;

wire       B_pi_dqs_out_of_range;

reg        B_pi_fine_enable;

reg        B_pi_fine_inc;

reg        B_pi_counter_load_en;

reg [5:0]  B_pi_counter_load_val;

reg        B_pi_rst_dqs_find;

reg        B_po_fine_enable;

reg        B_po_coarse_enable;

 reg        B_po_fine_inc /* synthesis syn_maxfan = 3 */;

reg        B_po_coarse_inc;

reg        B_po_sel_fine_oclk_delay;

reg        B_po_counter_load_en;

reg [8:0]  B_po_counter_load_val;

wire       B_rclk;

reg        B_idelay_ce;

reg        B_idelay_ld;

reg [29:0] B_fine_delay;

reg        B_fine_delay_sel;

reg        C_pi_fine_inc;

reg        D_pi_fine_inc;

reg        C_pi_fine_enable;

reg        D_pi_fine_enable;

reg        C_po_counter_load_en;

reg        D_po_counter_load_en;

reg        C_po_coarse_inc;

reg        D_po_coarse_inc;

 reg        C_po_fine_inc /* synthesis syn_maxfan = 3 */;

 reg        D_po_fine_inc /* synthesis syn_maxfan = 3 */;

reg        C_po_sel_fine_oclk_delay;

reg        D_po_sel_fine_oclk_delay;

reg [5:0]  C_pi_counter_load_val;

reg [5:0]  D_pi_counter_load_val;

reg [8:0]  C_po_counter_load_val;

reg [8:0]  D_po_counter_load_val;

reg        C_po_coarse_enable;

reg        D_po_coarse_enable;

reg        C_po_fine_enable;

reg        D_po_fine_enable;

wire       C_po_coarse_overflow;

wire       D_po_coarse_overflow;

wire       C_po_fine_overflow;

wire       D_po_fine_overflow;

wire [8:0] C_po_counter_read_val;

wire [8:0] D_po_counter_read_val;

reg        C_po_counter_read_en;

reg        D_po_counter_read_en;

wire       C_pi_dqs_found;

wire       D_pi_dqs_found;

wire       C_pi_fine_overflow;

wire       D_pi_fine_overflow;

reg        C_pi_counter_read_en;

reg        D_pi_counter_read_en;

reg        C_pi_counter_load_en;

reg        D_pi_counter_load_en;

wire       C_pi_phase_locked;

wire       C_pi_iserdes_rst;

wire       D_pi_phase_locked;

wire       D_pi_iserdes_rst;

wire       C_pi_dqs_out_of_range;

wire       D_pi_dqs_out_of_range;

wire [5:0] C_pi_counter_read_val;

wire [5:0] D_pi_counter_read_val;

wire       C_rclk;

wire       D_rclk;

reg        C_idelay_ce;

reg        D_idelay_ce;

reg        C_idelay_ld;

reg        D_idelay_ld;

reg        C_pi_rst_dqs_find;

reg        D_pi_rst_dqs_find;

reg [29:0] C_fine_delay;

reg [29:0] D_fine_delay;

reg        C_fine_delay_sel;

reg        D_fine_delay_sel;

wire       pi_iserdes_rst;

wire       A_if_empty;

wire       B_if_empty;

wire       C_if_empty;

wire       D_if_empty;

wire       A_byte_rd_en;

wire       B_byte_rd_en;

wire       C_byte_rd_en;

wire       D_byte_rd_en;

wire       A_if_a_empty;

wire       B_if_a_empty;

wire       C_if_a_empty;

wire       D_if_a_empty;

//wire       A_if_full;

//wire       B_if_full;

//wire       C_if_full;

//wire       D_if_full;

//wire       A_of_empty;

//wire       B_of_empty;

//wire       C_of_empty;

//wire       D_of_empty;

wire       A_of_full;

wire       B_of_full;

wire       C_of_full;

wire       D_of_full;

wire       A_of_ctl_full;

wire       B_of_ctl_full;

wire       C_of_ctl_full;

wire       D_of_ctl_full;

wire       A_of_data_full;

wire       B_of_data_full;

wire       C_of_data_full;

wire       D_of_data_full;

wire       A_of_a_full;

wire       B_of_a_full;

wire       C_of_a_full;

wire       D_of_a_full;

wire       A_pre_fifo_a_full;

wire       B_pre_fifo_a_full;

wire       C_pre_fifo_a_full;

wire       D_pre_fifo_a_full;

wire       A_of_ctl_a_full;

wire       B_of_ctl_a_full;

wire       C_of_ctl_a_full;

wire       D_of_ctl_a_full;

wire       A_of_data_a_full;

wire       B_of_data_a_full;

wire       C_of_data_a_full;

wire       D_of_data_a_full;

wire       A_pre_data_a_full;

wire       B_pre_data_a_full;

wire       C_pre_data_a_full;

wire       D_pre_data_a_full;

wire  [LP_DDR_CK_WIDTH*6-1:0]  A_ddr_clk;  // for generation

wire  [LP_DDR_CK_WIDTH*6-1:0]  B_ddr_clk;  //

wire  [LP_DDR_CK_WIDTH*6-1:0]  C_ddr_clk;  //

wire  [LP_DDR_CK_WIDTH*6-1:0]  D_ddr_clk;  //

wire [3:0] dummy_data;

wire  [31:0]  _phy_ctl_wd;

wire [1:0] phy_encalib;

assign pi_dqs_found_all =

           (! PRESENT_DATA_A | A_pi_dqs_found) &

           (! PRESENT_DATA_B | B_pi_dqs_found) &

           (! PRESENT_DATA_C | C_pi_dqs_found) &

           (! PRESENT_DATA_D | D_pi_dqs_found) ;

assign  pi_dqs_found_any =

           ( PRESENT_DATA_A & A_pi_dqs_found) |

           ( PRESENT_DATA_B & B_pi_dqs_found) |

           ( PRESENT_DATA_C & C_pi_dqs_found) |

           ( PRESENT_DATA_D & D_pi_dqs_found) ;

assign  pi_phase_locked_all =

           (! PRESENT_DATA_A | A_pi_phase_locked) &

           (! PRESENT_DATA_B | B_pi_phase_locked) &

           (! PRESENT_DATA_C | C_pi_phase_locked) &

           (! PRESENT_DATA_D | D_pi_phase_locked);

wire       dangling_inputs = (& dummy_data) & input_sink & 1'b0;  // this reduces all constant 0 values to 1 signal

                              // which is combined into another signals such that

                              // the other signal isn't changed. The purpose

                              // is to fake the tools into ignoring dangling inputs.

                              // Because it is anded with 1'b0, the contributing signals

                              // are folded as constants or trimmed.

assign      if_empty = !if_empty_def  ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty);

assign      byte_rd_en = !if_empty_def  ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) :

                                          (A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en);

assign      if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty);

assign      if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty);

assign      if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty;

//assign      if_full  = A_if_full  | B_if_full  | C_if_full  | D_if_full ;

//assign      of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;

assign      of_ctl_full     = A_of_ctl_full  | B_of_ctl_full  | C_of_ctl_full  | D_of_ctl_full ;

assign      of_data_full    = A_of_data_full  | B_of_data_full  | C_of_data_full  | D_of_data_full ;

assign      of_ctl_a_full   = A_of_ctl_a_full  | B_of_ctl_a_full  | C_of_ctl_a_full  | D_of_ctl_a_full ;

assign      of_data_a_full  = A_of_data_a_full  | B_of_data_a_full  | C_of_data_a_full  | D_of_data_a_full | dangling_inputs   ;

assign      pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full;

function [79:0] part_select_80;

input [319:0] vector;

input [1:0]  select;

begin

     case (select)

     2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];