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//*****************************************************************************
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// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
8 
//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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//   ____  ____
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//  /   /\/   /
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// /___/  \  /    Vendor: Xilinx
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// \   \   \/     Version:
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//  \   \         Application: MIG
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//  /   /         Filename: ddr_phy_prbs_rdlvl.v
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// /___/   /\     Date Last Modified: $Date: 2011/06/24 14:49:00 $
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// \   \  /  \    Date Created:
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//  \___\/\___\
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//
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//Device: 7 Series
60 
//Design Name: DDR3 SDRAM
61 
//Purpose:
62 
//  PRBS Read leveling calibration logic
63 
//  NOTES:
64 
//    1. Window detection with PRBS pattern.
65 
//Reference:
66 
//Revision History:
67 
//*****************************************************************************
68 
 
69 
/******************************************************************************
70 
**$Id: ddr_phy_prbs_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $
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**$Date: 2011/06/24 14:49:00 $
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**$Author: mgeorge $
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**$Revision: 1.2 $
74 
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_prbs_rdlvl.v,v $
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******************************************************************************/
76 
 
77 
`timescale 1ps/1ps
78 
 
79 
module mig_7series_v2_3_ddr_phy_prbs_rdlvl #
80 
  (
81 
   parameter TCQ             = 100,    // clk->out delay (sim only)
82 
   parameter nCK_PER_CLK     = 2,      // # of memory clocks per CLK
83 
   parameter DQ_WIDTH        = 64,     // # of DQ (data)
84 
   parameter DQS_CNT_WIDTH   = 3,      // = ceil(log2(DQS_WIDTH))
85 
   parameter DQS_WIDTH       = 8,      // # of DQS (strobe)
86 
   parameter DRAM_WIDTH      = 8,      // # of DQ per DQS
87 
   parameter RANKS           = 1,      // # of DRAM ranks
88 
   parameter SIM_CAL_OPTION  = "NONE", // Skip various calibration steps
89 
   parameter PRBS_WIDTH      = 8,      // PRBS generator output width
90 
   parameter FIXED_VICTIM    = "TRUE",  // No victim rotation when "TRUE"
91 
   parameter FINE_PER_BIT    = "ON",
92 
   parameter CENTER_COMP_MODE = "ON",
93 
   parameter PI_VAL_ADJ       = "ON"
94 
   )
95 
  (
96 
   input                        clk,
97 
   input                        rst,
98 
   // Calibration status, control signals
99 
   input                        prbs_rdlvl_start,
100 
   (* max_fanout = 100 *) output reg                   prbs_rdlvl_done,
101 
   output reg                   prbs_last_byte_done,
102 
   output reg                   prbs_rdlvl_prech_req,
103 
   input                        complex_sample_cnt_inc,
104 
   input                        prech_done,
105 
   input                        phy_if_empty,
106 
   // Captured data in fabric clock domain
107 
   input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
108 
   //Expected data from PRBS generator
109 
   input [2*nCK_PER_CLK*DQ_WIDTH-1:0] compare_data,
110 
   // Decrement initial Phaser_IN Fine tap delay
111 
   input [5:0]                  pi_counter_read_val,
112 
   // Stage 1 calibration outputs
113 
   output reg                   pi_en_stg2_f,
114 
   output reg                   pi_stg2_f_incdec,
115 
   output [255:0]               dbg_prbs_rdlvl,
116 
   output [DQS_CNT_WIDTH:0]     pi_stg2_prbs_rdlvl_cnt,
117 
   output reg [2:0]             rd_victim_sel,
118 
   output reg                   complex_victim_inc,
119 
   output reg                   reset_rd_addr,
120 
   output reg                   read_pause,
121 
 
122 
   output reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,
123 
   output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
124 
   output reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
125 
   output reg [DRAM_WIDTH-1:0]        fine_delay_incdec_pb,  //fine_delay decreament per bit
126 
   output reg                         fine_delay_sel        //fine delay selection - actual update of fine delay
127 
   );
128 
 
129 
 
130 
 
131 
 
132 
  localparam [5:0] PRBS_IDLE                 = 6'h00;
133 
  localparam [5:0] PRBS_NEW_DQS_WAIT         = 6'h01;
134 
  localparam [5:0] PRBS_PAT_COMPARE          = 6'h02;
135 
  localparam [5:0] PRBS_DEC_DQS              = 6'h03;
136 
  localparam [5:0] PRBS_DEC_DQS_WAIT         = 6'h04;
137 
  localparam [5:0] PRBS_INC_DQS              = 6'h05;
138 
  localparam [5:0] PRBS_INC_DQS_WAIT         = 6'h06;
139 
  localparam [5:0] PRBS_CALC_TAPS            = 6'h07;
140 
  localparam [5:0] PRBS_NEXT_DQS             = 6'h08;
141 
  localparam [5:0] PRBS_NEW_DQS_PREWAIT      = 6'h09;
142 
  localparam [5:0] PRBS_DONE                 = 6'h0A;
143 
  localparam [5:0] PRBS_CALC_TAPS_PRE        = 6'h0B;
144 
  localparam [5:0] PRBS_CALC_TAPS_WAIT       = 6'h0C;
145 
 
146 
  localparam [5:0] FINE_PI_DEC               = 6'h0D;  //go back to all fail or back to center
147 
  localparam [5:0] FINE_PI_DEC_WAIT          = 6'h0E;  //wait for PI tap dec settle
148 
  localparam [5:0] FINE_PI_INC               = 6'h0F;  //increse up to 1 fail
149 
  localparam [5:0] FINE_PI_INC_WAIT          = 6'h10;  //wait for PI tap int settle
150 
  localparam [5:0] FINE_PAT_COMPARE_PER_BIT  = 6'h11;  //compare per bit error and check left/right/gain/loss
151 
  localparam [5:0] FINE_CALC_TAPS            = 6'h12;  //setup fine_delay_incdec_pb for better window size
152 
  localparam [5:0] FINE_CALC_TAPS_WAIT       = 6'h13;  //wait for ROM value for dec cnt
153 
 
154 
  localparam [11:0] NUM_SAMPLES_CNT  = (SIM_CAL_OPTION == "NONE") ? 'd50 : 12'h001;
155 
  localparam [11:0] NUM_SAMPLES_CNT1 = (SIM_CAL_OPTION == "NONE") ? 'd20 : 12'h001;
156 
  localparam [11:0] NUM_SAMPLES_CNT2 = (SIM_CAL_OPTION == "NONE") ? 'd10 : 12'h001;
157 
 
158 
  wire [DQS_CNT_WIDTH+2:0]prbs_dqs_cnt_timing;
159 
  reg [DQS_CNT_WIDTH+2:0] prbs_dqs_cnt_timing_r;
160 
  reg [DQS_CNT_WIDTH:0]   prbs_dqs_cnt_r;
161 
  reg                     prbs_prech_req_r;
162 
  reg [5:0]               prbs_state_r;
163 
  reg [5:0]               prbs_state_r1;
164 
  reg                     wait_state_cnt_en_r;
165 
  reg [3:0]               wait_state_cnt_r;
166 
  reg                     cnt_wait_state;
167 
  reg                     err_chk_invalid;
168 
 // reg                     found_edge_r;
169 
  reg                     prbs_found_1st_edge_r;
170 
  reg                     prbs_found_2nd_edge_r;
171 
  reg [5:0]               prbs_1st_edge_taps_r;
172 
 // reg                     found_stable_eye_r;
173 
  reg [5:0]               prbs_dqs_tap_cnt_r;
174 
  reg [5:0]               prbs_dec_tap_calc_plus_3;
175 
  reg [5:0]               prbs_dec_tap_calc_minus_3;
176 
  reg                     prbs_dqs_tap_limit_r;
177 
  reg [5:0]               prbs_inc_tap_cnt;
178 
  reg [5:0]               prbs_dec_tap_cnt;
179 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall0_r1;
180 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall1_r1;
181 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise0_r1;
182 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise1_r1;
183 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall2_r1;
184 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall3_r1;
185 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise2_r1;
186 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise3_r1;
187 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall0_r2;
188 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall1_r2;
189 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise0_r2;
190 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise1_r2;
191 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall2_r2;
192 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall3_r2;
193 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise2_r2;
194 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise3_r2;
195 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall0_r3;
196 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall1_r3;
197 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise0_r3;
198 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise1_r3;
199 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall2_r3;
200 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall3_r3;
201 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise2_r3;
202 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise3_r3;
203 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall0_r4;
204 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall1_r4;
205 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise0_r4;
206 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise1_r4;
207 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall2_r4;
208 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall3_r4;
209 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise2_r4;
210 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise3_r4;
211 
  reg                     mux_rd_valid_r;
212 
  reg                     rd_valid_r1;
213 
  reg                     rd_valid_r2;
214 
  reg                     rd_valid_r3;
215 
  reg                     new_cnt_dqs_r;
216 
  reg                     prbs_tap_en_r;
217 
  reg                     prbs_tap_inc_r;
218 
  reg                     pi_en_stg2_f_timing;
219 
  reg                     pi_stg2_f_incdec_timing;
220 
  wire [DQ_WIDTH-1:0]     rd_data_rise0;
221 
  wire [DQ_WIDTH-1:0]     rd_data_fall0;
222 
  wire [DQ_WIDTH-1:0]     rd_data_rise1;
223 
  wire [DQ_WIDTH-1:0]     rd_data_fall1;
224 
  wire [DQ_WIDTH-1:0]     rd_data_rise2;
225 
  wire [DQ_WIDTH-1:0]     rd_data_fall2;
226 
  wire [DQ_WIDTH-1:0]     rd_data_rise3;
227 
  wire [DQ_WIDTH-1:0]     rd_data_fall3;
228 
  wire [DQ_WIDTH-1:0]     compare_data_r0;
229 
  wire [DQ_WIDTH-1:0]     compare_data_f0;
230 
  wire [DQ_WIDTH-1:0]     compare_data_r1;
231 
  wire [DQ_WIDTH-1:0]     compare_data_f1;
232 
  wire [DQ_WIDTH-1:0]     compare_data_r2;
233 
  wire [DQ_WIDTH-1:0]     compare_data_f2;
234 
  wire [DQ_WIDTH-1:0]     compare_data_r3;
235 
  wire [DQ_WIDTH-1:0]     compare_data_f3;
236 
  reg [DRAM_WIDTH-1:0]    compare_data_rise0_r1;
237 
  reg [DRAM_WIDTH-1:0]    compare_data_fall0_r1;
238 
  reg [DRAM_WIDTH-1:0]    compare_data_rise1_r1;
239 
  reg [DRAM_WIDTH-1:0]    compare_data_fall1_r1;
240 
  reg [DRAM_WIDTH-1:0]    compare_data_rise2_r1;
241 
  reg [DRAM_WIDTH-1:0]    compare_data_fall2_r1;
242 
  reg [DRAM_WIDTH-1:0]    compare_data_rise3_r1;
243 
  reg [DRAM_WIDTH-1:0]    compare_data_fall3_r1;
244 
  reg [DQS_CNT_WIDTH:0]   rd_mux_sel_r;
245 
  reg [5:0]               prbs_2nd_edge_taps_r;
246 
 
247 
 // reg [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
248 
  reg [5:0]               rdlvl_cpt_tap_cnt;
249 
  reg                     prbs_rdlvl_start_r;
250 
 
251 
  reg                     compare_err;
252 
  reg                     compare_err_r0;
253 
  reg                     compare_err_f0;
254 
  reg                     compare_err_r1;
255 
  reg                     compare_err_f1;
256 
  reg                     compare_err_r2;
257 
  reg                     compare_err_f2;
258 
  reg                     compare_err_r3;
259 
  reg                     compare_err_f3;
260 
 
261 
  reg                     samples_cnt1_en_r;
262 
  reg                     samples_cnt2_en_r;
263 
  reg [11:0]              samples_cnt_r;
264 
  reg                     num_samples_done_r;
265 
  reg                     num_samples_done_ind;  //indicate num_samples_done_r is set in FINE_PAT_COMPARE_PER_BIT to prevent victim_sel_rd out of sync
266 
  reg [DQS_WIDTH-1:0]     prbs_tap_mod;
267 
 
268 
  //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
269 
  //reg [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
270 
 
271 
   //**************************************************************************
272 
   // signals for per-bit algorithm of fine_delay calculations
273 
   //**************************************************************************
274 
  reg [6*DRAM_WIDTH-1:0] left_edge_pb;           //left edge value per bit
275 
  reg [6*DRAM_WIDTH-1:0] right_edge_pb;          //right edge value per bit
276 
  reg [5*DRAM_WIDTH-1:0] match_flag_pb;          //5 consecutive match flag per bit
277 
  reg [4:0]              match_flag_and;         //5 consecute match flag of all bits (1: all bit fail)
278 
  reg [DRAM_WIDTH-1:0]   left_edge_found_pb;     //left_edge found per bit - use for loss calculation
279 
  reg [DRAM_WIDTH-1:0]   left_edge_updated;      //left edge was updated for this PI tap - used for largest left edge /ref bit update
280 
  reg [DRAM_WIDTH-1:0]   right_edge_found_pb;    //right_edge found per bit - use for gail calulation and smallest right edge update
281 
  reg                    right_edge_found;       //smallest right_edge found
282 
  reg [DRAM_WIDTH*6-1:0] left_loss_pb;           //left_edge loss per bit
283 
  reg [DRAM_WIDTH*6-1:0] right_gain_pb;          //right_edge gain per bit
284 
  reg [DRAM_WIDTH-1:0]   ref_bit;                //bit number which has largest left edge (with smaller right edge)
285 
  reg [DRAM_WIDTH-1:0]   bit_cnt;                //bit number used to calculate ref bit
286 
  reg [DRAM_WIDTH-1:0]   ref_bit_per_bit;        //bit flags which have largest left edge
287 
  reg [5:0]              ref_right_edge;         //ref_bit right edge - keep the smallest edge of ref bits
288 
  reg [5:0]              largest_left_edge;      //biggest left edge of per bit - will be left edge of byte
289 
  reg [5:0]              smallest_right_edge;    //smallest right edge of per bit - will be right edge of byte
290 
  reg [5:0]              fine_pi_dec_cnt;        //Phase In tap decrement count (to go back to '0' or center)
291 
  reg [6:0]              center_calc;            //used for calculate the dec tap for centering
292 
  reg [5:0]              right_edge_ref;         //ref_bit right edge
293 
  reg [5:0]              left_edge_ref;          //ref_bit left edge
294 
 
295 
  reg [DRAM_WIDTH-1:0]   compare_err_pb;         //compare error per bit
296 
  reg [DRAM_WIDTH-1:0]   compare_err_pb_latch_r; //sticky compare error per bit used for left/right edge
297 
  reg                    compare_err_pb_and;     //indicate all bit fail
298 
  reg                    fine_inc_stage;         //fine_inc_stage (1: increment all except ref_bit, 0: only inc for gain bit)
299 
  reg [1:0]              stage_cnt;              //stage cnt (0,1: fine delay inc stage, 2: fine delay dec stage)
300 
  wire                   fine_calib;             //turn on/off fine delay calibration
301 
 
302 
  reg [5:0]              mem_out_dec;
303 
  reg [5:0]              dec_cnt;
304 
  reg                    fine_dly_error;        //indicate it has wrong left/right edge
305 
 
306 
  wire                   center_comp;
307 
  wire                   pi_adj;
308 
 
309 
   //**************************************************************************
310 
   // DQS count to hard PHY during write calibration using Phaser_OUT Stage2
311 
   // coarse delay
312 
   //**************************************************************************
313 
   assign pi_stg2_prbs_rdlvl_cnt = prbs_dqs_cnt_r;
314 
 
315 
   //fine delay turn on
316 
   assign fine_calib    = (FINE_PER_BIT=="ON")? 1:0;
317 
   assign center_comp   = (CENTER_COMP_MODE == "ON")? 1: 0;
318 
   assign pi_adj        = (PI_VAL_ADJ == "ON")?1:0;
319 
 
320 
   assign dbg_prbs_rdlvl[0+:6]  = left_edge_pb[0+:6];
321 
   assign dbg_prbs_rdlvl[7:6]  = left_loss_pb[0+:2];
322 
   assign dbg_prbs_rdlvl[8+:6]  = left_edge_pb[6+:6];
323 
   assign dbg_prbs_rdlvl[15:14]  = left_loss_pb[6+:2];
324 
   assign dbg_prbs_rdlvl[16+:6] = left_edge_pb[12+:6] ;
325 
   assign dbg_prbs_rdlvl[23:22]  = left_loss_pb[12+:2];
326 
   assign dbg_prbs_rdlvl[24+:6] = left_edge_pb[18+:6] ;
327 
   assign dbg_prbs_rdlvl[31:30]  = left_loss_pb[18+:2];
328 
   assign dbg_prbs_rdlvl[32+:6] = left_edge_pb[24+:6];
329 
   assign dbg_prbs_rdlvl[39:38]  = left_loss_pb[24+:2];
330 
   assign dbg_prbs_rdlvl[40+:6] = left_edge_pb[30+:6];
331 
   assign dbg_prbs_rdlvl[47:46]  = left_loss_pb[30+:2];
332 
   assign dbg_prbs_rdlvl[48+:6] = left_edge_pb[36+:6];
333 
   assign dbg_prbs_rdlvl[55:54]  = left_loss_pb[36+:2];
334 
   assign dbg_prbs_rdlvl[56+:6] = left_edge_pb[42+:6];
335 
   assign dbg_prbs_rdlvl[63:62]  = left_loss_pb[42+:2];
336 
 
337 
   assign dbg_prbs_rdlvl[64+:6]  = right_edge_pb[0+:6];
338 
   assign dbg_prbs_rdlvl[71:70]  = right_gain_pb[0+:2];
339 
   assign dbg_prbs_rdlvl[72+:6]  = right_edge_pb[6+:6] ;
340 
   assign dbg_prbs_rdlvl[79:78]  = right_gain_pb[6+:2];
341 
   assign dbg_prbs_rdlvl[80+:6]  = right_edge_pb[12+:6];
342 
   assign dbg_prbs_rdlvl[87:86]  = right_gain_pb[12+:2];
343 
   assign dbg_prbs_rdlvl[88+:6]  = right_edge_pb[18+:6];
344 
   assign dbg_prbs_rdlvl[95:94]  = right_gain_pb[18+:2];
345 
   assign dbg_prbs_rdlvl[96+:6]  = right_edge_pb[24+:6];
346 
   assign dbg_prbs_rdlvl[103:102]  = right_gain_pb[24+:2];
347 
   assign dbg_prbs_rdlvl[104+:6] = right_edge_pb[30+:6];
348 
   assign dbg_prbs_rdlvl[111:110]  = right_gain_pb[30+:2];
349 
   assign dbg_prbs_rdlvl[112+:6] = right_edge_pb[36+:6];
350 
   assign dbg_prbs_rdlvl[119:118]  = right_gain_pb[36+:2];
351 
   assign dbg_prbs_rdlvl[120+:6] = right_edge_pb[42+:6];
352 
   assign dbg_prbs_rdlvl[127:126]  = right_gain_pb[42+:2];
353 
 
354 
   assign dbg_prbs_rdlvl[128+:6] = pi_counter_read_val;
355 
   assign dbg_prbs_rdlvl[134+:6] = prbs_dqs_tap_cnt_r;
356 
 
357 
   assign dbg_prbs_rdlvl[140]    = prbs_found_1st_edge_r;
358 
   assign dbg_prbs_rdlvl[141]    = prbs_found_2nd_edge_r;
359 
   assign dbg_prbs_rdlvl[142]    = compare_err;
360 
   assign dbg_prbs_rdlvl[143]    = phy_if_empty;
361 
   assign dbg_prbs_rdlvl[144]    = prbs_rdlvl_start;
362 
   assign dbg_prbs_rdlvl[145]    = prbs_rdlvl_done;
363 
   assign dbg_prbs_rdlvl[146+:5] = prbs_dqs_cnt_r;
364 
   assign dbg_prbs_rdlvl[151+:6] = left_edge_pb[prbs_dqs_cnt_r*6+:6] ;
365 
   assign dbg_prbs_rdlvl[157+:6] = right_edge_pb[prbs_dqs_cnt_r*6+:6];
366 
   assign dbg_prbs_rdlvl[163+:6] = {2'h0,complex_victim_inc, rd_victim_sel[2:0]};
367 
   assign dbg_prbs_rdlvl[169+:6] =right_gain_pb[prbs_dqs_cnt_r*6+:6] ;
368 
   assign dbg_prbs_rdlvl[177:175] = ref_bit[2:0];
369 
 
370 
   assign dbg_prbs_rdlvl[178+:6] = prbs_state_r1[5:0];
371 
   assign dbg_prbs_rdlvl[184] = rd_valid_r2;
372 
   assign dbg_prbs_rdlvl[185] = compare_err_r0;
373 
   assign dbg_prbs_rdlvl[186] = compare_err_f0;
374 
   assign dbg_prbs_rdlvl[187] = compare_err_r1;
375 
   assign dbg_prbs_rdlvl[188] = compare_err_f1;
376 
   assign dbg_prbs_rdlvl[189] = compare_err_r2;
377 
   assign dbg_prbs_rdlvl[190] = compare_err_f2;
378 
   assign dbg_prbs_rdlvl[191] = compare_err_r3;
379 
   assign dbg_prbs_rdlvl[192] = compare_err_f3;
380 
   assign dbg_prbs_rdlvl[193+:8] = left_edge_found_pb;
381 
   assign dbg_prbs_rdlvl[201+:8] = right_edge_found_pb;
382 
   assign dbg_prbs_rdlvl[209+:6] =largest_left_edge ;
383 
   assign dbg_prbs_rdlvl[215+:6] =smallest_right_edge ;
384 
   assign dbg_prbs_rdlvl[221+:8] = fine_delay_incdec_pb;
385 
   assign dbg_prbs_rdlvl[229] = fine_delay_sel;
386 
   assign dbg_prbs_rdlvl[230+:8] = compare_err_pb_latch_r;
387 
   assign dbg_prbs_rdlvl[238+:6] = fine_pi_dec_cnt;
388 
   assign dbg_prbs_rdlvl[244+:5] = match_flag_and ;
389 
   assign dbg_prbs_rdlvl[249+:2] =stage_cnt  ;
390 
   assign dbg_prbs_rdlvl[251] =  fine_inc_stage  ;
391 
   assign dbg_prbs_rdlvl[252] =  compare_err_pb_and  ;
392 
   assign dbg_prbs_rdlvl[253] =  right_edge_found ;
393 
   assign dbg_prbs_rdlvl[254] =  fine_dly_error ;
394 
   assign dbg_prbs_rdlvl[255]= 'b0;//reserved
395 
 
396 
  //**************************************************************************
397 
  // Record first and second edges found during calibration
398 
  //**************************************************************************
399 
  generate
400 
    always @(posedge clk)
401 
      if (rst) begin
402 
        dbg_prbs_first_edge_taps  <= #TCQ 'b0;
403 
        dbg_prbs_second_edge_taps <= #TCQ 'b0;
404 
      end else if (prbs_state_r == PRBS_CALC_TAPS) begin
405 
        // Record tap counts of first and second edge edges during
406 
        // calibration for each DQS group. If neither edge has
407 
        // been found, then those taps will remain 0
408 
          if (prbs_found_1st_edge_r)
409 
            dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
410 
              <= #TCQ prbs_1st_edge_taps_r;
411 
          if (prbs_found_2nd_edge_r)
412 
            dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
413 
              <= #TCQ prbs_2nd_edge_taps_r;
414 
      end else if (prbs_state_r == FINE_CALC_TAPS) begin
415 
        if(stage_cnt == 'd2) begin
416 
            dbg_prbs_first_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
417 
              <= #TCQ largest_left_edge;
418 
            dbg_prbs_second_edge_taps[(prbs_dqs_cnt_timing_r*6)+:6]
419 
            <= #TCQ smallest_right_edge;
420 
        end
421 
      end
422 
  endgenerate
423 
 
424 
 //padded calculation
425 
  always @ (smallest_right_edge or largest_left_edge)
426 
    center_calc <= {1'b0, smallest_right_edge} + {1'b0,largest_left_edge};
427 
  //***************************************************************************
428 
  //***************************************************************************
429 
  // Data mux to route appropriate bit to calibration logic - i.e. calibration
430 
  // is done sequentially, one bit (or DQS group) at a time
431 
  //***************************************************************************
432 
 
433 
  generate
434 
    if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk
435 
      assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
436 
      assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
437 
      assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
438 
      assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
439 
      assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
440 
      assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
441 
      assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
442 
      assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
443 
      assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];
444 
      assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];
445 
      assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
446 
      assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
447 
      assign compare_data_r2 = compare_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
448 
      assign compare_data_f2 = compare_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
449 
      assign compare_data_r3 = compare_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
450 
      assign compare_data_f3 = compare_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
451 
    end else begin: rd_data_div2_logic_clk
452 
      assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
453 
      assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
454 
      assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
455 
      assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
456 
      assign compare_data_r0 = compare_data[DQ_WIDTH-1:0];
457 
      assign compare_data_f0 = compare_data[2*DQ_WIDTH-1:DQ_WIDTH];
458 
      assign compare_data_r1 = compare_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
459 
      assign compare_data_f1 = compare_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
460 
      assign compare_data_r2 = 'h0;
461 
      assign compare_data_f2 = 'h0;
462 
      assign compare_data_r3 = 'h0;
463 
      assign compare_data_f3 = 'h0;
464 
    end
465 
  endgenerate
466 
 
467 
  always @(posedge clk) begin
468 
    rd_mux_sel_r <= #TCQ prbs_dqs_cnt_r;
469 
  end
470 
 
471 
  // Register outputs for improved timing.
472 
  // NOTE: Will need to change when per-bit DQ deskew is supported.
473 
  //       Currenly all bits in DQS group are checked in aggregate
474 
  generate
475 
    genvar mux_i;
476 
    for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
477 
      always @(posedge clk) begin
478 
        mux_rd_rise0_r1[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
479 
        mux_rd_fall0_r1[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
480 
        mux_rd_rise1_r1[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
481 
        mux_rd_fall1_r1[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
482 
        mux_rd_rise2_r1[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
483 
        mux_rd_fall2_r1[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
484 
        mux_rd_rise3_r1[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
485 
        mux_rd_fall3_r1[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
486 
        //Compare data
487 
        compare_data_rise0_r1[mux_i]  <= #TCQ compare_data_r0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
488 
        compare_data_fall0_r1[mux_i]  <= #TCQ compare_data_f0[DRAM_WIDTH*rd_mux_sel_r + mux_i];
489 
        compare_data_rise1_r1[mux_i]  <= #TCQ compare_data_r1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
490 
        compare_data_fall1_r1[mux_i]  <= #TCQ compare_data_f1[DRAM_WIDTH*rd_mux_sel_r + mux_i];
491 
        compare_data_rise2_r1[mux_i]  <= #TCQ compare_data_r2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
492 
        compare_data_fall2_r1[mux_i]  <= #TCQ compare_data_f2[DRAM_WIDTH*rd_mux_sel_r + mux_i];
493 
        compare_data_rise3_r1[mux_i]  <= #TCQ compare_data_r3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
494 
        compare_data_fall3_r1[mux_i]  <= #TCQ compare_data_f3[DRAM_WIDTH*rd_mux_sel_r + mux_i];
495 
      end
496 
    end
497 
  endgenerate
498 
 
499 
  generate
500 
    genvar muxr2_i;
501 
    if (nCK_PER_CLK == 4) begin: gen_mux_div4
502 
        for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_4
503 
          always @(posedge clk) begin
504 
            if (mux_rd_valid_r) begin
505 
              mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];
506 
              mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];
507 
              mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];
508 
              mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i];
509 
              mux_rd_rise2_r2[muxr2_i] <= #TCQ mux_rd_rise2_r1[muxr2_i];
510 
              mux_rd_fall2_r2[muxr2_i] <= #TCQ mux_rd_fall2_r1[muxr2_i];
511 
              mux_rd_rise3_r2[muxr2_i] <= #TCQ mux_rd_rise3_r1[muxr2_i];
512 
              mux_rd_fall3_r2[muxr2_i] <= #TCQ mux_rd_fall3_r1[muxr2_i];
513 
            end
514 
           //pipeline stage
515 
            mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];
516 
            mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];
517 
            mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];
518 
            mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];
519 
            mux_rd_rise2_r3[muxr2_i] <= #TCQ mux_rd_rise2_r2[muxr2_i];
520 
            mux_rd_fall2_r3[muxr2_i] <= #TCQ mux_rd_fall2_r2[muxr2_i];
521 
            mux_rd_rise3_r3[muxr2_i] <= #TCQ mux_rd_rise3_r2[muxr2_i];
522 
            mux_rd_fall3_r3[muxr2_i] <= #TCQ mux_rd_fall3_r2[muxr2_i];
523 
          //pipeline stage
524 
            mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];
525 
            mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];
526 
            mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];
527 
            mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];
528 
            mux_rd_rise2_r4[muxr2_i] <= #TCQ mux_rd_rise2_r3[muxr2_i];
529 
            mux_rd_fall2_r4[muxr2_i] <= #TCQ mux_rd_fall2_r3[muxr2_i];
530 
            mux_rd_rise3_r4[muxr2_i] <= #TCQ mux_rd_rise3_r3[muxr2_i];
531 
            mux_rd_fall3_r4[muxr2_i] <= #TCQ mux_rd_fall3_r3[muxr2_i];
532 
          end
533 
                end
534 
    end else if (nCK_PER_CLK == 2) begin: gen_mux_div2
535 
        for (muxr2_i = 0; muxr2_i < DRAM_WIDTH; muxr2_i = muxr2_i + 1) begin: gen_rd_2
536 
          always @(posedge clk) begin
537 
            if (mux_rd_valid_r) begin
538 
              mux_rd_rise0_r2[muxr2_i] <= #TCQ mux_rd_rise0_r1[muxr2_i];
539 
              mux_rd_fall0_r2[muxr2_i] <= #TCQ mux_rd_fall0_r1[muxr2_i];
540 
              mux_rd_rise1_r2[muxr2_i] <= #TCQ mux_rd_rise1_r1[muxr2_i];
541 
              mux_rd_fall1_r2[muxr2_i] <= #TCQ mux_rd_fall1_r1[muxr2_i];
542 
              mux_rd_rise2_r2[muxr2_i] <= 'h0;
543 
              mux_rd_fall2_r2[muxr2_i] <= 'h0;
544 
              mux_rd_rise3_r2[muxr2_i] <= 'h0;
545 
              mux_rd_fall3_r2[muxr2_i] <= 'h0;
546 
            end
547 
            mux_rd_rise0_r3[muxr2_i] <= #TCQ mux_rd_rise0_r2[muxr2_i];
548 
            mux_rd_fall0_r3[muxr2_i] <= #TCQ mux_rd_fall0_r2[muxr2_i];
549 
            mux_rd_rise1_r3[muxr2_i] <= #TCQ mux_rd_rise1_r2[muxr2_i];
550 
            mux_rd_fall1_r3[muxr2_i] <= #TCQ mux_rd_fall1_r2[muxr2_i];
551 
            mux_rd_rise2_r3[muxr2_i] <= 'h0;
552 
            mux_rd_fall2_r3[muxr2_i] <= 'h0;
553 
            mux_rd_rise3_r3[muxr2_i] <= 'h0;
554 
            mux_rd_fall3_r3[muxr2_i] <= 'h0;
555 
 
556 
            //pipeline stage
557 
            mux_rd_rise0_r4[muxr2_i] <= #TCQ mux_rd_rise0_r3[muxr2_i];
558 
            mux_rd_fall0_r4[muxr2_i] <= #TCQ mux_rd_fall0_r3[muxr2_i];
559 
            mux_rd_rise1_r4[muxr2_i] <= #TCQ mux_rd_rise1_r3[muxr2_i];
560 
            mux_rd_fall1_r4[muxr2_i] <= #TCQ mux_rd_fall1_r3[muxr2_i];
561 
            mux_rd_rise2_r4[muxr2_i] <= 'h0;
562 
            mux_rd_fall2_r4[muxr2_i] <= 'h0;
563 
            mux_rd_rise3_r4[muxr2_i] <= 'h0;
564 
            mux_rd_fall3_r4[muxr2_i] <= 'h0;
565 
          end
566 
        end
567 
    end
568 
  endgenerate
569 
 
570 
 
571 
  // Registered signal indicates when mux_rd_rise/fall_r is valid
572 
  always @(posedge clk) begin
573 
    mux_rd_valid_r <= #TCQ ~phy_if_empty && prbs_rdlvl_start;
574 
    rd_valid_r1    <= #TCQ mux_rd_valid_r;
575 
    rd_valid_r2    <= #TCQ rd_valid_r1;
576 
    rd_valid_r3    <= #TCQ rd_valid_r2;
577 
  end
578 
 
579 
 
580 
 
581 
 
582 
// Counter counts # of samples compared
583 
// Reset sample counter when not "sampling"
584 
// Otherwise, count # of samples compared
585 
// Same counter is shared for three samples checked
586 
  always @(posedge clk)
587 
    if (rst)
588 
      samples_cnt_r <= #TCQ 'b0;
589 
    else if (samples_cnt_r == NUM_SAMPLES_CNT) begin
590 
      samples_cnt_r <= #TCQ 'b0;
591 
    end else if (complex_sample_cnt_inc) begin
592 
      samples_cnt_r <= #TCQ samples_cnt_r + 1;
593 
      /*if (!rd_valid_r1 ||
594 
          (prbs_state_r == PRBS_DEC_DQS_WAIT) ||
595 
          (prbs_state_r == PRBS_INC_DQS_WAIT) ||
596 
          (prbs_state_r == PRBS_DEC_DQS) ||
597 
          (prbs_state_r == PRBS_INC_DQS) ||
598 
          (samples_cnt_r == NUM_SAMPLES_CNT) ||
599 
          (samples_cnt_r == NUM_SAMPLES_CNT1))
600 
        samples_cnt_r <= #TCQ 'b0;
601 
      else if (rd_valid_r1 &&
602 
               (((samples_cnt_r < NUM_SAMPLES_CNT) && ~samples_cnt1_en_r) ||
603 
                ((samples_cnt_r < NUM_SAMPLES_CNT1) && ~samples_cnt2_en_r) ||
604 
                ((samples_cnt_r < NUM_SAMPLES_CNT2) && samples_cnt2_en_r)))
605 
        samples_cnt_r <= #TCQ samples_cnt_r + 1;*/
606 
    end
607 
 
608 
// Count #2 enable generation
609 
// Assert when correct number of samples compared
610 
  always @(posedge clk)
611 
    if (rst)
612 
      samples_cnt1_en_r <= #TCQ 1'b0;
613 
    else begin
614 
      if ((prbs_state_r == PRBS_IDLE) ||
615 
          (prbs_state_r == PRBS_DEC_DQS) ||
616 
          (prbs_state_r == PRBS_INC_DQS) ||
617 
          (prbs_state_r == FINE_PI_INC) ||
618 
          (prbs_state_r == PRBS_NEW_DQS_PREWAIT))
619 
        samples_cnt1_en_r <= #TCQ 1'b0;
620 
      else if ((samples_cnt_r == NUM_SAMPLES_CNT) && rd_valid_r1)
621 
        samples_cnt1_en_r <= #TCQ 1'b1;
622 
    end
623 
 
624 
// Counter #3 enable generation
625 
// Assert when correct number of samples compared
626 
  always @(posedge clk)
627 
    if (rst)
628 
      samples_cnt2_en_r <= #TCQ 1'b0;
629 
    else begin
630 
      if ((prbs_state_r == PRBS_IDLE) ||
631 
          (prbs_state_r == PRBS_DEC_DQS) ||
632 
          (prbs_state_r == PRBS_INC_DQS) ||
633 
          (prbs_state_r == FINE_PI_INC) ||
634 
          (prbs_state_r == PRBS_NEW_DQS_PREWAIT))
635 
        samples_cnt2_en_r <= #TCQ 1'b0;
636 
      else if ((samples_cnt_r == NUM_SAMPLES_CNT1) && rd_valid_r1 && samples_cnt1_en_r)
637 
        samples_cnt2_en_r <= #TCQ 1'b1;
638 
    end
639 
 
640 
// Victim selection logic
641 
  always @(posedge clk)
642 
    if (rst)
643 
      rd_victim_sel    <= #TCQ 'd0;
644 
    else if (num_samples_done_r)
645 
      rd_victim_sel    <= #TCQ 'd0;
646 
    else if (samples_cnt_r == NUM_SAMPLES_CNT) begin
647 
      if (rd_victim_sel < 'd7)
648 
        rd_victim_sel    <= #TCQ rd_victim_sel + 1;
649 
    end
650 
 
651 
// Output row count increment pulse to phy_init
652 
  always @(posedge clk)
653 
    if (rst)
654 
      complex_victim_inc <= #TCQ 1'b0;
655 
    else if (samples_cnt_r == NUM_SAMPLES_CNT)
656 
      complex_victim_inc <= #TCQ 1'b1;
657 
    else
658 
      complex_victim_inc <= #TCQ 1'b0;
659 
 
660 
generate
661 
  if (FIXED_VICTIM == "TRUE") begin: victim_fixed
662 
    always @(posedge clk)
663 
      if (rst)
664 
        num_samples_done_r <= #TCQ 1'b0;
665 
      else if ((prbs_state_r == PRBS_DEC_DQS) ||
666 
            (prbs_state_r == PRBS_INC_DQS)||
667 
            (prbs_state_r == FINE_PI_INC) ||
668 
            (prbs_state_r == FINE_PI_DEC))
669 
        num_samples_done_r <= #TCQ 'b0;
670 
      else if (samples_cnt_r == NUM_SAMPLES_CNT)
671 
        num_samples_done_r <= #TCQ 1'b1;
672 
  end else begin: victim_not_fixed
673 
    always @(posedge clk)
674 
      if (rst)
675 
        num_samples_done_r <= #TCQ 1'b0;
676 
      else if ((prbs_state_r == PRBS_DEC_DQS) ||
677 
            (prbs_state_r == PRBS_INC_DQS)||
678 
            (prbs_state_r == FINE_PI_INC) ||
679 
            (prbs_state_r == FINE_PI_DEC))
680 
        num_samples_done_r <= #TCQ 'b0;
681 
      else if ((samples_cnt_r == NUM_SAMPLES_CNT) && (rd_victim_sel == 'd7))
682 
        num_samples_done_r <= #TCQ 1'b1;
683 
  end
684 
endgenerate
685 
 
686 
 
687 
  //***************************************************************************
688 
  // Compare Read Data for the byte being Leveled with Expected data from PRBS
689 
  // generator. Resulting compare_err signal used to determine read data valid
690 
  // edge.
691 
  //***************************************************************************
692 
  generate
693 
    if (nCK_PER_CLK == 4) begin: cmp_err_4to1
694 
      always @ (posedge clk) begin
695 
        if (rst || new_cnt_dqs_r) begin
696 
              compare_err    <= #TCQ 1'b0;
697 
              compare_err_r0 <= #TCQ 1'b0;
698 
              compare_err_f0 <= #TCQ 1'b0;
699 
              compare_err_r1 <= #TCQ 1'b0;
700 
              compare_err_f1 <= #TCQ 1'b0;
701 
              compare_err_r2 <= #TCQ 1'b0;
702 
              compare_err_f2 <= #TCQ 1'b0;
703 
              compare_err_r3 <= #TCQ 1'b0;
704 
              compare_err_f3 <= #TCQ 1'b0;
705 
            end else if (rd_valid_r2) begin
706 
              compare_err_r0  <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);
707 
              compare_err_f0  <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);
708 
              compare_err_r1  <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);
709 
              compare_err_f1  <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);
710 
              compare_err_r2  <= #TCQ (mux_rd_rise2_r3 != compare_data_rise2_r1);
711 
              compare_err_f2  <= #TCQ (mux_rd_fall2_r3 != compare_data_fall2_r1);
712 
              compare_err_r3  <= #TCQ (mux_rd_rise3_r3 != compare_data_rise3_r1);
713 
              compare_err_f3  <= #TCQ (mux_rd_fall3_r3 != compare_data_fall3_r1);
714 
              compare_err     <= #TCQ (compare_err_r0 | compare_err_f0 |
715 
                                       compare_err_r1 | compare_err_f1 |
716 
                                                           compare_err_r2 | compare_err_f2 |
717 
                                                           compare_err_r3 | compare_err_f3);
718 
            end
719 
      end
720 
        end else begin: cmp_err_2to1
721 
          always @ (posedge clk) begin
722 
        if (rst || new_cnt_dqs_r) begin
723 
              compare_err    <= #TCQ 1'b0;
724 
              compare_err_r0 <= #TCQ 1'b0;
725 
              compare_err_f0 <= #TCQ 1'b0;
726 
              compare_err_r1 <= #TCQ 1'b0;
727 
              compare_err_f1 <= #TCQ 1'b0;
728 
            end else if (rd_valid_r2) begin
729 
              compare_err_r0  <= #TCQ (mux_rd_rise0_r3 != compare_data_rise0_r1);
730 
              compare_err_f0  <= #TCQ (mux_rd_fall0_r3 != compare_data_fall0_r1);
731 
              compare_err_r1  <= #TCQ (mux_rd_rise1_r3 != compare_data_rise1_r1);
732 
              compare_err_f1  <= #TCQ (mux_rd_fall1_r3 != compare_data_fall1_r1);
733 
              compare_err     <= #TCQ (compare_err_r0 | compare_err_f0 |
734 
                                       compare_err_r1 | compare_err_f1);
735 
            end
736 
      end
737 
        end
738 
  endgenerate
739 
 
740 
//***************************************************************************
741 
// Decrement initial Phaser_IN fine delay value before proceeding with
742 
// read calibration
743 
//***************************************************************************
744 
 
745 
 
746 
//***************************************************************************
747 
// Demultiplexor to control Phaser_IN delay values
748 
//***************************************************************************
749 
 
750 
// Read DQS
751 
  always @(posedge clk) begin
752 
    if (rst) begin
753 
      pi_en_stg2_f_timing     <= #TCQ 'b0;
754 
      pi_stg2_f_incdec_timing <= #TCQ 'b0;
755 
    end else if (prbs_tap_en_r) begin
756 
// Change only specified DQS
757 
      pi_en_stg2_f_timing     <= #TCQ 1'b1;
758 
      pi_stg2_f_incdec_timing <= #TCQ prbs_tap_inc_r;
759 
    end else begin
760 
      pi_en_stg2_f_timing     <= #TCQ 'b0;
761 
      pi_stg2_f_incdec_timing <= #TCQ 'b0;
762 
    end
763 
  end
764 
 
765 
// registered for timing
766 
  always @(posedge clk) begin
767 
    pi_en_stg2_f     <= #TCQ pi_en_stg2_f_timing;
768 
    pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing;
769 
  end
770 
 
771 
//***************************************************************************
772 
// generate request to PHY_INIT logic to issue precharged. Required when
773 
// calibration can take a long time (during which there are only constant
774 
// reads present on this bus). In this case need to issue perioidic
775 
// precharges to avoid tRAS violation. This signal must meet the following
776 
// requirements: (1) only transition from 0->1 when prech is first needed,
777 
// (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
778 
//***************************************************************************
779 
 
780 
  always @(posedge clk)
781 
    if (rst)
782 
      prbs_rdlvl_prech_req <= #TCQ 1'b0;
783 
    else
784 
      prbs_rdlvl_prech_req <= #TCQ prbs_prech_req_r;
785 
 
786 
//*****************************************************************
787 
// keep track of edge tap counts found, and current capture clock
788 
// tap count
789 
//*****************************************************************
790 
 
791 
  always @(posedge clk)
792 
    if (rst) begin
793 
      prbs_dqs_tap_cnt_r   <= #TCQ 'b0;
794 
      rdlvl_cpt_tap_cnt    <= #TCQ 'b0;
795 
    end else if (new_cnt_dqs_r) begin
796 
      prbs_dqs_tap_cnt_r   <= #TCQ pi_counter_read_val;
797 
      rdlvl_cpt_tap_cnt    <= #TCQ pi_counter_read_val;
798 
    end else if (prbs_tap_en_r) begin
799 
      if (prbs_tap_inc_r)
800 
        prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r + 1;
801 
      else if (prbs_dqs_tap_cnt_r != 'd0)
802 
        prbs_dqs_tap_cnt_r <= #TCQ prbs_dqs_tap_cnt_r - 1;
803 
    end
804 
 
805 
  always @(posedge clk)
806 
    if (rst) begin
807 
      prbs_dec_tap_calc_plus_3  <= #TCQ 'b0;
808 
      prbs_dec_tap_calc_minus_3 <= #TCQ 'b0;
809 
    end else if (new_cnt_dqs_r) begin
810 
      prbs_dec_tap_calc_plus_3  <= #TCQ 'b000011;
811 
      prbs_dec_tap_calc_minus_3 <= #TCQ 'b111100;
812 
    end else begin
813 
      prbs_dec_tap_calc_plus_3  <= #TCQ (prbs_dqs_tap_cnt_r  - rdlvl_cpt_tap_cnt + 3);
814 
      prbs_dec_tap_calc_minus_3 <= #TCQ (prbs_dqs_tap_cnt_r  - rdlvl_cpt_tap_cnt - 3);
815 
    end
816 
 
817 
  always @(posedge clk)
818 
    if (rst || new_cnt_dqs_r)
819 
      prbs_dqs_tap_limit_r <= #TCQ 1'b0;
820 
    else if (prbs_dqs_tap_cnt_r == 6'd63)
821 
      prbs_dqs_tap_limit_r <= #TCQ 1'b1;
822 
    else
823 
      prbs_dqs_tap_limit_r <= #TCQ 1'b0;
824 
 
825 
  // Temp wire for timing.
826 
   // The following in the always block below causes timing issues
827 
   // due to DSP block inference
828 
   // 6*prbs_dqs_cnt_r.
829 
   // replacing this with two left shifts + one left shift  to avoid
830 
   // DSP multiplier.
831 
 
832 
  assign prbs_dqs_cnt_timing = {2'd0, prbs_dqs_cnt_r};
833 
 
834 
 
835 
  always @(posedge clk)
836 
    prbs_dqs_cnt_timing_r <= #TCQ prbs_dqs_cnt_timing;
837 
 
838 
 
839 
   // Storing DQS tap values at the end of each DQS read leveling
840 
   always @(posedge clk) begin
841 
     if (rst) begin
842 
       prbs_final_dqs_tap_cnt_r <= #TCQ 'b0;
843 
     end else if ((prbs_state_r == PRBS_NEXT_DQS) && (prbs_state_r1 != PRBS_NEXT_DQS)) begin
844 
        prbs_final_dqs_tap_cnt_r[(prbs_dqs_cnt_timing_r*6)+:6]
845 
           <= #TCQ prbs_dqs_tap_cnt_r;
846 
     end
847 
   end
848 
 
849 
 
850 
 
851 
 
852 
  //*****************************************************************
853 
 
854 
  always @(posedge clk) begin
855 
    prbs_state_r1      <= #TCQ prbs_state_r;
856 
    prbs_rdlvl_start_r <= #TCQ prbs_rdlvl_start;
857 
  end
858 
 
859 
// Wait counter for wait states
860 
  always @(posedge clk)
861 
    if ((prbs_state_r == PRBS_NEW_DQS_WAIT) ||
862 
        (prbs_state_r == PRBS_INC_DQS_WAIT) ||
863 
        (prbs_state_r == PRBS_DEC_DQS_WAIT) ||
864 
        (prbs_state_r == FINE_PI_DEC_WAIT)  ||
865 
        (prbs_state_r == FINE_PI_INC_WAIT)  ||
866 
        (prbs_state_r == PRBS_NEW_DQS_PREWAIT))
867 
      wait_state_cnt_en_r <= #TCQ 1'b1;
868 
    else
869 
      wait_state_cnt_en_r <= #TCQ 1'b0;
870 
 
871 
  always @(posedge clk)
872 
    if (!wait_state_cnt_en_r) begin
873 
      wait_state_cnt_r <= #TCQ 'b0;
874 
      cnt_wait_state   <= #TCQ 1'b0;
875 
    end else begin
876 
      if (wait_state_cnt_r < 'd15) begin
877 
        wait_state_cnt_r <= #TCQ wait_state_cnt_r + 1;
878 
        cnt_wait_state   <= #TCQ 1'b0;
879 
      end else begin
880 
        // Need to reset to 0 to handle the case when there are two
881 
        // different WAIT states back-to-back
882 
        wait_state_cnt_r <= #TCQ 'b0;
883 
        cnt_wait_state   <= #TCQ 1'b1;
884 
      end
885 
    end
886 
 
887 
  always @ (posedge clk)
888 
    err_chk_invalid <= #TCQ (wait_state_cnt_r < 'd14);
889 
 
890 
 
891 
//*****************************************************************
892 
// compare error checking per-bit
893 
//****************************************************************
894 
 
895 
  generate
896 
    genvar pb_i;
897 
    if (nCK_PER_CLK == 4) begin: cmp_err_pb_4to1
898 
      for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin
899 
        always @ (posedge clk) begin
900 
          //prevent error check during PI inc/dec and wait
901 
          if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) ||
902 
         (err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT))))
903 
            compare_err_pb[pb_i]  <= #TCQ 1'b0;
904 
          else if (rd_valid_r2)
905 
            compare_err_pb[pb_i]  <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) |
906 
                                          (mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) |
907 
                                          (mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) |
908 
                                          (mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) |
909 
                                          (mux_rd_rise2_r3[pb_i] != compare_data_rise2_r1[pb_i]) |
910 
                                          (mux_rd_fall2_r3[pb_i] != compare_data_fall2_r1[pb_i]) |
911 
                                          (mux_rd_rise3_r3[pb_i] != compare_data_rise3_r1[pb_i]) |
912 
                                          (mux_rd_fall3_r3[pb_i] != compare_data_fall3_r1[pb_i]) ;
913 
        end //always
914 
      end  //for
915 
    end else begin: cmp_err_pb_2to1
916 
      for(pb_i=0 ; pb_i<DRAM_WIDTH; pb_i=pb_i+1) begin
917 
        always @ (posedge clk) begin
918 
          if (rst || new_cnt_dqs_r || (prbs_state_r == FINE_PI_INC) || (prbs_state_r == FINE_PI_DEC) ||
919 
          (err_chk_invalid && ((prbs_state_r == FINE_PI_DEC_WAIT)||(prbs_state_r == FINE_PI_INC_WAIT))))
920 
            compare_err_pb[pb_i]  <= #TCQ 1'b0;
921 
          else if (rd_valid_r2)
922 
            compare_err_pb[pb_i]  <= #TCQ (mux_rd_rise0_r3[pb_i] != compare_data_rise0_r1[pb_i]) |
923 
                                          (mux_rd_fall0_r3[pb_i] != compare_data_fall0_r1[pb_i]) |
924 
                                          (mux_rd_rise1_r3[pb_i] != compare_data_rise1_r1[pb_i]) |
925 
                                          (mux_rd_fall1_r3[pb_i] != compare_data_fall1_r1[pb_i]) ;
926 
        end //always
927 
      end  //for
928 
    end  //if
929 
  endgenerate
930 
 
931 
  //checking all bit has error
932 
  always @ (posedge clk) begin
933 
    if(rst || new_cnt_dqs_r) begin
934 
      compare_err_pb_and <= #TCQ 1'b0;
935 
    end else begin
936 
      compare_err_pb_and <= #TCQ &compare_err_pb;
937 
    end
938 
  end
939 
 
940 
  //generate stick error bit - left/right edge
941 
  generate
942 
  genvar pb_r;
943 
    for(pb_r=0; pb_r<DRAM_WIDTH; pb_r=pb_r+1) begin
944 
      always @ (posedge clk) begin
945 
        if((prbs_state_r == FINE_PI_INC) | (prbs_state_r == FINE_PI_DEC) |
946 
          (~cnt_wait_state && ((prbs_state_r == FINE_PI_INC_WAIT)|(prbs_state_r == FINE_PI_DEC_WAIT))))
947 
          compare_err_pb_latch_r[pb_r] <= #TCQ 1'b0;
948 
        else
949 
          compare_err_pb_latch_r[pb_r] <= #TCQ compare_err_pb[pb_r]? 1'b1:compare_err_pb_latch_r[pb_r];
950 
      end
951 
    end
952 
  endgenerate
953 
 
954 
  //in stage 0, if left edge found, update ref_bit (one hot)
955 
  always @ (posedge clk) begin
956 
    if (rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
957 
      ref_bit_per_bit <= #TCQ 'd0;
958 
    end else if ((prbs_state_r == FINE_PI_INC) && (stage_cnt=='b0)) begin
959 
      if(|left_edge_updated) ref_bit_per_bit <= #TCQ left_edge_updated;
960 
    end
961 
  end
962 
 
963 
  //ref bit with samllest right edge
964 
  //if bit 1 and 3 are set to ref_bit_per_bit but bit 1 has smaller right edge, bit is selected as ref_bit
965 
  always @ (posedge clk) begin
966 
    if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
967 
      bit_cnt <= #TCQ 'd0;
968 
      ref_right_edge <= #TCQ 6'h3f;
969 
      ref_bit <= #TCQ 'd0;
970 
    end else if ((prbs_state_r == FINE_CALC_TAPS_WAIT) && (stage_cnt == 'b0) && (bit_cnt < DRAM_WIDTH)) begin
971 
      bit_cnt <= #TCQ bit_cnt +'b1;
972 
      if ((ref_bit_per_bit[bit_cnt]==1'b1) && (right_edge_pb[bit_cnt*6+:6]<= ref_right_edge)) begin
973 
        ref_bit <= #TCQ bit_cnt;
974 
        ref_right_edge <= #TCQ right_edge_pb[bit_cnt*6+:6];
975 
      end
976 
    end
977 
  end
978 
 
979 
  //pipe lining for reference bit left/right edge
980 
  always @ (posedge clk) begin
981 
    left_edge_ref <= #TCQ left_edge_pb[ref_bit*6+:6];
982 
    right_edge_ref <= #TCQ right_edge_pb[ref_bit*6+:6];
983 
  end
984 
 
985 
  //left_edge/right_edge/left_loss/right_gain update
986 
  generate
987 
  genvar eg;
988 
  for(eg=0; eg<DRAM_WIDTH; eg = eg+1) begin
989 
    always @ (posedge clk) begin
990 
      if(rst | (prbs_state_r == PRBS_NEW_DQS_WAIT)) begin
991 
        match_flag_pb[eg*5+:5] <= #TCQ 5'h1f;
992 
        left_edge_pb[eg*6+:6] <= #TCQ 'b0;
993 
        right_edge_pb[eg*6+:6] <= #TCQ 6'h3f;
994 
        left_edge_found_pb[eg] <= #TCQ 1'b0;
995 
        right_edge_found_pb[eg] <= #TCQ 1'b0;
996 
        left_loss_pb[eg*6+:6] <= #TCQ 'b0;
997 
        right_gain_pb[eg*6+:6] <= #TCQ 'b0;
998 
        left_edge_updated[eg]  <= #TCQ 'b0;
999 
      end else begin
1000 
        if((prbs_state_r == FINE_PAT_COMPARE_PER_BIT) && (num_samples_done_r || compare_err_pb_and)) begin
1001 
            //left edge is updated when match flag becomes 100000 (1 fail , 5 success)
1002 
            if(match_flag_pb[eg*5+:5]==5'b10000 && compare_err_pb_latch_r[eg]==0) begin
1003 
              left_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-4;
1004 
              left_edge_found_pb[eg] <= #TCQ 1'b1;  //used for update largest_left_edge
1005 
              left_edge_updated[eg] <= #TCQ 1'b1;
1006 
              //check the loss of bit - update only for left edge found
1007 
              if(~left_edge_found_pb[eg])
1008 
                left_loss_pb[eg*6+:6] <= #TCQ (left_edge_ref > prbs_dqs_tap_cnt_r - 4)? 'd0
1009 
                                 : prbs_dqs_tap_cnt_r-4-left_edge_ref;
1010 
            //right edge is updated when match flag becomes 000001 (5 success, 1 fail)
1011 
            end else if (match_flag_pb[eg*5+:5]==5'b00000 && compare_err_pb_latch_r[eg]) begin
1012 
               right_edge_pb[eg*6+:6] <= #TCQ prbs_dqs_tap_cnt_r-1;
1013 
               right_edge_found_pb[eg] <= #TCQ 1'b1;
1014 
               //check the gain of bit - update only for right edge found
1015 
               if(~right_edge_found_pb[eg])
1016 
                 right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > prbs_dqs_tap_cnt_r-1)?
1017 
                                           ((right_edge_pb[eg*6 +:6] > prbs_dqs_tap_cnt_r-1)? 0: prbs_dqs_tap_cnt_r-1- right_edge_pb[eg*6+:6]):
1018 
                                           ((right_edge_pb[eg*6+:6] > right_edge_ref)? 0 : right_edge_ref - right_edge_pb[eg*6+:6]);
1019 
           //no right edge found
1020 
           end else if (prbs_dqs_tap_cnt_r == 6'h3f && ~right_edge_found_pb[eg]) begin
1021 
             right_edge_pb[eg*6+:6] <= #TCQ 6'h3f;
1022 
             right_edge_found_pb[eg] <= #TCQ 1'b1;
1023 
             //right edge at 63. gain = max(0, ref_bit_right_tap - prev_right_edge)
1024 
             right_gain_pb[eg*6+:6] <= #TCQ (right_edge_ref > right_edge_pb[eg*6+:6])?
1025 
                                   (right_edge_ref - right_edge_pb[eg*6+:6]) : 0;
1026 
           end
1027 
           //update match flag - shift and update
1028 
           match_flag_pb[eg*5+:5] <= #TCQ {match_flag_pb[(eg*5)+:4],compare_err_pb_latch_r[eg]};
1029 
         end else if (prbs_state_r == FINE_PI_DEC) begin
1030 
           left_edge_found_pb[eg] <= #TCQ 1'b0;
1031 
           right_edge_found_pb[eg] <= #TCQ 1'b0;
1032 
           left_loss_pb[eg*6+:6] <= #TCQ 'b0;
1033 
           right_gain_pb[eg*6+:6] <= #TCQ 'b0;
1034 
           match_flag_pb[eg*5+:5] <= #TCQ 5'h1f;  //new fix
1035 
         end else if (prbs_state_r == FINE_PI_INC) begin
1036 
           left_edge_updated[eg] <= #TCQ 'b0;   //used only for update largest ref_bit and largest_left_edge
1037 
         end
1038 
       end
1039 
     end  //always
1040 
   end //for
1041 
   endgenerate
1042 
 
1043 
   //update fine_delay according to loss/gain value per bit
1044 
   generate
1045 
   genvar f_pb;
1046 
   for(f_pb=0; f_pb<DRAM_WIDTH; f_pb=f_pb+1) begin
1047 
     always @ (posedge clk) begin
1048 
       if(rst | prbs_state_r == PRBS_NEW_DQS_WAIT ) begin
1049 
         fine_delay_incdec_pb[f_pb] <= #TCQ 1'b0;
1050 
       end else if((prbs_state_r == FINE_CALC_TAPS_WAIT) && (bit_cnt == DRAM_WIDTH)) begin
1051 
         if(stage_cnt == 'd0) fine_delay_incdec_pb[f_pb] <= #TCQ (f_pb==ref_bit)? 1'b0:1'b1;  //only for initial stage
1052 
         else if(stage_cnt == 'd1) fine_delay_incdec_pb[f_pb] <= #TCQ (right_gain_pb[f_pb*6+:6]>left_loss_pb[f_pb*6+:6])?1'b1:1'b0;
1053 
       end
1054 
     end
1055 
   end
1056 
   endgenerate
1057 
 
1058 
   //fine inc stage (stage cnt 0,1,2), fine dec stage (stage cnt 3)
1059 
   always @ (posedge clk) begin
1060 
     if (rst)
1061 
       fine_inc_stage <= #TCQ 'b1;
1062 
     else
1063 
       fine_inc_stage <= #TCQ (stage_cnt!='d3);
1064 
   end
1065 
//*****************************************************************
1066 
 
1067 
  always @(posedge clk)
1068 
    if (rst) begin
1069 
      prbs_dqs_cnt_r        <= #TCQ 'b0;
1070 
      prbs_tap_en_r         <= #TCQ 1'b0;
1071 
      prbs_tap_inc_r        <= #TCQ 1'b0;
1072 
      prbs_prech_req_r      <= #TCQ 1'b0;
1073 
      prbs_state_r          <= #TCQ PRBS_IDLE;
1074 
      prbs_found_1st_edge_r <= #TCQ 1'b0;
1075 
      prbs_found_2nd_edge_r <= #TCQ 1'b0;
1076 
      prbs_1st_edge_taps_r  <= #TCQ 6'bxxxxxx;
1077 
      prbs_inc_tap_cnt      <= #TCQ 'b0;
1078 
      prbs_dec_tap_cnt      <= #TCQ 'b0;
1079 
      new_cnt_dqs_r         <= #TCQ 1'b0;
1080 
      if (SIM_CAL_OPTION == "FAST_CAL")
1081 
        prbs_rdlvl_done       <= #TCQ 1'b1;
1082 
      else
1083 
        prbs_rdlvl_done       <= #TCQ 1'b0;
1084 
      prbs_2nd_edge_taps_r  <= #TCQ 6'bxxxxxx;
1085 
      prbs_last_byte_done   <= #TCQ 1'b0;
1086 
      prbs_tap_mod          <= #TCQ 'd0;
1087 
      reset_rd_addr         <= #TCQ 'b0;
1088 
      read_pause            <= #TCQ 'b0;
1089 
      fine_pi_dec_cnt       <= #TCQ 'b0;
1090 
      match_flag_and        <= #TCQ 5'h1f;
1091 
      stage_cnt             <= #TCQ 2'b00;
1092 
      right_edge_found      <= #TCQ 1'b0;
1093 
      largest_left_edge     <= #TCQ 6'b000000;
1094 
      smallest_right_edge   <= #TCQ 6'b111111;
1095 
      num_samples_done_ind  <= #TCQ 'b0;
1096 
      fine_delay_sel        <= #TCQ 'b0;
1097 
      fine_dly_error        <= #TCQ 'b0;
1098 
    end else begin
1099 
 
1100 
      case (prbs_state_r)
1101 
 
1102 
        PRBS_IDLE: begin
1103 
          prbs_last_byte_done  <= #TCQ 1'b0;
1104 
          prbs_prech_req_r     <= #TCQ 1'b0;
1105 
          if (prbs_rdlvl_start && ~prbs_rdlvl_start_r) begin
1106 
            if (SIM_CAL_OPTION == "SKIP_CAL" || SIM_CAL_OPTION == "FAST_CAL") begin
1107 
              prbs_state_r  <= #TCQ PRBS_DONE;
1108 
              reset_rd_addr <= #TCQ 1'b1;
1109 
            end else begin
1110 
              new_cnt_dqs_r <= #TCQ 1'b1;
1111 
              prbs_state_r  <= #TCQ PRBS_NEW_DQS_WAIT;
1112 
              fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
1113 
            end
1114 
          end
1115 
        end
1116 
 
1117 
        // Wait for the new DQS group to change
1118 
        // also gives time for the read data IN_FIFO to
1119 
        // output the updated data for the new DQS group
1120 
        PRBS_NEW_DQS_WAIT: begin
1121 
          reset_rd_addr <= #TCQ 'b0;
1122 
          prbs_last_byte_done <= #TCQ 1'b0;
1123 
          prbs_prech_req_r    <= #TCQ 1'b0;
1124 
          //fine_inc_stage      <= #TCQ 1'b1;
1125 
          stage_cnt           <= #TCQ 2'b0;
1126 
          match_flag_and        <= #TCQ 5'h1f;
1127 
          if (cnt_wait_state) begin
1128 
            new_cnt_dqs_r <= #TCQ 1'b0;
1129 
            prbs_state_r  <= #TCQ fine_calib? FINE_PI_DEC:PRBS_PAT_COMPARE;
1130 
          end
1131 
        end
1132 
 
1133 
        // Check for presence of data eye edge. During this state, we
1134 
        // sample the read data multiple times, and look for changes
1135 
        // in the read data, specifically:
1136 
        //   1. A change in the read data compared with the value of
1137 
        //      read data from the previous delay tap. This indicates
1138 
        //      that the most recent tap delay increment has moved us
1139 
        //      into either a new window, or moved/kept us in the
1140 
        //      transition/jitter region between windows. Note that this
1141 
        //      condition only needs to be checked for once, and for
1142 
        //      logistical purposes, we check this soon after entering
1143 
        //      this state (see comment in PRBS_PAT_COMPARE below for
1144 
        //      why this is done)
1145 
        //   2. A change in the read data while we are in this state
1146 
        //      (i.e. in the absence of a tap delay increment). This
1147 
        //      indicates that we're close enough to a window edge that
1148 
        //      jitter will cause the read data to change even in the
1149 
        //      absence of a tap delay change
1150 
        PRBS_PAT_COMPARE: begin
1151 
 
1152 
          // Continue to sample read data and look for edges until the
1153 
          // appropriate time interval (shorter for simulation-only,
1154 
          // much, much longer for actual h/w) has elapsed
1155 
          if (num_samples_done_r || compare_err) begin
1156 
            if (prbs_dqs_tap_limit_r)
1157 
              // Only one edge detected and ran out of taps since only one
1158 
              // bit time worth of taps available for window detection. This
1159 
              // can happen if at tap 0 DQS is in previous window which results
1160 
              // in only left edge being detected. Or at tap 0 DQS is in the
1161 
              // current window resulting in only right edge being detected.
1162 
              // Depending on the frequency this case can also happen if at
1163 
              // tap 0 DQS is in the left noise region resulting in only left
1164 
              // edge being detected.
1165 
              prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;
1166 
            else if (compare_err || (prbs_dqs_tap_cnt_r == 'd0)) begin
1167 
              // Sticky bit - asserted after we encounter an edge, although
1168 
              // the current edge may not be considered the "first edge" this
1169 
              // just means we found at least one edge
1170 
              prbs_found_1st_edge_r <= #TCQ 1'b1;
1171 
 
1172 
              // Both edges of data valid window found:
1173 
              // If we've found a second edge after a region of stability
1174 
              // then we must have just passed the second ("right" edge of
1175 
              // the window. Record this second_edge_taps = current tap-1,
1176 
              // because we're one past the actual second edge tap, where
1177 
              // the edge taps represent the extremes of the data valid
1178 
              // window (i.e. smallest & largest taps where data still valid
1179 
              if (prbs_found_1st_edge_r) begin
1180 
                prbs_found_2nd_edge_r <= #TCQ 1'b1;
1181 
                prbs_2nd_edge_taps_r  <= #TCQ prbs_dqs_tap_cnt_r - 1;
1182 
                prbs_state_r          <= #TCQ PRBS_CALC_TAPS_PRE;
1183 
              end else begin
1184 
                // Otherwise, an edge was found (just not the "second" edge)
1185 
                // Assuming DQS is in the correct window at tap 0 of Phaser IN
1186 
                // fine tap. The first edge found is the right edge of the valid
1187 
                // window and is the beginning of the jitter region hence done!
1188 
                if (compare_err)
1189 
                  prbs_1st_edge_taps_r <= #TCQ prbs_dqs_tap_cnt_r + 1;
1190 
                else
1191 
                  prbs_1st_edge_taps_r <= #TCQ 'd0;
1192 
 
1193 
                prbs_inc_tap_cnt     <= #TCQ rdlvl_cpt_tap_cnt - prbs_dqs_tap_cnt_r;
1194 
                prbs_state_r         <= #TCQ PRBS_INC_DQS;
1195 
              end
1196 
            end else begin
1197 
              // Otherwise, if we haven't found an edge....
1198 
              // If we still have taps left to use, then keep incrementing
1199 
              if (prbs_found_1st_edge_r)
1200 
                prbs_state_r  <= #TCQ PRBS_INC_DQS;
1201 
              else
1202 
                prbs_state_r  <= #TCQ PRBS_DEC_DQS;
1203 
            end
1204 
          end
1205 
        end
1206 
 
1207 
        // Increment Phaser_IN delay for DQS
1208 
        PRBS_INC_DQS: begin
1209 
          prbs_state_r        <= #TCQ PRBS_INC_DQS_WAIT;
1210 
          if (prbs_inc_tap_cnt > 'd0)
1211 
            prbs_inc_tap_cnt <= #TCQ prbs_inc_tap_cnt - 1;
1212 
          if (~prbs_dqs_tap_limit_r) begin
1213 
            prbs_tap_en_r    <= #TCQ 1'b1;
1214 
            prbs_tap_inc_r   <= #TCQ 1'b1;
1215 
          end
1216 
        end
1217 
 
1218 
        // Wait for Phaser_In to settle, before checking again for an edge
1219 
        PRBS_INC_DQS_WAIT: begin
1220 
          prbs_tap_en_r    <= #TCQ 1'b0;
1221 
          prbs_tap_inc_r   <= #TCQ 1'b0;
1222 
          if (cnt_wait_state) begin
1223 
            if (prbs_inc_tap_cnt > 'd0)
1224 
              prbs_state_r <= #TCQ PRBS_INC_DQS;
1225 
            else
1226 
              prbs_state_r <= #TCQ PRBS_PAT_COMPARE;
1227 
          end
1228 
        end
1229 
 
1230 
        // Calculate final value of Phaser_IN taps. At this point, one or both
1231 
        // edges of data eye have been found, and/or all taps have been
1232 
        // exhausted looking for the edges
1233 
        // NOTE: The amount to be decrement by is calculated, not the
1234 
        //  absolute setting for DQS.
1235 
        // CENTER compensation with shift by 1
1236 
        PRBS_CALC_TAPS: begin
1237 
          if (center_comp) begin
1238 
            prbs_dec_tap_cnt <= #TCQ (dec_cnt[5] & dec_cnt[0])? 'd32: dec_cnt + pi_adj;
1239 
            fine_dly_error <= #TCQ (dec_cnt[5] & dec_cnt[0])? 1'b1: fine_dly_error; //sticky bit
1240 
            read_pause <= #TCQ 'b1;
1241 
            prbs_state_r <= #TCQ PRBS_DEC_DQS;
1242 
          end else begin  //No center compensation
1243 
            if (prbs_found_2nd_edge_r && prbs_found_1st_edge_r)
1244 
            // Both edges detected
1245 
              prbs_dec_tap_cnt
1246 
                <=  #TCQ ((prbs_2nd_edge_taps_r -
1247 
                         prbs_1st_edge_taps_r)>>1) + 1 + pi_adj;
1248 
            else if (~prbs_found_2nd_edge_r && prbs_found_1st_edge_r)
1249 
            // Only left edge detected
1250 
              prbs_dec_tap_cnt
1251 
                <=  #TCQ ((prbs_dqs_tap_cnt_r - prbs_1st_edge_taps_r)>>1) + pi_adj;
1252 
            else
1253 
            // No edges detected
1254 
              prbs_dec_tap_cnt
1255 
                <=  #TCQ (prbs_dqs_tap_cnt_r>>1) + pi_adj;
1256 
            // Now use the value we just calculated to decrement CPT taps
1257 
            // to the desired calibration point
1258 
            read_pause <= #TCQ 'b1;
1259 
            prbs_state_r <= #TCQ PRBS_DEC_DQS;
1260 
          end
1261 
        end
1262 
 
1263 
        // decrement capture clock for final adjustment - center
1264 
        // capture clock in middle of data eye. This adjustment will occur
1265 
        // only when both the edges are found usign CPT taps. Must do this
1266 
        // incrementally to avoid clock glitching (since CPT drives clock
1267 
        // divider within each ISERDES)
1268 
        PRBS_DEC_DQS: begin
1269 
          prbs_tap_en_r  <= #TCQ 1'b1;
1270 
          prbs_tap_inc_r <= #TCQ 1'b0;
1271 
          // once adjustment is complete, we're done with calibration for
1272 
          // this DQS, repeat for next DQS
1273 
          if (prbs_dec_tap_cnt > 'd0)
1274 
            prbs_dec_tap_cnt <= #TCQ prbs_dec_tap_cnt - 1;
1275 
          if (prbs_dec_tap_cnt == 6'b000001)
1276 
            prbs_state_r <= #TCQ PRBS_NEXT_DQS;
1277 
          else
1278 
            prbs_state_r <= #TCQ PRBS_DEC_DQS_WAIT;
1279 
        end
1280 
 
1281 
        PRBS_DEC_DQS_WAIT: begin
1282 
          prbs_tap_en_r  <= #TCQ 1'b0;
1283 
          prbs_tap_inc_r <= #TCQ 1'b0;
1284 
          if (cnt_wait_state) begin
1285 
            if (prbs_dec_tap_cnt > 'd0)
1286 
              prbs_state_r <= #TCQ PRBS_DEC_DQS;
1287 
            else
1288 
              prbs_state_r <= #TCQ PRBS_PAT_COMPARE;
1289 
          end
1290 
        end
1291 
 
1292 
        // Determine whether we're done, or have more DQS's to calibrate
1293 
        // Also request precharge after every byte, as appropriate
1294 
        PRBS_NEXT_DQS: begin
1295 
          read_pause <= #TCQ 'b0;
1296 
          reset_rd_addr <= #TCQ 'b1;
1297 
          prbs_prech_req_r  <= #TCQ 1'b1;
1298 
          prbs_tap_en_r  <= #TCQ 1'b0;
1299 
          prbs_tap_inc_r <= #TCQ 1'b0;
1300 
          // Prepare for another iteration with next DQS group
1301 
          prbs_found_1st_edge_r <= #TCQ 1'b0;
1302 
          prbs_found_2nd_edge_r <= #TCQ 1'b0;
1303 
          prbs_1st_edge_taps_r  <= #TCQ 'd0;
1304 
          prbs_2nd_edge_taps_r  <= #TCQ 'd0;
1305 
          largest_left_edge       <= #TCQ 6'b000000;
1306 
          smallest_right_edge     <= #TCQ 6'b111111;
1307 
          if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin
1308 
            prbs_last_byte_done <= #TCQ 1'b1;
1309 
          end
1310 
 
1311 
          // Wait until precharge that occurs in between calibration of
1312 
          // DQS groups is finished
1313 
          if (prech_done) begin
1314 
            prbs_prech_req_r <= #TCQ 1'b0;
1315 
            if (prbs_dqs_cnt_r >= DQS_WIDTH-1) begin
1316 
              // All DQS groups done
1317 
              prbs_state_r <= #TCQ PRBS_DONE;
1318 
            end else begin
1319 
              // Process next DQS group
1320 
              new_cnt_dqs_r  <= #TCQ 1'b1;
1321 
              //fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
1322 
              prbs_dqs_cnt_r <= #TCQ prbs_dqs_cnt_r + 1;
1323 
              prbs_state_r   <= #TCQ PRBS_NEW_DQS_PREWAIT;
1324 
            end
1325 
          end
1326 
        end
1327 
 
1328 
        PRBS_NEW_DQS_PREWAIT: begin
1329 
          if (cnt_wait_state) begin
1330 
            prbs_state_r <= #TCQ PRBS_NEW_DQS_WAIT;
1331 
            fine_pi_dec_cnt <= #TCQ pi_counter_read_val;//.
1332 
          end
1333 
        end
1334 
 
1335 
        PRBS_CALC_TAPS_PRE:
1336 
        begin
1337 
          if(num_samples_done_r) begin
1338 
            prbs_state_r <= #TCQ fine_calib? PRBS_NEXT_DQS:PRBS_CALC_TAPS_WAIT;
1339 
            if(center_comp && ~fine_calib) begin
1340 
              if(prbs_found_1st_edge_r) largest_left_edge <= #TCQ prbs_1st_edge_taps_r;
1341 
              else largest_left_edge <= #TCQ 6'd0;
1342 
              if(prbs_found_2nd_edge_r) smallest_right_edge <= #TCQ prbs_2nd_edge_taps_r;
1343 
              else smallest_right_edge <= #TCQ 6'd63;
1344 
            end
1345 
          end
1346 
        end
1347 
            //wait for center compensation
1348 
        PRBS_CALC_TAPS_WAIT:
1349 
        begin
1350 
              prbs_state_r <= #TCQ PRBS_CALC_TAPS;
1351 
        end
1352 
        //if it is fine_inc stage (first/second stage): dec to 0
1353 
        //if it is fine_dec stage (third stage): dec to center
1354 
        FINE_PI_DEC: begin
1355 
          fine_delay_sel <= #TCQ 'b0;
1356 
          if(fine_pi_dec_cnt > 0) begin
1357 
            prbs_tap_en_r  <= #TCQ 1'b1;
1358 
            prbs_tap_inc_r <= #TCQ 1'b0;
1359 
            fine_pi_dec_cnt <= #TCQ fine_pi_dec_cnt - 'd1;
1360 
          end
1361 
          prbs_state_r <= #TCQ FINE_PI_DEC_WAIT;
1362 
        end
1363 
        //wait for phaser_in tap decrement.
1364 
        //if first/second stage is done, goes to FINE_PI_INC
1365 
        //if last stage is done, goes to NEXT_DQS
1366 
        FINE_PI_DEC_WAIT: begin
1367 
          prbs_tap_en_r  <= #TCQ 1'b0;
1368 
          prbs_tap_inc_r <= #TCQ 1'b0;
1369 
          if(cnt_wait_state) begin
1370 
            if(fine_pi_dec_cnt >0)
1371 
              prbs_state_r <= #TCQ FINE_PI_DEC;
1372 
            else
1373 
              if(fine_inc_stage)
1374 
               // prbs_state_r <= #TCQ FINE_PI_INC;  //for temp change
1375 
                prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT;   //start from pi tap "0"
1376 
              else
1377 
                prbs_state_r <= #TCQ PRBS_CALC_TAPS_PRE;  //finish the process and go to the next DQS
1378 
          end
1379 
        end
1380 
 
1381 
        FINE_PI_INC: begin
1382 
          if(|left_edge_updated) largest_left_edge <= #TCQ prbs_dqs_tap_cnt_r-4;
1383 
          if(|right_edge_found_pb && ~right_edge_found) begin
1384 
            smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r -1 ;
1385 
            right_edge_found <= #TCQ 'b1;
1386 
          end
1387 
          //left_edge_found_pb <= #TCQ {DRAM_WIDTH{1'b0}};
1388 
          prbs_state_r <= #TCQ FINE_PI_INC_WAIT;
1389 
          if(~prbs_dqs_tap_limit_r) begin
1390 
            prbs_tap_en_r    <= #TCQ 1'b1;
1391 
            prbs_tap_inc_r   <= #TCQ 1'b1;
1392 
          end
1393 
        end
1394 
        //wait for phase_in tap increment
1395 
        //need to do pattern compare for every bit
1396 
        FINE_PI_INC_WAIT: begin
1397 
          prbs_tap_en_r    <= #TCQ 1'b0;
1398 
          prbs_tap_inc_r   <= #TCQ 1'b0;
1399 
          if (cnt_wait_state) begin
1400 
              prbs_state_r <= #TCQ FINE_PAT_COMPARE_PER_BIT;
1401 
          end
1402 
        end
1403 
        //compare per bit data and update flags,left/right edge
1404 
        FINE_PAT_COMPARE_PER_BIT: begin
1405 
          if(num_samples_done_r || compare_err_pb_and) begin
1406 
            //update and_flag - shift and add
1407 
            match_flag_and <= #TCQ {match_flag_and[3:0],compare_err_pb_and};
1408 
            //if it is consecutive 5 passing taps followed by fail or tap limit (finish the search)
1409 
            //don't go to fine_FINE_CALC_TAPS to prevent to skip whole stage
1410 
            //Or if all right edge are found
1411 
            if((match_flag_and == 5'b00000 && compare_err_pb_and && (prbs_dqs_tap_cnt_r > 5)) || prbs_dqs_tap_limit_r || (&right_edge_found_pb)) begin
1412 
              prbs_state_r <= #TCQ FINE_CALC_TAPS;
1413 
              //if all right edge are alined (all right edge found at the same time), update smallest right edge in here
1414 
              //doesnt need to set right_edge_found to 1 since it is not used after this stage
1415 
              if(!right_edge_found) smallest_right_edge <= #TCQ prbs_dqs_tap_cnt_r-1;
1416 
            end else begin
1417 
              prbs_state_r <= #TCQ FINE_PI_INC;  //keep increase until all fail
1418 
            end
1419 
            num_samples_done_ind <= num_samples_done_r;
1420 
          end
1421 
        end
1422 
        //for fine_inc stage, inc all fine delay
1423 
        //for fine_dec stage, apply dec fine delay for specific bits (by calculating the loss/gain)
1424 
        //                    put phaser_in taps to the center
1425 
        FINE_CALC_TAPS: begin
1426 
         if(num_samples_done_ind || num_samples_done_r) begin
1427 
          num_samples_done_ind <= #TCQ 'b0; //indicate num_samples_done_r is set
1428 
          right_edge_found <= #TCQ 1'b0;  //reset right edge found
1429 
          match_flag_and <= #TCQ 5'h1f;   //reset match flag for all bits
1430 
          prbs_state_r <= #TCQ FINE_CALC_TAPS_WAIT;
1431 
          end
1432 
        end
1433 
 
1434 
        FINE_CALC_TAPS_WAIT: begin  //wait for ROM read out
1435 
          if(stage_cnt == 'd2) begin  //last stage : back to center
1436 
            if(center_comp) begin
1437 
              fine_pi_dec_cnt <= #TCQ (dec_cnt[5]&dec_cnt[0])? 'd32: prbs_dqs_tap_cnt_r - smallest_right_edge + dec_cnt - 1 + pi_adj ;  //going to the center value & shift by 1
1438 
              fine_dly_error <= #TCQ (dec_cnt[5]&dec_cnt[0]) ? 1'b1: fine_dly_error;
1439 
            end else begin
1440 
              fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r - center_calc[6:1] - center_calc[0] + pi_adj;  //going to the center value & shift left by 1
1441 
              fine_dly_error <= #TCQ 1'b0;
1442 
            end
1443 
          end else begin
1444 
            fine_pi_dec_cnt <= #TCQ prbs_dqs_tap_cnt_r;
1445 
          end
1446 
          if (bit_cnt == DRAM_WIDTH) begin
1447 
            fine_delay_sel <= #TCQ 'b1;
1448 
            stage_cnt <= #TCQ stage_cnt + 1;
1449 
            prbs_state_r <= #TCQ FINE_PI_DEC;
1450 
          end
1451 
 
1452 
        end
1453 
 
1454 
        // Done with this stage of calibration
1455 
        PRBS_DONE: begin
1456 
          prbs_prech_req_r    <= #TCQ 1'b0;
1457 
          prbs_last_byte_done <= #TCQ 1'b0;
1458 
          prbs_rdlvl_done     <= #TCQ 1'b1;
1459 
          reset_rd_addr       <= #TCQ 1'b0;
1460 
        end
1461 
 
1462 
      endcase
1463 
    end
1464 
 
1465 
  //ROM generation for dec counter
1466 
  always @ (largest_left_edge or smallest_right_edge) begin
1467 
    case ({largest_left_edge, smallest_right_edge})
1468 
      12'd0    :  mem_out_dec = 6'b111111;
1469 
      12'd1    :  mem_out_dec = 6'b111111;
1470 
      12'd2    :  mem_out_dec = 6'b111111;
1471 
      12'd3    :  mem_out_dec = 6'b111111;
1472 
      12'd4    :  mem_out_dec = 6'b111111;
1473 
      12'd5    :  mem_out_dec = 6'b111111;
1474 
      12'd6    :  mem_out_dec = 6'b000100;
1475 
      12'd7    :  mem_out_dec = 6'b000101;
1476 
      12'd8    :  mem_out_dec = 6'b000101;
1477 
      12'd9    :  mem_out_dec = 6'b000110;
1478 
      12'd10   :  mem_out_dec = 6'b000110;
1479 
      12'd11   :  mem_out_dec = 6'b000111;
1480 
      12'd12   :  mem_out_dec = 6'b001000;
1481 
      12'd13   :  mem_out_dec = 6'b001000;
1482 
      12'd14   :  mem_out_dec = 6'b001001;
1483 
      12'd15   :  mem_out_dec = 6'b001010;
1484 
      12'd16   :  mem_out_dec = 6'b001010;
1485 
      12'd17   :  mem_out_dec = 6'b001011;
1486 
      12'd18   :  mem_out_dec = 6'b001011;
1487 
      12'd19   :  mem_out_dec = 6'b001100;
1488 
      12'd20   :  mem_out_dec = 6'b001100;
1489 
      12'd21   :  mem_out_dec = 6'b001100;
1490 
      12'd22   :  mem_out_dec = 6'b001100;
1491 
      12'd23   :  mem_out_dec = 6'b001101;
1492 
      12'd24   :  mem_out_dec = 6'b001100;
1493 
      12'd25   :  mem_out_dec = 6'b001100;
1494 
      12'd26   :  mem_out_dec = 6'b001101;
1495 
      12'd27   :  mem_out_dec = 6'b001110;
1496 
      12'd28   :  mem_out_dec = 6'b001110;
1497 
      12'd29   :  mem_out_dec = 6'b001111;
1498 
      12'd30   :  mem_out_dec = 6'b010000;
1499 
      12'd31   :  mem_out_dec = 6'b010001;
1500 
      12'd32   :  mem_out_dec = 6'b010001;
1501 
      12'd33   :  mem_out_dec = 6'b010010;
1502 
      12'd34   :  mem_out_dec = 6'b010010;
1503 
      12'd35   :  mem_out_dec = 6'b010010;
1504 
      12'd36   :  mem_out_dec = 6'b010011;
1505 
      12'd37   :  mem_out_dec = 6'b010100;
1506 
      12'd38   :  mem_out_dec = 6'b010100;
1507 
      12'd39   :  mem_out_dec = 6'b010101;
1508 
      12'd40   :  mem_out_dec = 6'b010101;
1509 
      12'd41   :  mem_out_dec = 6'b010110;
1510 
      12'd42   :  mem_out_dec = 6'b010110;
1511 
      12'd43   :  mem_out_dec = 6'b010111;
1512 
      12'd44   :  mem_out_dec = 6'b011000;
1513 
      12'd45   :  mem_out_dec = 6'b011001;
1514 
      12'd46   :  mem_out_dec = 6'b011001;
1515 
      12'd47   :  mem_out_dec = 6'b011010;
1516 
      12'd48   :  mem_out_dec = 6'b011010;
1517 
      12'd49   :  mem_out_dec = 6'b011011;
1518 
      12'd50   :  mem_out_dec = 6'b011011;
1519 
      12'd51   :  mem_out_dec = 6'b011100;
1520 
      12'd52   :  mem_out_dec = 6'b011100;
1521 
      12'd53   :  mem_out_dec = 6'b011100;
1522 
      12'd54   :  mem_out_dec = 6'b011100;
1523 
      12'd55   :  mem_out_dec = 6'b011100;
1524 
      12'd56   :  mem_out_dec = 6'b011100;
1525 
      12'd57   :  mem_out_dec = 6'b011100;
1526 
      12'd58   :  mem_out_dec = 6'b011100;
1527 
      12'd59   :  mem_out_dec = 6'b011101;
1528 
      12'd60   :  mem_out_dec = 6'b011110;
1529 
      12'd61   :  mem_out_dec = 6'b011111;
1530 
      12'd62   :  mem_out_dec = 6'b100000;
1531 
      12'd63   :  mem_out_dec = 6'b100000;
1532 
      12'd64   :  mem_out_dec = 6'b111111;
1533 
      12'd65   :  mem_out_dec = 6'b111111;
1534 
      12'd66   :  mem_out_dec = 6'b111111;
1535 
      12'd67   :  mem_out_dec = 6'b111111;
1536 
      12'd68   :  mem_out_dec = 6'b111111;
1537 
      12'd69   :  mem_out_dec = 6'b111111;
1538 
      12'd70   :  mem_out_dec = 6'b111111;
1539 
      12'd71   :  mem_out_dec = 6'b000100;
1540 
      12'd72   :  mem_out_dec = 6'b000100;
1541 
      12'd73   :  mem_out_dec = 6'b000101;
1542 
      12'd74   :  mem_out_dec = 6'b000110;
1543 
      12'd75   :  mem_out_dec = 6'b000111;
1544 
      12'd76   :  mem_out_dec = 6'b000111;
1545 
      12'd77   :  mem_out_dec = 6'b001000;
1546 
      12'd78   :  mem_out_dec = 6'b001001;
1547 
      12'd79   :  mem_out_dec = 6'b001001;
1548 
      12'd80   :  mem_out_dec = 6'b001010;
1549 
      12'd81   :  mem_out_dec = 6'b001010;
1550 
      12'd82   :  mem_out_dec = 6'b001011;
1551 
      12'd83   :  mem_out_dec = 6'b001011;
1552 
      12'd84   :  mem_out_dec = 6'b001011;
1553 
      12'd85   :  mem_out_dec = 6'b001011;
1554 
      12'd86   :  mem_out_dec = 6'b001011;
1555 
      12'd87   :  mem_out_dec = 6'b001100;
1556 
      12'd88   :  mem_out_dec = 6'b001011;
1557 
      12'd89   :  mem_out_dec = 6'b001100;
1558 
      12'd90   :  mem_out_dec = 6'b001100;
1559 
      12'd91   :  mem_out_dec = 6'b001101;
1560 
      12'd92   :  mem_out_dec = 6'b001110;
1561 
      12'd93   :  mem_out_dec = 6'b001111;
1562 
      12'd94   :  mem_out_dec = 6'b001111;
1563 
      12'd95   :  mem_out_dec = 6'b010000;
1564 
      12'd96   :  mem_out_dec = 6'b010001;
1565 
      12'd97   :  mem_out_dec = 6'b010001;
1566 
      12'd98   :  mem_out_dec = 6'b010010;
1567 
      12'd99   :  mem_out_dec = 6'b010010;
1568 
      12'd100  :  mem_out_dec = 6'b010011;
1569 
      12'd101  :  mem_out_dec = 6'b010011;
1570 
      12'd102  :  mem_out_dec = 6'b010100;
1571 
      12'd103  :  mem_out_dec = 6'b010100;
1572 
      12'd104  :  mem_out_dec = 6'b010100;
1573 
      12'd105  :  mem_out_dec = 6'b010101;
1574 
      12'd106  :  mem_out_dec = 6'b010110;
1575 
      12'd107  :  mem_out_dec = 6'b010111;
1576 
      12'd108  :  mem_out_dec = 6'b010111;
1577 
      12'd109  :  mem_out_dec = 6'b011000;
1578 
      12'd110  :  mem_out_dec = 6'b011001;
1579 
      12'd111  :  mem_out_dec = 6'b011001;
1580 
      12'd112  :  mem_out_dec = 6'b011010;
1581 
      12'd113  :  mem_out_dec = 6'b011010;
1582 
      12'd114  :  mem_out_dec = 6'b011011;
1583 
      12'd115  :  mem_out_dec = 6'b011011;
1584 
      12'd116  :  mem_out_dec = 6'b011011;
1585 
      12'd117  :  mem_out_dec = 6'b011011;
1586 
      12'd118  :  mem_out_dec = 6'b011011;
1587 
      12'd119  :  mem_out_dec = 6'b011011;
1588 
      12'd120  :  mem_out_dec = 6'b011011;
1589 
      12'd121  :  mem_out_dec = 6'b011011;
1590 
      12'd122  :  mem_out_dec = 6'b011100;
1591 
      12'd123  :  mem_out_dec = 6'b011101;
1592 
      12'd124  :  mem_out_dec = 6'b011110;
1593 
      12'd125  :  mem_out_dec = 6'b011110;
1594 
      12'd126  :  mem_out_dec = 6'b011111;
1595 
      12'd127  :  mem_out_dec = 6'b100000;
1596 
      12'd128  :  mem_out_dec = 6'b111111;
1597 
      12'd129  :  mem_out_dec = 6'b111111;
1598 
      12'd130  :  mem_out_dec = 6'b111111;
1599 
      12'd131  :  mem_out_dec = 6'b111111;
1600 
      12'd132  :  mem_out_dec = 6'b111111;
1601 
      12'd133  :  mem_out_dec = 6'b111111;
1602 
      12'd134  :  mem_out_dec = 6'b111111;
1603 
      12'd135  :  mem_out_dec = 6'b111111;
1604 
      12'd136  :  mem_out_dec = 6'b000100;
1605 
      12'd137  :  mem_out_dec = 6'b000101;
1606 
      12'd138  :  mem_out_dec = 6'b000101;
1607 
      12'd139  :  mem_out_dec = 6'b000110;
1608 
      12'd140  :  mem_out_dec = 6'b000110;
1609 
      12'd141  :  mem_out_dec = 6'b000111;
1610 
      12'd142  :  mem_out_dec = 6'b001000;
1611 
      12'd143  :  mem_out_dec = 6'b001001;
1612 
      12'd144  :  mem_out_dec = 6'b001001;
1613 
      12'd145  :  mem_out_dec = 6'b001010;
1614 
      12'd146  :  mem_out_dec = 6'b001010;
1615 
      12'd147  :  mem_out_dec = 6'b001010;
1616 
      12'd148  :  mem_out_dec = 6'b001010;
1617 
      12'd149  :  mem_out_dec = 6'b001010;
1618 
      12'd150  :  mem_out_dec = 6'b001010;
1619 
      12'd151  :  mem_out_dec = 6'b001011;
1620 
      12'd152  :  mem_out_dec = 6'b001010;
1621 
      12'd153  :  mem_out_dec = 6'b001011;
1622 
      12'd154  :  mem_out_dec = 6'b001100;
1623 
      12'd155  :  mem_out_dec = 6'b001101;
1624 
      12'd156  :  mem_out_dec = 6'b001101;
1625 
      12'd157  :  mem_out_dec = 6'b001110;
1626 
      12'd158  :  mem_out_dec = 6'b001111;
1627 
      12'd159  :  mem_out_dec = 6'b010000;
1628 
      12'd160  :  mem_out_dec = 6'b010000;
1629 
      12'd161  :  mem_out_dec = 6'b010001;
1630 
      12'd162  :  mem_out_dec = 6'b010001;
1631 
      12'd163  :  mem_out_dec = 6'b010010;
1632 
      12'd164  :  mem_out_dec = 6'b010010;
1633 
      12'd165  :  mem_out_dec = 6'b010011;
1634 
      12'd166  :  mem_out_dec = 6'b010011;
1635 
      12'd167  :  mem_out_dec = 6'b010100;
1636 
      12'd168  :  mem_out_dec = 6'b010100;
1637 
      12'd169  :  mem_out_dec = 6'b010101;
1638 
      12'd170  :  mem_out_dec = 6'b010101;
1639 
      12'd171  :  mem_out_dec = 6'b010110;
1640 
      12'd172  :  mem_out_dec = 6'b010111;
1641 
      12'd173  :  mem_out_dec = 6'b010111;
1642 
      12'd174  :  mem_out_dec = 6'b011000;
1643 
      12'd175  :  mem_out_dec = 6'b011001;
1644 
      12'd176  :  mem_out_dec = 6'b011001;
1645 
      12'd177  :  mem_out_dec = 6'b011010;
1646 
      12'd178  :  mem_out_dec = 6'b011010;
1647 
      12'd179  :  mem_out_dec = 6'b011010;
1648 
      12'd180  :  mem_out_dec = 6'b011010;
1649 
      12'd181  :  mem_out_dec = 6'b011010;
1650 
      12'd182  :  mem_out_dec = 6'b011010;
1651 
      12'd183  :  mem_out_dec = 6'b011010;
1652 
      12'd184  :  mem_out_dec = 6'b011010;
1653 
      12'd185  :  mem_out_dec = 6'b011011;
1654 
      12'd186  :  mem_out_dec = 6'b011100;
1655 
      12'd187  :  mem_out_dec = 6'b011100;
1656 
      12'd188  :  mem_out_dec = 6'b011101;
1657 
      12'd189  :  mem_out_dec = 6'b011110;
1658 
      12'd190  :  mem_out_dec = 6'b011111;
1659 
      12'd191  :  mem_out_dec = 6'b100000;
1660 
      12'd192  :  mem_out_dec = 6'b111111;
1661 
      12'd193  :  mem_out_dec = 6'b111111;
1662 
      12'd194  :  mem_out_dec = 6'b111111;
1663 
      12'd195  :  mem_out_dec = 6'b111111;
1664 
      12'd196  :  mem_out_dec = 6'b111111;
1665 
      12'd197  :  mem_out_dec = 6'b111111;
1666 
      12'd198  :  mem_out_dec = 6'b111111;
1667 
      12'd199  :  mem_out_dec = 6'b111111;
1668 
      12'd200  :  mem_out_dec = 6'b111111;
1669 
      12'd201  :  mem_out_dec = 6'b000100;
1670 
      12'd202  :  mem_out_dec = 6'b000100;
1671 
      12'd203  :  mem_out_dec = 6'b000101;
1672 
      12'd204  :  mem_out_dec = 6'b000110;
1673 
      12'd205  :  mem_out_dec = 6'b000111;
1674 
      12'd206  :  mem_out_dec = 6'b001000;
1675 
      12'd207  :  mem_out_dec = 6'b001000;
1676 
      12'd208  :  mem_out_dec = 6'b001001;
1677 
      12'd209  :  mem_out_dec = 6'b001001;
1678 
      12'd210  :  mem_out_dec = 6'b001001;
1679 
      12'd211  :  mem_out_dec = 6'b001001;
1680 
      12'd212  :  mem_out_dec = 6'b001001;
1681 
      12'd213  :  mem_out_dec = 6'b001001;
1682 
      12'd214  :  mem_out_dec = 6'b001001;
1683 
      12'd215  :  mem_out_dec = 6'b001010;
1684 
      12'd216  :  mem_out_dec = 6'b001010;
1685 
      12'd217  :  mem_out_dec = 6'b001011;
1686 
      12'd218  :  mem_out_dec = 6'b001011;
1687 
      12'd219  :  mem_out_dec = 6'b001100;
1688 
      12'd220  :  mem_out_dec = 6'b001101;
1689 
      12'd221  :  mem_out_dec = 6'b001110;
1690 
      12'd222  :  mem_out_dec = 6'b001111;
1691 
      12'd223  :  mem_out_dec = 6'b001111;
1692 
      12'd224  :  mem_out_dec = 6'b010000;
1693 
      12'd225  :  mem_out_dec = 6'b010000;
1694 
      12'd226  :  mem_out_dec = 6'b010001;
1695 
      12'd227  :  mem_out_dec = 6'b010001;
1696 
      12'd228  :  mem_out_dec = 6'b010010;
1697 
      12'd229  :  mem_out_dec = 6'b010010;
1698 
      12'd230  :  mem_out_dec = 6'b010011;
1699 
      12'd231  :  mem_out_dec = 6'b010011;
1700 
      12'd232  :  mem_out_dec = 6'b010011;
1701 
      12'd233  :  mem_out_dec = 6'b010100;
1702 
      12'd234  :  mem_out_dec = 6'b010100;
1703 
      12'd235  :  mem_out_dec = 6'b010101;
1704 
      12'd236  :  mem_out_dec = 6'b010110;
1705 
      12'd237  :  mem_out_dec = 6'b010111;
1706 
      12'd238  :  mem_out_dec = 6'b011000;
1707 
      12'd239  :  mem_out_dec = 6'b011000;
1708 
      12'd240  :  mem_out_dec = 6'b011001;
1709 
      12'd241  :  mem_out_dec = 6'b011001;
1710 
      12'd242  :  mem_out_dec = 6'b011001;
1711 
      12'd243  :  mem_out_dec = 6'b011001;
1712 
      12'd244  :  mem_out_dec = 6'b011001;
1713 
      12'd245  :  mem_out_dec = 6'b011001;
1714 
      12'd246  :  mem_out_dec = 6'b011001;
1715 
      12'd247  :  mem_out_dec = 6'b011001;
1716 
      12'd248  :  mem_out_dec = 6'b011010;
1717 
      12'd249  :  mem_out_dec = 6'b011010;
1718 
      12'd250  :  mem_out_dec = 6'b011011;
1719 
      12'd251  :  mem_out_dec = 6'b011100;
1720 
      12'd252  :  mem_out_dec = 6'b011101;
1721 
      12'd253  :  mem_out_dec = 6'b011110;
1722 
      12'd254  :  mem_out_dec = 6'b011110;
1723 
      12'd255  :  mem_out_dec = 6'b011111;
1724 
      12'd256  :  mem_out_dec = 6'b111111;
1725 
      12'd257  :  mem_out_dec = 6'b111111;
1726 
      12'd258  :  mem_out_dec = 6'b111111;
1727 
      12'd259  :  mem_out_dec = 6'b111111;
1728 
      12'd260  :  mem_out_dec = 6'b111111;
1729 
      12'd261  :  mem_out_dec = 6'b111111;
1730 
      12'd262  :  mem_out_dec = 6'b111111;
1731 
      12'd263  :  mem_out_dec = 6'b111111;
1732 
      12'd264  :  mem_out_dec = 6'b111111;
1733 
      12'd265  :  mem_out_dec = 6'b111111;
1734 
      12'd266  :  mem_out_dec = 6'b000100;
1735 
      12'd267  :  mem_out_dec = 6'b000101;
1736 
      12'd268  :  mem_out_dec = 6'b000110;
1737 
      12'd269  :  mem_out_dec = 6'b000110;
1738 
      12'd270  :  mem_out_dec = 6'b000111;
1739 
      12'd271  :  mem_out_dec = 6'b001000;
1740 
      12'd272  :  mem_out_dec = 6'b001000;
1741 
      12'd273  :  mem_out_dec = 6'b001000;
1742 
      12'd274  :  mem_out_dec = 6'b001000;
1743 
      12'd275  :  mem_out_dec = 6'b001000;
1744 
      12'd276  :  mem_out_dec = 6'b001000;
1745 
      12'd277  :  mem_out_dec = 6'b001000;
1746 
      12'd278  :  mem_out_dec = 6'b001000;
1747 
      12'd279  :  mem_out_dec = 6'b001001;
1748 
      12'd280  :  mem_out_dec = 6'b001001;
1749 
      12'd281  :  mem_out_dec = 6'b001010;
1750 
      12'd282  :  mem_out_dec = 6'b001011;
1751 
      12'd283  :  mem_out_dec = 6'b001100;
1752 
      12'd284  :  mem_out_dec = 6'b001101;
1753 
      12'd285  :  mem_out_dec = 6'b001101;
1754 
      12'd286  :  mem_out_dec = 6'b001110;
1755 
      12'd287  :  mem_out_dec = 6'b001111;
1756 
      12'd288  :  mem_out_dec = 6'b001111;
1757 
      12'd289  :  mem_out_dec = 6'b010000;
1758 
      12'd290  :  mem_out_dec = 6'b010000;
1759 
      12'd291  :  mem_out_dec = 6'b010001;
1760 
      12'd292  :  mem_out_dec = 6'b010001;
1761 
      12'd293  :  mem_out_dec = 6'b010010;
1762 
      12'd294  :  mem_out_dec = 6'b010010;
1763 
      12'd295  :  mem_out_dec = 6'b010011;
1764 
      12'd296  :  mem_out_dec = 6'b010010;
1765 
      12'd297  :  mem_out_dec = 6'b010011;
1766 
      12'd298  :  mem_out_dec = 6'b010100;
1767 
      12'd299  :  mem_out_dec = 6'b010101;
1768 
      12'd300  :  mem_out_dec = 6'b010110;
1769 
      12'd301  :  mem_out_dec = 6'b010110;
1770 
      12'd302  :  mem_out_dec = 6'b010111;
1771 
      12'd303  :  mem_out_dec = 6'b011000;
1772 
      12'd304  :  mem_out_dec = 6'b011000;
1773 
      12'd305  :  mem_out_dec = 6'b011000;
1774 
      12'd306  :  mem_out_dec = 6'b011000;
1775 
      12'd307  :  mem_out_dec = 6'b011000;
1776 
      12'd308  :  mem_out_dec = 6'b011000;
1777 
      12'd309  :  mem_out_dec = 6'b011000;
1778 
      12'd310  :  mem_out_dec = 6'b011000;
1779 
      12'd311  :  mem_out_dec = 6'b011001;
1780 
      12'd312  :  mem_out_dec = 6'b011001;
1781 
      12'd313  :  mem_out_dec = 6'b011010;
1782 
      12'd314  :  mem_out_dec = 6'b011011;
1783 
      12'd315  :  mem_out_dec = 6'b011100;
1784 
      12'd316  :  mem_out_dec = 6'b011100;
1785 
      12'd317  :  mem_out_dec = 6'b011101;
1786 
      12'd318  :  mem_out_dec = 6'b011110;
1787 
      12'd319  :  mem_out_dec = 6'b011111;
1788 
      12'd320  :  mem_out_dec = 6'b111111;
1789 
      12'd321  :  mem_out_dec = 6'b111111;
1790 
      12'd322  :  mem_out_dec = 6'b111111;
1791 
      12'd323  :  mem_out_dec = 6'b111111;
1792 
      12'd324  :  mem_out_dec = 6'b111111;
1793 
      12'd325  :  mem_out_dec = 6'b111111;
1794 
      12'd326  :  mem_out_dec = 6'b111111;
1795 
      12'd327  :  mem_out_dec = 6'b111111;
1796 
      12'd328  :  mem_out_dec = 6'b111111;
1797 
      12'd329  :  mem_out_dec = 6'b111111;
1798 
      12'd330  :  mem_out_dec = 6'b111111;
1799 
      12'd331  :  mem_out_dec = 6'b000100;
1800 
      12'd332  :  mem_out_dec = 6'b000101;
1801 
      12'd333  :  mem_out_dec = 6'b000110;
1802 
      12'd334  :  mem_out_dec = 6'b000111;
1803 
      12'd335  :  mem_out_dec = 6'b001000;
1804 
      12'd336  :  mem_out_dec = 6'b000111;
1805 
      12'd337  :  mem_out_dec = 6'b000111;
1806 
      12'd338  :  mem_out_dec = 6'b000111;
1807 
      12'd339  :  mem_out_dec = 6'b000111;
1808 
      12'd340  :  mem_out_dec = 6'b000111;
1809 
      12'd341  :  mem_out_dec = 6'b000111;
1810 
      12'd342  :  mem_out_dec = 6'b001000;
1811 
      12'd343  :  mem_out_dec = 6'b001001;
1812 
      12'd344  :  mem_out_dec = 6'b001001;
1813 
      12'd345  :  mem_out_dec = 6'b001010;
1814 
      12'd346  :  mem_out_dec = 6'b001011;
1815 
      12'd347  :  mem_out_dec = 6'b001011;
1816 
      12'd348  :  mem_out_dec = 6'b001100;
1817 
      12'd349  :  mem_out_dec = 6'b001101;
1818 
      12'd350  :  mem_out_dec = 6'b001110;
1819 
      12'd351  :  mem_out_dec = 6'b001110;
1820 
      12'd352  :  mem_out_dec = 6'b001111;
1821 
      12'd353  :  mem_out_dec = 6'b001111;
1822 
      12'd354  :  mem_out_dec = 6'b010000;
1823 
      12'd355  :  mem_out_dec = 6'b010000;
1824 
      12'd356  :  mem_out_dec = 6'b010001;
1825 
      12'd357  :  mem_out_dec = 6'b010001;
1826 
      12'd358  :  mem_out_dec = 6'b010001;
1827 
      12'd359  :  mem_out_dec = 6'b010010;
1828 
      12'd360  :  mem_out_dec = 6'b010010;
1829 
      12'd361  :  mem_out_dec = 6'b010011;
1830 
      12'd362  :  mem_out_dec = 6'b010100;
1831 
      12'd363  :  mem_out_dec = 6'b010100;
1832 
      12'd364  :  mem_out_dec = 6'b010101;
1833 
      12'd365  :  mem_out_dec = 6'b010110;
1834 
      12'd366  :  mem_out_dec = 6'b010111;
1835 
      12'd367  :  mem_out_dec = 6'b011000;
1836 
      12'd368  :  mem_out_dec = 6'b010111;
1837 
      12'd369  :  mem_out_dec = 6'b010111;
1838 
      12'd370  :  mem_out_dec = 6'b010111;
1839 
      12'd371  :  mem_out_dec = 6'b010111;
1840 
      12'd372  :  mem_out_dec = 6'b010111;
1841 
      12'd373  :  mem_out_dec = 6'b010111;
1842 
      12'd374  :  mem_out_dec = 6'b011000;
1843 
      12'd375  :  mem_out_dec = 6'b011001;
1844 
      12'd376  :  mem_out_dec = 6'b011001;
1845 
      12'd377  :  mem_out_dec = 6'b011010;
1846 
      12'd378  :  mem_out_dec = 6'b011010;
1847 
      12'd379  :  mem_out_dec = 6'b011011;
1848 
      12'd380  :  mem_out_dec = 6'b011100;
1849 
      12'd381  :  mem_out_dec = 6'b011101;
1850 
      12'd382  :  mem_out_dec = 6'b011101;
1851 
      12'd383  :  mem_out_dec = 6'b011110;
1852 
      12'd384  :  mem_out_dec = 6'b111111;
1853 
      12'd385  :  mem_out_dec = 6'b111111;
1854 
      12'd386  :  mem_out_dec = 6'b111111;
1855 
      12'd387  :  mem_out_dec = 6'b111111;
1856 
      12'd388  :  mem_out_dec = 6'b111111;
1857 
      12'd389  :  mem_out_dec = 6'b111111;
1858 
      12'd390  :  mem_out_dec = 6'b111111;
1859 
      12'd391  :  mem_out_dec = 6'b111111;
1860 
      12'd392  :  mem_out_dec = 6'b111111;
1861 
      12'd393  :  mem_out_dec = 6'b111111;
1862 
      12'd394  :  mem_out_dec = 6'b111111;
1863 
      12'd395  :  mem_out_dec = 6'b111111;
1864 
      12'd396  :  mem_out_dec = 6'b000101;
1865 
      12'd397  :  mem_out_dec = 6'b000110;
1866 
      12'd398  :  mem_out_dec = 6'b000110;
1867 
      12'd399  :  mem_out_dec = 6'b000111;
1868 
      12'd400  :  mem_out_dec = 6'b000110;
1869 
      12'd401  :  mem_out_dec = 6'b000110;
1870 
      12'd402  :  mem_out_dec = 6'b000110;
1871 
      12'd403  :  mem_out_dec = 6'b000110;
1872 
      12'd404  :  mem_out_dec = 6'b000110;
1873 
      12'd405  :  mem_out_dec = 6'b000111;
1874 
      12'd406  :  mem_out_dec = 6'b001000;
1875 
      12'd407  :  mem_out_dec = 6'b001000;
1876 
      12'd408  :  mem_out_dec = 6'b001001;
1877 
      12'd409  :  mem_out_dec = 6'b001001;
1878 
      12'd410  :  mem_out_dec = 6'b001010;
1879 
      12'd411  :  mem_out_dec = 6'b001011;
1880 
      12'd412  :  mem_out_dec = 6'b001100;
1881 
      12'd413  :  mem_out_dec = 6'b001100;
1882 
      12'd414  :  mem_out_dec = 6'b001101;
1883 
      12'd415  :  mem_out_dec = 6'b001110;
1884 
      12'd416  :  mem_out_dec = 6'b001110;
1885 
      12'd417  :  mem_out_dec = 6'b001111;
1886 
      12'd418  :  mem_out_dec = 6'b001111;
1887 
      12'd419  :  mem_out_dec = 6'b010000;
1888 
      12'd420  :  mem_out_dec = 6'b010000;
1889 
      12'd421  :  mem_out_dec = 6'b010000;
1890 
      12'd422  :  mem_out_dec = 6'b010001;
1891 
      12'd423  :  mem_out_dec = 6'b010001;
1892 
      12'd424  :  mem_out_dec = 6'b010010;
1893 
      12'd425  :  mem_out_dec = 6'b010011;
1894 
      12'd426  :  mem_out_dec = 6'b010011;
1895 
      12'd427  :  mem_out_dec = 6'b010100;
1896 
      12'd428  :  mem_out_dec = 6'b010101;
1897 
      12'd429  :  mem_out_dec = 6'b010110;
1898 
      12'd430  :  mem_out_dec = 6'b010111;
1899 
      12'd431  :  mem_out_dec = 6'b010111;
1900 
      12'd432  :  mem_out_dec = 6'b010110;
1901 
      12'd433  :  mem_out_dec = 6'b010110;
1902 
      12'd434  :  mem_out_dec = 6'b010110;
1903 
      12'd435  :  mem_out_dec = 6'b010110;
1904 
      12'd436  :  mem_out_dec = 6'b010110;
1905 
      12'd437  :  mem_out_dec = 6'b010111;
1906 
      12'd438  :  mem_out_dec = 6'b010111;
1907 
      12'd439  :  mem_out_dec = 6'b011000;
1908 
      12'd440  :  mem_out_dec = 6'b011001;
1909 
      12'd441  :  mem_out_dec = 6'b011001;
1910 
      12'd442  :  mem_out_dec = 6'b011010;
1911 
      12'd443  :  mem_out_dec = 6'b011011;
1912 
      12'd444  :  mem_out_dec = 6'b011011;
1913 
      12'd445  :  mem_out_dec = 6'b011100;
1914 
      12'd446  :  mem_out_dec = 6'b011101;
1915 
      12'd447  :  mem_out_dec = 6'b011110;
1916 
      12'd448  :  mem_out_dec = 6'b111111;
1917 
      12'd449  :  mem_out_dec = 6'b111111;
1918 
      12'd450  :  mem_out_dec = 6'b111111;
1919 
      12'd451  :  mem_out_dec = 6'b111111;
1920 
      12'd452  :  mem_out_dec = 6'b111111;
1921 
      12'd453  :  mem_out_dec = 6'b111111;
1922 
      12'd454  :  mem_out_dec = 6'b111111;
1923 
      12'd455  :  mem_out_dec = 6'b111111;
1924 
      12'd456  :  mem_out_dec = 6'b111111;
1925 
      12'd457  :  mem_out_dec = 6'b111111;
1926 
      12'd458  :  mem_out_dec = 6'b111111;
1927 
      12'd459  :  mem_out_dec = 6'b111111;
1928 
      12'd460  :  mem_out_dec = 6'b111111;
1929 
      12'd461  :  mem_out_dec = 6'b000101;
1930 
      12'd462  :  mem_out_dec = 6'b000110;
1931 
      12'd463  :  mem_out_dec = 6'b000110;
1932 
      12'd464  :  mem_out_dec = 6'b000110;
1933 
      12'd465  :  mem_out_dec = 6'b000110;
1934 
      12'd466  :  mem_out_dec = 6'b000110;
1935 
      12'd467  :  mem_out_dec = 6'b000110;
1936 
      12'd468  :  mem_out_dec = 6'b000110;
1937 
      12'd469  :  mem_out_dec = 6'b000111;
1938 
      12'd470  :  mem_out_dec = 6'b000111;
1939 
      12'd471  :  mem_out_dec = 6'b001000;
1940 
      12'd472  :  mem_out_dec = 6'b001000;
1941 
      12'd473  :  mem_out_dec = 6'b001001;
1942 
      12'd474  :  mem_out_dec = 6'b001010;
1943 
      12'd475  :  mem_out_dec = 6'b001011;
1944 
      12'd476  :  mem_out_dec = 6'b001011;
1945 
      12'd477  :  mem_out_dec = 6'b001100;
1946 
      12'd478  :  mem_out_dec = 6'b001101;
1947 
      12'd479  :  mem_out_dec = 6'b001110;
1948 
      12'd480  :  mem_out_dec = 6'b001110;
1949 
      12'd481  :  mem_out_dec = 6'b001110;
1950 
      12'd482  :  mem_out_dec = 6'b001111;
1951 
      12'd483  :  mem_out_dec = 6'b001111;
1952 
      12'd484  :  mem_out_dec = 6'b010000;
1953 
      12'd485  :  mem_out_dec = 6'b010000;
1954 
      12'd486  :  mem_out_dec = 6'b010000;
1955 
      12'd487  :  mem_out_dec = 6'b010001;
1956 
      12'd488  :  mem_out_dec = 6'b010001;
1957 
      12'd489  :  mem_out_dec = 6'b010010;
1958 
      12'd490  :  mem_out_dec = 6'b010011;
1959 
      12'd491  :  mem_out_dec = 6'b010100;
1960 
      12'd492  :  mem_out_dec = 6'b010101;
1961 
      12'd493  :  mem_out_dec = 6'b010101;
1962 
      12'd494  :  mem_out_dec = 6'b010110;
1963 
      12'd495  :  mem_out_dec = 6'b010110;
1964 
      12'd496  :  mem_out_dec = 6'b010110;
1965 
      12'd497  :  mem_out_dec = 6'b010110;
1966 
      12'd498  :  mem_out_dec = 6'b010101;
1967 
      12'd499  :  mem_out_dec = 6'b010101;
1968 
      12'd500  :  mem_out_dec = 6'b010110;
1969 
      12'd501  :  mem_out_dec = 6'b010111;
1970 
      12'd502  :  mem_out_dec = 6'b010111;
1971 
      12'd503  :  mem_out_dec = 6'b011000;
1972 
      12'd504  :  mem_out_dec = 6'b011000;
1973 
      12'd505  :  mem_out_dec = 6'b011001;
1974 
      12'd506  :  mem_out_dec = 6'b011010;
1975 
      12'd507  :  mem_out_dec = 6'b011010;
1976 
      12'd508  :  mem_out_dec = 6'b011011;
1977 
      12'd509  :  mem_out_dec = 6'b011100;
1978 
      12'd510  :  mem_out_dec = 6'b011101;
1979 
      12'd511  :  mem_out_dec = 6'b011101;
1980 
      12'd512  :  mem_out_dec = 6'b111111;
1981 
      12'd513  :  mem_out_dec = 6'b111111;
1982 
      12'd514  :  mem_out_dec = 6'b111111;
1983 
      12'd515  :  mem_out_dec = 6'b111111;
1984 
      12'd516  :  mem_out_dec = 6'b111111;
1985 
      12'd517  :  mem_out_dec = 6'b111111;
1986 
      12'd518  :  mem_out_dec = 6'b111111;
1987 
      12'd519  :  mem_out_dec = 6'b111111;
1988 
      12'd520  :  mem_out_dec = 6'b111111;
1989 
      12'd521  :  mem_out_dec = 6'b111111;
1990 
      12'd522  :  mem_out_dec = 6'b111111;
1991 
      12'd523  :  mem_out_dec = 6'b111111;
1992 
      12'd524  :  mem_out_dec = 6'b111111;
1993 
      12'd525  :  mem_out_dec = 6'b111111;
1994 
      12'd526  :  mem_out_dec = 6'b000100;
1995 
      12'd527  :  mem_out_dec = 6'b000101;
1996 
      12'd528  :  mem_out_dec = 6'b000100;
1997 
      12'd529  :  mem_out_dec = 6'b000100;
1998 
      12'd530  :  mem_out_dec = 6'b000100;
1999 
      12'd531  :  mem_out_dec = 6'b000101;
2000 
      12'd532  :  mem_out_dec = 6'b000101;
2001 
      12'd533  :  mem_out_dec = 6'b000110;
2002 
      12'd534  :  mem_out_dec = 6'b000111;
2003 
      12'd535  :  mem_out_dec = 6'b000111;
2004 
      12'd536  :  mem_out_dec = 6'b000111;
2005 
      12'd537  :  mem_out_dec = 6'b001000;
2006 
      12'd538  :  mem_out_dec = 6'b001001;
2007 
      12'd539  :  mem_out_dec = 6'b001010;
2008 
      12'd540  :  mem_out_dec = 6'b001011;
2009 
      12'd541  :  mem_out_dec = 6'b001011;
2010 
      12'd542  :  mem_out_dec = 6'b001100;
2011 
      12'd543  :  mem_out_dec = 6'b001101;
2012 
      12'd544  :  mem_out_dec = 6'b001101;
2013 
      12'd545  :  mem_out_dec = 6'b001101;
2014 
      12'd546  :  mem_out_dec = 6'b001110;
2015 
      12'd547  :  mem_out_dec = 6'b001110;
2016 
      12'd548  :  mem_out_dec = 6'b001110;
2017 
      12'd549  :  mem_out_dec = 6'b001111;
2018 
      12'd550  :  mem_out_dec = 6'b010000;
2019 
      12'd551  :  mem_out_dec = 6'b010000;
2020 
      12'd552  :  mem_out_dec = 6'b010001;
2021 
      12'd553  :  mem_out_dec = 6'b010001;
2022 
      12'd554  :  mem_out_dec = 6'b010010;
2023 
      12'd555  :  mem_out_dec = 6'b010010;
2024 
      12'd556  :  mem_out_dec = 6'b010011;
2025 
      12'd557  :  mem_out_dec = 6'b010100;
2026 
      12'd558  :  mem_out_dec = 6'b010100;
2027 
      12'd559  :  mem_out_dec = 6'b010100;
2028 
      12'd560  :  mem_out_dec = 6'b010100;
2029 
      12'd561  :  mem_out_dec = 6'b010100;
2030 
      12'd562  :  mem_out_dec = 6'b010100;
2031 
      12'd563  :  mem_out_dec = 6'b010101;
2032 
      12'd564  :  mem_out_dec = 6'b010101;
2033 
      12'd565  :  mem_out_dec = 6'b010110;
2034 
      12'd566  :  mem_out_dec = 6'b010111;
2035 
      12'd567  :  mem_out_dec = 6'b010111;
2036 
      12'd568  :  mem_out_dec = 6'b010111;
2037 
      12'd569  :  mem_out_dec = 6'b011000;
2038 
      12'd570  :  mem_out_dec = 6'b011001;
2039 
      12'd571  :  mem_out_dec = 6'b011010;
2040 
      12'd572  :  mem_out_dec = 6'b011010;
2041 
      12'd573  :  mem_out_dec = 6'b011011;
2042 
      12'd574  :  mem_out_dec = 6'b011100;
2043 
      12'd575  :  mem_out_dec = 6'b011101;
2044 
      12'd576  :  mem_out_dec = 6'b111111;
2045 
      12'd577  :  mem_out_dec = 6'b111111;
2046 
      12'd578  :  mem_out_dec = 6'b111111;
2047 
      12'd579  :  mem_out_dec = 6'b111111;
2048 
      12'd580  :  mem_out_dec = 6'b111111;
2049 
      12'd581  :  mem_out_dec = 6'b111111;
2050 
      12'd582  :  mem_out_dec = 6'b111111;
2051 
      12'd583  :  mem_out_dec = 6'b111111;
2052 
      12'd584  :  mem_out_dec = 6'b111111;
2053 
      12'd585  :  mem_out_dec = 6'b111111;
2054 
      12'd586  :  mem_out_dec = 6'b111111;
2055 
      12'd587  :  mem_out_dec = 6'b111111;
2056 
      12'd588  :  mem_out_dec = 6'b111111;
2057 
      12'd589  :  mem_out_dec = 6'b111111;
2058 
      12'd590  :  mem_out_dec = 6'b111111;
2059 
      12'd591  :  mem_out_dec = 6'b000100;
2060 
      12'd592  :  mem_out_dec = 6'b000011;
2061 
      12'd593  :  mem_out_dec = 6'b000011;
2062 
      12'd594  :  mem_out_dec = 6'b000100;
2063 
      12'd595  :  mem_out_dec = 6'b000101;
2064 
      12'd596  :  mem_out_dec = 6'b000101;
2065 
      12'd597  :  mem_out_dec = 6'b000110;
2066 
      12'd598  :  mem_out_dec = 6'b000110;
2067 
      12'd599  :  mem_out_dec = 6'b000111;
2068 
      12'd600  :  mem_out_dec = 6'b000111;
2069 
      12'd601  :  mem_out_dec = 6'b001000;
2070 
      12'd602  :  mem_out_dec = 6'b001001;
2071 
      12'd603  :  mem_out_dec = 6'b001010;
2072 
      12'd604  :  mem_out_dec = 6'b001010;
2073 
      12'd605  :  mem_out_dec = 6'b001011;
2074 
      12'd606  :  mem_out_dec = 6'b001100;
2075 
      12'd607  :  mem_out_dec = 6'b001101;
2076 
      12'd608  :  mem_out_dec = 6'b001101;
2077 
      12'd609  :  mem_out_dec = 6'b001101;
2078 
      12'd610  :  mem_out_dec = 6'b001110;
2079 
      12'd611  :  mem_out_dec = 6'b001110;
2080 
      12'd612  :  mem_out_dec = 6'b001110;
2081 
      12'd613  :  mem_out_dec = 6'b001111;
2082 
      12'd614  :  mem_out_dec = 6'b010000;
2083 
      12'd615  :  mem_out_dec = 6'b010000;
2084 
      12'd616  :  mem_out_dec = 6'b010000;
2085 
      12'd617  :  mem_out_dec = 6'b010001;
2086 
      12'd618  :  mem_out_dec = 6'b010001;
2087 
      12'd619  :  mem_out_dec = 6'b010010;
2088 
      12'd620  :  mem_out_dec = 6'b010010;
2089 
      12'd621  :  mem_out_dec = 6'b010011;
2090 
      12'd622  :  mem_out_dec = 6'b010011;
2091 
      12'd623  :  mem_out_dec = 6'b010100;
2092 
      12'd624  :  mem_out_dec = 6'b010011;
2093 
      12'd625  :  mem_out_dec = 6'b010011;
2094 
      12'd626  :  mem_out_dec = 6'b010100;
2095 
      12'd627  :  mem_out_dec = 6'b010100;
2096 
      12'd628  :  mem_out_dec = 6'b010101;
2097 
      12'd629  :  mem_out_dec = 6'b010110;
2098 
      12'd630  :  mem_out_dec = 6'b010110;
2099 
      12'd631  :  mem_out_dec = 6'b010111;
2100 
      12'd632  :  mem_out_dec = 6'b010111;
2101 
      12'd633  :  mem_out_dec = 6'b011000;
2102 
      12'd634  :  mem_out_dec = 6'b011001;
2103 
      12'd635  :  mem_out_dec = 6'b011001;
2104 
      12'd636  :  mem_out_dec = 6'b011010;
2105 
      12'd637  :  mem_out_dec = 6'b011011;
2106 
      12'd638  :  mem_out_dec = 6'b011100;
2107 
      12'd639  :  mem_out_dec = 6'b011100;
2108 
      12'd640  :  mem_out_dec = 6'b111111;
2109 
      12'd641  :  mem_out_dec = 6'b111111;
2110 
      12'd642  :  mem_out_dec = 6'b111111;
2111 
      12'd643  :  mem_out_dec = 6'b111111;
2112 
      12'd644  :  mem_out_dec = 6'b111111;
2113 
      12'd645  :  mem_out_dec = 6'b111111;
2114 
      12'd646  :  mem_out_dec = 6'b111111;
2115 
      12'd647  :  mem_out_dec = 6'b111111;
2116 
      12'd648  :  mem_out_dec = 6'b111111;
2117 
      12'd649  :  mem_out_dec = 6'b111111;
2118 
      12'd650  :  mem_out_dec = 6'b111111;
2119 
      12'd651  :  mem_out_dec = 6'b111111;
2120 
      12'd652  :  mem_out_dec = 6'b111111;
2121 
      12'd653  :  mem_out_dec = 6'b111111;
2122 
      12'd654  :  mem_out_dec = 6'b111111;
2123 
      12'd655  :  mem_out_dec = 6'b111111;
2124 
      12'd656  :  mem_out_dec = 6'b000011;
2125 
      12'd657  :  mem_out_dec = 6'b000011;
2126 
      12'd658  :  mem_out_dec = 6'b000100;
2127 
      12'd659  :  mem_out_dec = 6'b000100;
2128 
      12'd660  :  mem_out_dec = 6'b000101;
2129 
      12'd661  :  mem_out_dec = 6'b000110;
2130 
      12'd662  :  mem_out_dec = 6'b000110;
2131 
      12'd663  :  mem_out_dec = 6'b000111;
2132 
      12'd664  :  mem_out_dec = 6'b000111;
2133 
      12'd665  :  mem_out_dec = 6'b001000;
2134 
      12'd666  :  mem_out_dec = 6'b001001;
2135 
      12'd667  :  mem_out_dec = 6'b001001;
2136 
      12'd668  :  mem_out_dec = 6'b001010;
2137 
      12'd669  :  mem_out_dec = 6'b001011;
2138 
      12'd670  :  mem_out_dec = 6'b001100;
2139 
      12'd671  :  mem_out_dec = 6'b001100;
2140 
      12'd672  :  mem_out_dec = 6'b001100;
2141 
      12'd673  :  mem_out_dec = 6'b001101;
2142 
      12'd674  :  mem_out_dec = 6'b001101;
2143 
      12'd675  :  mem_out_dec = 6'b001101;
2144 
      12'd676  :  mem_out_dec = 6'b001110;
2145 
      12'd677  :  mem_out_dec = 6'b001111;
2146 
      12'd678  :  mem_out_dec = 6'b001111;
2147 
      12'd679  :  mem_out_dec = 6'b010000;
2148 
      12'd680  :  mem_out_dec = 6'b010000;
2149 
      12'd681  :  mem_out_dec = 6'b010000;
2150 
      12'd682  :  mem_out_dec = 6'b010001;
2151 
      12'd683  :  mem_out_dec = 6'b010001;
2152 
      12'd684  :  mem_out_dec = 6'b010010;
2153 
      12'd685  :  mem_out_dec = 6'b010010;
2154 
      12'd686  :  mem_out_dec = 6'b010011;
2155 
      12'd687  :  mem_out_dec = 6'b010011;
2156 
      12'd688  :  mem_out_dec = 6'b010011;
2157 
      12'd689  :  mem_out_dec = 6'b010011;
2158 
      12'd690  :  mem_out_dec = 6'b010100;
2159 
      12'd691  :  mem_out_dec = 6'b010100;
2160 
      12'd692  :  mem_out_dec = 6'b010101;
2161 
      12'd693  :  mem_out_dec = 6'b010101;
2162 
      12'd694  :  mem_out_dec = 6'b010110;
2163 
      12'd695  :  mem_out_dec = 6'b010111;
2164 
      12'd696  :  mem_out_dec = 6'b010111;
2165 
      12'd697  :  mem_out_dec = 6'b011000;
2166 
      12'd698  :  mem_out_dec = 6'b011000;
2167 
      12'd699  :  mem_out_dec = 6'b011001;
2168 
      12'd700  :  mem_out_dec = 6'b011010;
2169 
      12'd701  :  mem_out_dec = 6'b011011;
2170 
      12'd702  :  mem_out_dec = 6'b011011;
2171 
      12'd703  :  mem_out_dec = 6'b011100;
2172 
      12'd704  :  mem_out_dec = 6'b111111;
2173 
      12'd705  :  mem_out_dec = 6'b111111;
2174 
      12'd706  :  mem_out_dec = 6'b111111;
2175 
      12'd707  :  mem_out_dec = 6'b111111;
2176 
      12'd708  :  mem_out_dec = 6'b111111;
2177 
      12'd709  :  mem_out_dec = 6'b111111;
2178 
      12'd710  :  mem_out_dec = 6'b111111;
2179 
      12'd711  :  mem_out_dec = 6'b111111;
2180 
      12'd712  :  mem_out_dec = 6'b111111;
2181 
      12'd713  :  mem_out_dec = 6'b111111;
2182 
      12'd714  :  mem_out_dec = 6'b111111;
2183 
      12'd715  :  mem_out_dec = 6'b111111;
2184 
      12'd716  :  mem_out_dec = 6'b111111;
2185 
      12'd717  :  mem_out_dec = 6'b111111;
2186 
      12'd718  :  mem_out_dec = 6'b111111;
2187 
      12'd719  :  mem_out_dec = 6'b111111;
2188 
      12'd720  :  mem_out_dec = 6'b111111;
2189 
      12'd721  :  mem_out_dec = 6'b000011;
2190 
      12'd722  :  mem_out_dec = 6'b000100;
2191 
      12'd723  :  mem_out_dec = 6'b000100;
2192 
      12'd724  :  mem_out_dec = 6'b000101;
2193 
      12'd725  :  mem_out_dec = 6'b000101;
2194 
      12'd726  :  mem_out_dec = 6'b000110;
2195 
      12'd727  :  mem_out_dec = 6'b000111;
2196 
      12'd728  :  mem_out_dec = 6'b000111;
2197 
      12'd729  :  mem_out_dec = 6'b000111;
2198 
      12'd730  :  mem_out_dec = 6'b001000;
2199 
      12'd731  :  mem_out_dec = 6'b001001;
2200 
      12'd732  :  mem_out_dec = 6'b001010;
2201 
      12'd733  :  mem_out_dec = 6'b001011;
2202 
      12'd734  :  mem_out_dec = 6'b001011;
2203 
      12'd735  :  mem_out_dec = 6'b001100;
2204 
      12'd736  :  mem_out_dec = 6'b001100;
2205 
      12'd737  :  mem_out_dec = 6'b001101;
2206 
      12'd738  :  mem_out_dec = 6'b001101;
2207 
      12'd739  :  mem_out_dec = 6'b001101;
2208 
      12'd740  :  mem_out_dec = 6'b001110;
2209 
      12'd741  :  mem_out_dec = 6'b001110;
2210 
      12'd742  :  mem_out_dec = 6'b001111;
2211 
      12'd743  :  mem_out_dec = 6'b010000;
2212 
      12'd744  :  mem_out_dec = 6'b001111;
2213 
      12'd745  :  mem_out_dec = 6'b010000;
2214 
      12'd746  :  mem_out_dec = 6'b010000;
2215 
      12'd747  :  mem_out_dec = 6'b010001;
2216 
      12'd748  :  mem_out_dec = 6'b010001;
2217 
      12'd749  :  mem_out_dec = 6'b010010;
2218 
      12'd750  :  mem_out_dec = 6'b010010;
2219 
      12'd751  :  mem_out_dec = 6'b010011;
2220 
      12'd752  :  mem_out_dec = 6'b010010;
2221 
      12'd753  :  mem_out_dec = 6'b010011;
2222 
      12'd754  :  mem_out_dec = 6'b010011;
2223 
      12'd755  :  mem_out_dec = 6'b010100;
2224 
      12'd756  :  mem_out_dec = 6'b010101;
2225 
      12'd757  :  mem_out_dec = 6'b010101;
2226 
      12'd758  :  mem_out_dec = 6'b010110;
2227 
      12'd759  :  mem_out_dec = 6'b010110;
2228 
      12'd760  :  mem_out_dec = 6'b010111;
2229 
      12'd761  :  mem_out_dec = 6'b010111;
2230 
      12'd762  :  mem_out_dec = 6'b011000;
2231 
      12'd763  :  mem_out_dec = 6'b011001;
2232 
      12'd764  :  mem_out_dec = 6'b011010;
2233 
      12'd765  :  mem_out_dec = 6'b011010;
2234 
      12'd766  :  mem_out_dec = 6'b011011;
2235 
      12'd767  :  mem_out_dec = 6'b011100;
2236 
      12'd768  :  mem_out_dec = 6'b111111;
2237 
      12'd769  :  mem_out_dec = 6'b111111;
2238 
      12'd770  :  mem_out_dec = 6'b111111;
2239 
      12'd771  :  mem_out_dec = 6'b111111;
2240 
      12'd772  :  mem_out_dec = 6'b111111;
2241 
      12'd773  :  mem_out_dec = 6'b111111;
2242 
      12'd774  :  mem_out_dec = 6'b111111;
2243 
      12'd775  :  mem_out_dec = 6'b111111;
2244 
      12'd776  :  mem_out_dec = 6'b111111;
2245 
      12'd777  :  mem_out_dec = 6'b111111;
2246 
      12'd778  :  mem_out_dec = 6'b111111;
2247 
      12'd779  :  mem_out_dec = 6'b111111;
2248 
      12'd780  :  mem_out_dec = 6'b111111;
2249 
      12'd781  :  mem_out_dec = 6'b111111;
2250 
      12'd782  :  mem_out_dec = 6'b111111;
2251 
      12'd783  :  mem_out_dec = 6'b111111;
2252 
      12'd784  :  mem_out_dec = 6'b111111;
2253 
      12'd785  :  mem_out_dec = 6'b111111;
2254 
      12'd786  :  mem_out_dec = 6'b000011;
2255 
      12'd787  :  mem_out_dec = 6'b000100;
2256 
      12'd788  :  mem_out_dec = 6'b000101;
2257 
      12'd789  :  mem_out_dec = 6'b000101;
2258 
      12'd790  :  mem_out_dec = 6'b000110;
2259 
      12'd791  :  mem_out_dec = 6'b000110;
2260 
      12'd792  :  mem_out_dec = 6'b000110;
2261 
      12'd793  :  mem_out_dec = 6'b000111;
2262 
      12'd794  :  mem_out_dec = 6'b001000;
2263 
      12'd795  :  mem_out_dec = 6'b001001;
2264 
      12'd796  :  mem_out_dec = 6'b001010;
2265 
      12'd797  :  mem_out_dec = 6'b001010;
2266 
      12'd798  :  mem_out_dec = 6'b001011;
2267 
      12'd799  :  mem_out_dec = 6'b001100;
2268 
      12'd800  :  mem_out_dec = 6'b001100;
2269 
      12'd801  :  mem_out_dec = 6'b001100;
2270 
      12'd802  :  mem_out_dec = 6'b001101;
2271 
      12'd803  :  mem_out_dec = 6'b001101;
2272 
      12'd804  :  mem_out_dec = 6'b001110;
2273 
      12'd805  :  mem_out_dec = 6'b001110;
2274 
      12'd806  :  mem_out_dec = 6'b001111;
2275 
      12'd807  :  mem_out_dec = 6'b010000;
2276 
      12'd808  :  mem_out_dec = 6'b001111;
2277 
      12'd809  :  mem_out_dec = 6'b001111;
2278 
      12'd810  :  mem_out_dec = 6'b010000;
2279 
      12'd811  :  mem_out_dec = 6'b010000;
2280 
      12'd812  :  mem_out_dec = 6'b010001;
2281 
      12'd813  :  mem_out_dec = 6'b010001;
2282 
      12'd814  :  mem_out_dec = 6'b010010;
2283 
      12'd815  :  mem_out_dec = 6'b010010;
2284 
      12'd816  :  mem_out_dec = 6'b010010;
2285 
      12'd817  :  mem_out_dec = 6'b010011;
2286 
      12'd818  :  mem_out_dec = 6'b010011;
2287 
      12'd819  :  mem_out_dec = 6'b010100;
2288 
      12'd820  :  mem_out_dec = 6'b010100;
2289 
      12'd821  :  mem_out_dec = 6'b010101;
2290 
      12'd822  :  mem_out_dec = 6'b010110;
2291 
      12'd823  :  mem_out_dec = 6'b010110;
2292 
      12'd824  :  mem_out_dec = 6'b010110;
2293 
      12'd825  :  mem_out_dec = 6'b010111;
2294 
      12'd826  :  mem_out_dec = 6'b011000;
2295 
      12'd827  :  mem_out_dec = 6'b011001;
2296 
      12'd828  :  mem_out_dec = 6'b011001;
2297 
      12'd829  :  mem_out_dec = 6'b011010;
2298 
      12'd830  :  mem_out_dec = 6'b011011;
2299 
      12'd831  :  mem_out_dec = 6'b011100;
2300 
      12'd832  :  mem_out_dec = 6'b111111;
2301 
      12'd833  :  mem_out_dec = 6'b111111;
2302 
      12'd834  :  mem_out_dec = 6'b111111;
2303 
      12'd835  :  mem_out_dec = 6'b111111;
2304 
      12'd836  :  mem_out_dec = 6'b111111;
2305 
      12'd837  :  mem_out_dec = 6'b111111;
2306 
      12'd838  :  mem_out_dec = 6'b111111;
2307 
      12'd839  :  mem_out_dec = 6'b111111;
2308 
      12'd840  :  mem_out_dec = 6'b111111;
2309 
      12'd841  :  mem_out_dec = 6'b111111;
2310 
      12'd842  :  mem_out_dec = 6'b111111;
2311 
      12'd843  :  mem_out_dec = 6'b111111;
2312 
      12'd844  :  mem_out_dec = 6'b111111;
2313 
      12'd845  :  mem_out_dec = 6'b111111;
2314 
      12'd846  :  mem_out_dec = 6'b111111;
2315 
      12'd847  :  mem_out_dec = 6'b111111;
2316 
      12'd848  :  mem_out_dec = 6'b111111;
2317 
      12'd849  :  mem_out_dec = 6'b111111;
2318 
      12'd850  :  mem_out_dec = 6'b111111;
2319 
      12'd851  :  mem_out_dec = 6'b000100;
2320 
      12'd852  :  mem_out_dec = 6'b000100;
2321 
      12'd853  :  mem_out_dec = 6'b000101;
2322 
      12'd854  :  mem_out_dec = 6'b000101;
2323 
      12'd855  :  mem_out_dec = 6'b000110;
2324 
      12'd856  :  mem_out_dec = 6'b000110;
2325 
      12'd857  :  mem_out_dec = 6'b000111;
2326 
      12'd858  :  mem_out_dec = 6'b001000;
2327 
      12'd859  :  mem_out_dec = 6'b001001;
2328 
      12'd860  :  mem_out_dec = 6'b001001;
2329 
      12'd861  :  mem_out_dec = 6'b001010;
2330 
      12'd862  :  mem_out_dec = 6'b001011;
2331 
      12'd863  :  mem_out_dec = 6'b001100;
2332 
      12'd864  :  mem_out_dec = 6'b001100;
2333 
      12'd865  :  mem_out_dec = 6'b001100;
2334 
      12'd866  :  mem_out_dec = 6'b001100;
2335 
      12'd867  :  mem_out_dec = 6'b001101;
2336 
      12'd868  :  mem_out_dec = 6'b001101;
2337 
      12'd869  :  mem_out_dec = 6'b001110;
2338 
      12'd870  :  mem_out_dec = 6'b001111;
2339 
      12'd871  :  mem_out_dec = 6'b001111;
2340 
      12'd872  :  mem_out_dec = 6'b001110;
2341 
      12'd873  :  mem_out_dec = 6'b001111;
2342 
      12'd874  :  mem_out_dec = 6'b001111;
2343 
      12'd875  :  mem_out_dec = 6'b010000;
2344 
      12'd876  :  mem_out_dec = 6'b010000;
2345 
      12'd877  :  mem_out_dec = 6'b010001;
2346 
      12'd878  :  mem_out_dec = 6'b010001;
2347 
      12'd879  :  mem_out_dec = 6'b010010;
2348 
      12'd880  :  mem_out_dec = 6'b010010;
2349 
      12'd881  :  mem_out_dec = 6'b010010;
2350 
      12'd882  :  mem_out_dec = 6'b010011;
2351 
      12'd883  :  mem_out_dec = 6'b010100;
2352 
      12'd884  :  mem_out_dec = 6'b010100;
2353 
      12'd885  :  mem_out_dec = 6'b010101;
2354 
      12'd886  :  mem_out_dec = 6'b010101;
2355 
      12'd887  :  mem_out_dec = 6'b010110;
2356 
      12'd888  :  mem_out_dec = 6'b010110;
2357 
      12'd889  :  mem_out_dec = 6'b010111;
2358 
      12'd890  :  mem_out_dec = 6'b011000;
2359 
      12'd891  :  mem_out_dec = 6'b011000;
2360 
      12'd892  :  mem_out_dec = 6'b011001;
2361 
      12'd893  :  mem_out_dec = 6'b011010;
2362 
      12'd894  :  mem_out_dec = 6'b011011;
2363 
      12'd895  :  mem_out_dec = 6'b011011;
2364 
      12'd896  :  mem_out_dec = 6'b111111;
2365 
      12'd897  :  mem_out_dec = 6'b111111;
2366 
      12'd898  :  mem_out_dec = 6'b111111;
2367 
      12'd899  :  mem_out_dec = 6'b111111;
2368 
      12'd900  :  mem_out_dec = 6'b111111;
2369 
      12'd901  :  mem_out_dec = 6'b111111;
2370 
      12'd902  :  mem_out_dec = 6'b111111;
2371 
      12'd903  :  mem_out_dec = 6'b111111;
2372 
      12'd904  :  mem_out_dec = 6'b111111;
2373 
      12'd905  :  mem_out_dec = 6'b111111;
2374 
      12'd906  :  mem_out_dec = 6'b111111;
2375 
      12'd907  :  mem_out_dec = 6'b111111;
2376 
      12'd908  :  mem_out_dec = 6'b111111;
2377 
      12'd909  :  mem_out_dec = 6'b111111;
2378 
      12'd910  :  mem_out_dec = 6'b111111;
2379 
      12'd911  :  mem_out_dec = 6'b111111;
2380 
      12'd912  :  mem_out_dec = 6'b111111;
2381 
      12'd913  :  mem_out_dec = 6'b111111;
2382 
      12'd914  :  mem_out_dec = 6'b111111;
2383 
      12'd915  :  mem_out_dec = 6'b111111;
2384 
      12'd916  :  mem_out_dec = 6'b000100;
2385 
      12'd917  :  mem_out_dec = 6'b000101;
2386 
      12'd918  :  mem_out_dec = 6'b000101;
2387 
      12'd919  :  mem_out_dec = 6'b000110;
2388 
      12'd920  :  mem_out_dec = 6'b000110;
2389 
      12'd921  :  mem_out_dec = 6'b000111;
2390 
      12'd922  :  mem_out_dec = 6'b001000;
2391 
      12'd923  :  mem_out_dec = 6'b001000;
2392 
      12'd924  :  mem_out_dec = 6'b001001;
2393 
      12'd925  :  mem_out_dec = 6'b001010;
2394 
      12'd926  :  mem_out_dec = 6'b001011;
2395 
      12'd927  :  mem_out_dec = 6'b001011;
2396 
      12'd928  :  mem_out_dec = 6'b001011;
2397 
      12'd929  :  mem_out_dec = 6'b001100;
2398 
      12'd930  :  mem_out_dec = 6'b001100;
2399 
      12'd931  :  mem_out_dec = 6'b001101;
2400 
      12'd932  :  mem_out_dec = 6'b001101;
2401 
      12'd933  :  mem_out_dec = 6'b001110;
2402 
      12'd934  :  mem_out_dec = 6'b001110;
2403 
      12'd935  :  mem_out_dec = 6'b001111;
2404 
      12'd936  :  mem_out_dec = 6'b001110;
2405 
      12'd937  :  mem_out_dec = 6'b001110;
2406 
      12'd938  :  mem_out_dec = 6'b001111;
2407 
      12'd939  :  mem_out_dec = 6'b001111;
2408 
      12'd940  :  mem_out_dec = 6'b010000;
2409 
      12'd941  :  mem_out_dec = 6'b010000;
2410 
      12'd942  :  mem_out_dec = 6'b010001;
2411 
      12'd943  :  mem_out_dec = 6'b010001;
2412 
      12'd944  :  mem_out_dec = 6'b010010;
2413 
      12'd945  :  mem_out_dec = 6'b010010;
2414 
      12'd946  :  mem_out_dec = 6'b010011;
2415 
      12'd947  :  mem_out_dec = 6'b010011;
2416 
      12'd948  :  mem_out_dec = 6'b010100;
2417 
      12'd949  :  mem_out_dec = 6'b010100;
2418 
      12'd950  :  mem_out_dec = 6'b010101;
2419 
      12'd951  :  mem_out_dec = 6'b010110;
2420 
      12'd952  :  mem_out_dec = 6'b010110;
2421 
      12'd953  :  mem_out_dec = 6'b010111;
2422 
      12'd954  :  mem_out_dec = 6'b010111;
2423 
      12'd955  :  mem_out_dec = 6'b011000;
2424 
      12'd956  :  mem_out_dec = 6'b011001;
2425 
      12'd957  :  mem_out_dec = 6'b011010;
2426 
      12'd958  :  mem_out_dec = 6'b011010;
2427 
      12'd959  :  mem_out_dec = 6'b011011;
2428 
      12'd960  :  mem_out_dec = 6'b111111;
2429 
      12'd961  :  mem_out_dec = 6'b111111;
2430 
      12'd962  :  mem_out_dec = 6'b111111;
2431 
      12'd963  :  mem_out_dec = 6'b111111;
2432 
      12'd964  :  mem_out_dec = 6'b111111;
2433 
      12'd965  :  mem_out_dec = 6'b111111;
2434 
      12'd966  :  mem_out_dec = 6'b111111;
2435 
      12'd967  :  mem_out_dec = 6'b111111;
2436 
      12'd968  :  mem_out_dec = 6'b111111;
2437 
      12'd969  :  mem_out_dec = 6'b111111;
2438 
      12'd970  :  mem_out_dec = 6'b111111;
2439 
      12'd971  :  mem_out_dec = 6'b111111;
2440 
      12'd972  :  mem_out_dec = 6'b111111;
2441 
      12'd973  :  mem_out_dec = 6'b111111;
2442 
      12'd974  :  mem_out_dec = 6'b111111;
2443 
      12'd975  :  mem_out_dec = 6'b111111;
2444 
      12'd976  :  mem_out_dec = 6'b111111;
2445 
      12'd977  :  mem_out_dec = 6'b111111;
2446 
      12'd978  :  mem_out_dec = 6'b111111;
2447 
      12'd979  :  mem_out_dec = 6'b111111;
2448 
      12'd980  :  mem_out_dec = 6'b111111;
2449 
      12'd981  :  mem_out_dec = 6'b000100;
2450 
      12'd982  :  mem_out_dec = 6'b000101;
2451 
      12'd983  :  mem_out_dec = 6'b000110;
2452 
      12'd984  :  mem_out_dec = 6'b000110;
2453 
      12'd985  :  mem_out_dec = 6'b000111;
2454 
      12'd986  :  mem_out_dec = 6'b000111;
2455 
      12'd987  :  mem_out_dec = 6'b001000;
2456 
      12'd988  :  mem_out_dec = 6'b001001;
2457 
      12'd989  :  mem_out_dec = 6'b001010;
2458 
      12'd990  :  mem_out_dec = 6'b001010;
2459 
      12'd991  :  mem_out_dec = 6'b001011;
2460 
      12'd992  :  mem_out_dec = 6'b001011;
2461 
      12'd993  :  mem_out_dec = 6'b001011;
2462 
      12'd994  :  mem_out_dec = 6'b001100;
2463 
      12'd995  :  mem_out_dec = 6'b001100;
2464 
      12'd996  :  mem_out_dec = 6'b001101;
2465 
      12'd997  :  mem_out_dec = 6'b001110;
2466 
      12'd998  :  mem_out_dec = 6'b001110;
2467 
      12'd999  :  mem_out_dec = 6'b001110;
2468 
      12'd1000 :  mem_out_dec = 6'b001101;
2469 
      12'd1001 :  mem_out_dec = 6'b001110;
2470 
      12'd1002 :  mem_out_dec = 6'b001110;
2471 
      12'd1003 :  mem_out_dec = 6'b001111;
2472 
      12'd1004 :  mem_out_dec = 6'b001111;
2473 
      12'd1005 :  mem_out_dec = 6'b010000;
2474 
      12'd1006 :  mem_out_dec = 6'b010000;
2475 
      12'd1007 :  mem_out_dec = 6'b010001;
2476 
      12'd1008 :  mem_out_dec = 6'b010001;
2477 
      12'd1009 :  mem_out_dec = 6'b010010;
2478 
      12'd1010 :  mem_out_dec = 6'b010011;
2479 
      12'd1011 :  mem_out_dec = 6'b010011;
2480 
      12'd1012 :  mem_out_dec = 6'b010100;
2481 
      12'd1013 :  mem_out_dec = 6'b010100;
2482 
      12'd1014 :  mem_out_dec = 6'b010101;
2483 
      12'd1015 :  mem_out_dec = 6'b010110;
2484 
      12'd1016 :  mem_out_dec = 6'b010110;
2485 
      12'd1017 :  mem_out_dec = 6'b010110;
2486 
      12'd1018 :  mem_out_dec = 6'b010111;
2487 
      12'd1019 :  mem_out_dec = 6'b011000;
2488 
      12'd1020 :  mem_out_dec = 6'b011001;
2489 
      12'd1021 :  mem_out_dec = 6'b011001;
2490 
      12'd1022 :  mem_out_dec = 6'b011010;
2491 
      12'd1023 :  mem_out_dec = 6'b011011;
2492 
      12'd1024 :  mem_out_dec = 6'b111111;
2493 
      12'd1025 :  mem_out_dec = 6'b111111;
2494 
      12'd1026 :  mem_out_dec = 6'b111111;
2495 
      12'd1027 :  mem_out_dec = 6'b111111;
2496 
      12'd1028 :  mem_out_dec = 6'b111111;
2497 
      12'd1029 :  mem_out_dec = 6'b111111;
2498 
      12'd1030 :  mem_out_dec = 6'b111111;
2499 
      12'd1031 :  mem_out_dec = 6'b111111;
2500 
      12'd1032 :  mem_out_dec = 6'b111111;
2501 
      12'd1033 :  mem_out_dec = 6'b111111;
2502 
      12'd1034 :  mem_out_dec = 6'b111111;
2503 
      12'd1035 :  mem_out_dec = 6'b111111;
2504 
      12'd1036 :  mem_out_dec = 6'b111111;
2505 
      12'd1037 :  mem_out_dec = 6'b111111;
2506 
      12'd1038 :  mem_out_dec = 6'b111111;
2507 
      12'd1039 :  mem_out_dec = 6'b111111;
2508 
      12'd1040 :  mem_out_dec = 6'b111111;
2509 
      12'd1041 :  mem_out_dec = 6'b111111;
2510 
      12'd1042 :  mem_out_dec = 6'b111111;
2511 
      12'd1043 :  mem_out_dec = 6'b111111;
2512 
      12'd1044 :  mem_out_dec = 6'b111111;
2513 
      12'd1045 :  mem_out_dec = 6'b111111;
2514 
      12'd1046 :  mem_out_dec = 6'b000100;
2515 
      12'd1047 :  mem_out_dec = 6'b000101;
2516 
      12'd1048 :  mem_out_dec = 6'b000101;
2517 
      12'd1049 :  mem_out_dec = 6'b000110;
2518 
      12'd1050 :  mem_out_dec = 6'b000110;
2519 
      12'd1051 :  mem_out_dec = 6'b000111;
2520 
      12'd1052 :  mem_out_dec = 6'b001000;
2521 
      12'd1053 :  mem_out_dec = 6'b001001;
2522 
      12'd1054 :  mem_out_dec = 6'b001001;
2523 
      12'd1055 :  mem_out_dec = 6'b001010;
2524 
      12'd1056 :  mem_out_dec = 6'b001010;
2525 
      12'd1057 :  mem_out_dec = 6'b001011;
2526 
      12'd1058 :  mem_out_dec = 6'b001011;
2527 
      12'd1059 :  mem_out_dec = 6'b001100;
2528 
      12'd1060 :  mem_out_dec = 6'b001100;
2529 
      12'd1061 :  mem_out_dec = 6'b001100;
2530 
      12'd1062 :  mem_out_dec = 6'b001100;
2531 
      12'd1063 :  mem_out_dec = 6'b001100;
2532 
      12'd1064 :  mem_out_dec = 6'b001100;
2533 
      12'd1065 :  mem_out_dec = 6'b001100;
2534 
      12'd1066 :  mem_out_dec = 6'b001101;
2535 
      12'd1067 :  mem_out_dec = 6'b001101;
2536 
      12'd1068 :  mem_out_dec = 6'b001110;
2537 
      12'd1069 :  mem_out_dec = 6'b001111;
2538 
      12'd1070 :  mem_out_dec = 6'b010000;
2539 
      12'd1071 :  mem_out_dec = 6'b010000;
2540 
      12'd1072 :  mem_out_dec = 6'b010001;
2541 
      12'd1073 :  mem_out_dec = 6'b010001;
2542 
      12'd1074 :  mem_out_dec = 6'b010010;
2543 
      12'd1075 :  mem_out_dec = 6'b010010;
2544 
      12'd1076 :  mem_out_dec = 6'b010011;
2545 
      12'd1077 :  mem_out_dec = 6'b010011;
2546 
      12'd1078 :  mem_out_dec = 6'b010100;
2547 
      12'd1079 :  mem_out_dec = 6'b010101;
2548 
      12'd1080 :  mem_out_dec = 6'b010101;
2549 
      12'd1081 :  mem_out_dec = 6'b010110;
2550 
      12'd1082 :  mem_out_dec = 6'b010110;
2551 
      12'd1083 :  mem_out_dec = 6'b010111;
2552 
      12'd1084 :  mem_out_dec = 6'b011000;
2553 
      12'd1085 :  mem_out_dec = 6'b011000;
2554 
      12'd1086 :  mem_out_dec = 6'b011001;
2555 
      12'd1087 :  mem_out_dec = 6'b011010;
2556 
      12'd1088 :  mem_out_dec = 6'b111111;
2557 
      12'd1089 :  mem_out_dec = 6'b111111;
2558 
      12'd1090 :  mem_out_dec = 6'b111111;
2559 
      12'd1091 :  mem_out_dec = 6'b111111;
2560 
      12'd1092 :  mem_out_dec = 6'b111111;
2561 
      12'd1093 :  mem_out_dec = 6'b111111;
2562 
      12'd1094 :  mem_out_dec = 6'b111111;
2563 
      12'd1095 :  mem_out_dec = 6'b111111;
2564 
      12'd1096 :  mem_out_dec = 6'b111111;
2565 
      12'd1097 :  mem_out_dec = 6'b111111;
2566 
      12'd1098 :  mem_out_dec = 6'b111111;
2567 
      12'd1099 :  mem_out_dec = 6'b111111;
2568 
      12'd1100 :  mem_out_dec = 6'b111111;
2569 
      12'd1101 :  mem_out_dec = 6'b111111;
2570 
      12'd1102 :  mem_out_dec = 6'b111111;
2571 
      12'd1103 :  mem_out_dec = 6'b111111;
2572 
      12'd1104 :  mem_out_dec = 6'b111111;
2573 
      12'd1105 :  mem_out_dec = 6'b111111;
2574 
      12'd1106 :  mem_out_dec = 6'b111111;
2575 
      12'd1107 :  mem_out_dec = 6'b111111;
2576 
      12'd1108 :  mem_out_dec = 6'b111111;
2577 
      12'd1109 :  mem_out_dec = 6'b111111;
2578 
      12'd1110 :  mem_out_dec = 6'b111111;
2579 
      12'd1111 :  mem_out_dec = 6'b000100;
2580 
      12'd1112 :  mem_out_dec = 6'b000100;
2581 
      12'd1113 :  mem_out_dec = 6'b000101;
2582 
      12'd1114 :  mem_out_dec = 6'b000110;
2583 
      12'd1115 :  mem_out_dec = 6'b000111;
2584 
      12'd1116 :  mem_out_dec = 6'b000111;
2585 
      12'd1117 :  mem_out_dec = 6'b001000;
2586 
      12'd1118 :  mem_out_dec = 6'b001001;
2587 
      12'd1119 :  mem_out_dec = 6'b001001;
2588 
      12'd1120 :  mem_out_dec = 6'b001010;
2589 
      12'd1121 :  mem_out_dec = 6'b001010;
2590 
      12'd1122 :  mem_out_dec = 6'b001011;
2591 
      12'd1123 :  mem_out_dec = 6'b001011;
2592 
      12'd1124 :  mem_out_dec = 6'b001011;
2593 
      12'd1125 :  mem_out_dec = 6'b001011;
2594 
      12'd1126 :  mem_out_dec = 6'b001011;
2595 
      12'd1127 :  mem_out_dec = 6'b001011;
2596 
      12'd1128 :  mem_out_dec = 6'b001011;
2597 
      12'd1129 :  mem_out_dec = 6'b001011;
2598 
      12'd1130 :  mem_out_dec = 6'b001100;
2599 
      12'd1131 :  mem_out_dec = 6'b001101;
2600 
      12'd1132 :  mem_out_dec = 6'b001110;
2601 
      12'd1133 :  mem_out_dec = 6'b001110;
2602 
      12'd1134 :  mem_out_dec = 6'b001111;
2603 
      12'd1135 :  mem_out_dec = 6'b010000;
2604 
      12'd1136 :  mem_out_dec = 6'b010000;
2605 
      12'd1137 :  mem_out_dec = 6'b010001;
2606 
      12'd1138 :  mem_out_dec = 6'b010001;
2607 
      12'd1139 :  mem_out_dec = 6'b010010;
2608 
      12'd1140 :  mem_out_dec = 6'b010010;
2609 
      12'd1141 :  mem_out_dec = 6'b010011;
2610 
      12'd1142 :  mem_out_dec = 6'b010100;
2611 
      12'd1143 :  mem_out_dec = 6'b010100;
2612 
      12'd1144 :  mem_out_dec = 6'b010100;
2613 
      12'd1145 :  mem_out_dec = 6'b010101;
2614 
      12'd1146 :  mem_out_dec = 6'b010110;
2615 
      12'd1147 :  mem_out_dec = 6'b010110;
2616 
      12'd1148 :  mem_out_dec = 6'b010111;
2617 
      12'd1149 :  mem_out_dec = 6'b011000;
2618 
      12'd1150 :  mem_out_dec = 6'b011000;
2619 
      12'd1151 :  mem_out_dec = 6'b011001;
2620 
      12'd1152 :  mem_out_dec = 6'b111111;
2621 
      12'd1153 :  mem_out_dec = 6'b111111;
2622 
      12'd1154 :  mem_out_dec = 6'b111111;
2623 
      12'd1155 :  mem_out_dec = 6'b111111;
2624 
      12'd1156 :  mem_out_dec = 6'b111111;
2625 
      12'd1157 :  mem_out_dec = 6'b111111;
2626 
      12'd1158 :  mem_out_dec = 6'b111111;
2627 
      12'd1159 :  mem_out_dec = 6'b111111;
2628 
      12'd1160 :  mem_out_dec = 6'b111111;
2629 
      12'd1161 :  mem_out_dec = 6'b111111;
2630 
      12'd1162 :  mem_out_dec = 6'b111111;
2631 
      12'd1163 :  mem_out_dec = 6'b111111;
2632 
      12'd1164 :  mem_out_dec = 6'b111111;
2633 
      12'd1165 :  mem_out_dec = 6'b111111;
2634 
      12'd1166 :  mem_out_dec = 6'b111111;
2635 
      12'd1167 :  mem_out_dec = 6'b111111;
2636 
      12'd1168 :  mem_out_dec = 6'b111111;
2637 
      12'd1169 :  mem_out_dec = 6'b111111;
2638 
      12'd1170 :  mem_out_dec = 6'b111111;
2639 
      12'd1171 :  mem_out_dec = 6'b111111;
2640 
      12'd1172 :  mem_out_dec = 6'b111111;
2641 
      12'd1173 :  mem_out_dec = 6'b111111;
2642 
      12'd1174 :  mem_out_dec = 6'b111111;
2643 
      12'd1175 :  mem_out_dec = 6'b111111;
2644 
      12'd1176 :  mem_out_dec = 6'b000100;
2645 
      12'd1177 :  mem_out_dec = 6'b000101;
2646 
      12'd1178 :  mem_out_dec = 6'b000101;
2647 
      12'd1179 :  mem_out_dec = 6'b000110;
2648 
      12'd1180 :  mem_out_dec = 6'b000111;
2649 
      12'd1181 :  mem_out_dec = 6'b000111;
2650 
      12'd1182 :  mem_out_dec = 6'b001000;
2651 
      12'd1183 :  mem_out_dec = 6'b001001;
2652 
      12'd1184 :  mem_out_dec = 6'b001001;
2653 
      12'd1185 :  mem_out_dec = 6'b001010;
2654 
      12'd1186 :  mem_out_dec = 6'b001010;
2655 
      12'd1187 :  mem_out_dec = 6'b001010;
2656 
      12'd1188 :  mem_out_dec = 6'b001010;
2657 
      12'd1189 :  mem_out_dec = 6'b001010;
2658 
      12'd1190 :  mem_out_dec = 6'b001010;
2659 
      12'd1191 :  mem_out_dec = 6'b001010;
2660 
      12'd1192 :  mem_out_dec = 6'b001010;
2661 
      12'd1193 :  mem_out_dec = 6'b001011;
2662 
      12'd1194 :  mem_out_dec = 6'b001100;
2663 
      12'd1195 :  mem_out_dec = 6'b001100;
2664 
      12'd1196 :  mem_out_dec = 6'b001101;
2665 
      12'd1197 :  mem_out_dec = 6'b001110;
2666 
      12'd1198 :  mem_out_dec = 6'b001111;
2667 
      12'd1199 :  mem_out_dec = 6'b010000;
2668 
      12'd1200 :  mem_out_dec = 6'b010000;
2669 
      12'd1201 :  mem_out_dec = 6'b010000;
2670 
      12'd1202 :  mem_out_dec = 6'b010001;
2671 
      12'd1203 :  mem_out_dec = 6'b010001;
2672 
      12'd1204 :  mem_out_dec = 6'b010010;
2673 
      12'd1205 :  mem_out_dec = 6'b010011;
2674 
      12'd1206 :  mem_out_dec = 6'b010011;
2675 
      12'd1207 :  mem_out_dec = 6'b010100;
2676 
      12'd1208 :  mem_out_dec = 6'b010100;
2677 
      12'd1209 :  mem_out_dec = 6'b010100;
2678 
      12'd1210 :  mem_out_dec = 6'b010101;
2679 
      12'd1211 :  mem_out_dec = 6'b010110;
2680 
      12'd1212 :  mem_out_dec = 6'b010110;
2681 
      12'd1213 :  mem_out_dec = 6'b010111;
2682 
      12'd1214 :  mem_out_dec = 6'b011000;
2683 
      12'd1215 :  mem_out_dec = 6'b011001;
2684 
      12'd1216 :  mem_out_dec = 6'b111111;
2685 
      12'd1217 :  mem_out_dec = 6'b111111;
2686 
      12'd1218 :  mem_out_dec = 6'b111111;
2687 
      12'd1219 :  mem_out_dec = 6'b111111;
2688 
      12'd1220 :  mem_out_dec = 6'b111111;
2689 
      12'd1221 :  mem_out_dec = 6'b111111;
2690 
      12'd1222 :  mem_out_dec = 6'b111111;
2691 
      12'd1223 :  mem_out_dec = 6'b111111;
2692 
      12'd1224 :  mem_out_dec = 6'b111111;
2693 
      12'd1225 :  mem_out_dec = 6'b111111;
2694 
      12'd1226 :  mem_out_dec = 6'b111111;
2695 
      12'd1227 :  mem_out_dec = 6'b111111;
2696 
      12'd1228 :  mem_out_dec = 6'b111111;
2697 
      12'd1229 :  mem_out_dec = 6'b111111;
2698 
      12'd1230 :  mem_out_dec = 6'b111111;
2699 
      12'd1231 :  mem_out_dec = 6'b111111;
2700 
      12'd1232 :  mem_out_dec = 6'b111111;
2701 
      12'd1233 :  mem_out_dec = 6'b111111;
2702 
      12'd1234 :  mem_out_dec = 6'b111111;
2703 
      12'd1235 :  mem_out_dec = 6'b111111;
2704 
      12'd1236 :  mem_out_dec = 6'b111111;
2705 
      12'd1237 :  mem_out_dec = 6'b111111;
2706 
      12'd1238 :  mem_out_dec = 6'b111111;
2707 
      12'd1239 :  mem_out_dec = 6'b111111;
2708 
      12'd1240 :  mem_out_dec = 6'b111111;
2709 
      12'd1241 :  mem_out_dec = 6'b000100;
2710 
      12'd1242 :  mem_out_dec = 6'b000100;
2711 
      12'd1243 :  mem_out_dec = 6'b000101;
2712 
      12'd1244 :  mem_out_dec = 6'b000110;
2713 
      12'd1245 :  mem_out_dec = 6'b000111;
2714 
      12'd1246 :  mem_out_dec = 6'b001000;
2715 
      12'd1247 :  mem_out_dec = 6'b001000;
2716 
      12'd1248 :  mem_out_dec = 6'b001001;
2717 
      12'd1249 :  mem_out_dec = 6'b001001;
2718 
      12'd1250 :  mem_out_dec = 6'b001001;
2719 
      12'd1251 :  mem_out_dec = 6'b001001;
2720 
      12'd1252 :  mem_out_dec = 6'b001001;
2721 
      12'd1253 :  mem_out_dec = 6'b001001;
2722 
      12'd1254 :  mem_out_dec = 6'b001001;
2723 
      12'd1255 :  mem_out_dec = 6'b001001;
2724 
      12'd1256 :  mem_out_dec = 6'b001010;
2725 
      12'd1257 :  mem_out_dec = 6'b001010;
2726 
      12'd1258 :  mem_out_dec = 6'b001011;
2727 
      12'd1259 :  mem_out_dec = 6'b001100;
2728 
      12'd1260 :  mem_out_dec = 6'b001101;
2729 
      12'd1261 :  mem_out_dec = 6'b001110;
2730 
      12'd1262 :  mem_out_dec = 6'b001110;
2731 
      12'd1263 :  mem_out_dec = 6'b001111;
2732 
      12'd1264 :  mem_out_dec = 6'b001111;
2733 
      12'd1265 :  mem_out_dec = 6'b010000;
2734 
      12'd1266 :  mem_out_dec = 6'b010000;
2735 
      12'd1267 :  mem_out_dec = 6'b010001;
2736 
      12'd1268 :  mem_out_dec = 6'b010001;
2737 
      12'd1269 :  mem_out_dec = 6'b010010;
2738 
      12'd1270 :  mem_out_dec = 6'b010011;
2739 
      12'd1271 :  mem_out_dec = 6'b010011;
2740 
      12'd1272 :  mem_out_dec = 6'b010011;
2741 
      12'd1273 :  mem_out_dec = 6'b010100;
2742 
      12'd1274 :  mem_out_dec = 6'b010100;
2743 
      12'd1275 :  mem_out_dec = 6'b010101;
2744 
      12'd1276 :  mem_out_dec = 6'b010110;
2745 
      12'd1277 :  mem_out_dec = 6'b010111;
2746 
      12'd1278 :  mem_out_dec = 6'b011000;
2747 
      12'd1279 :  mem_out_dec = 6'b011000;
2748 
      12'd1280 :  mem_out_dec = 6'b111111;
2749 
      12'd1281 :  mem_out_dec = 6'b111111;
2750 
      12'd1282 :  mem_out_dec = 6'b111111;
2751 
      12'd1283 :  mem_out_dec = 6'b111111;
2752 
      12'd1284 :  mem_out_dec = 6'b111111;
2753 
      12'd1285 :  mem_out_dec = 6'b111111;
2754 
      12'd1286 :  mem_out_dec = 6'b111111;
2755 
      12'd1287 :  mem_out_dec = 6'b111111;
2756 
      12'd1288 :  mem_out_dec = 6'b111111;
2757 
      12'd1289 :  mem_out_dec = 6'b111111;
2758 
      12'd1290 :  mem_out_dec = 6'b111111;
2759 
      12'd1291 :  mem_out_dec = 6'b111111;
2760 
      12'd1292 :  mem_out_dec = 6'b111111;
2761 
      12'd1293 :  mem_out_dec = 6'b111111;
2762 
      12'd1294 :  mem_out_dec = 6'b111111;
2763 
      12'd1295 :  mem_out_dec = 6'b111111;
2764 
      12'd1296 :  mem_out_dec = 6'b111111;
2765 
      12'd1297 :  mem_out_dec = 6'b111111;
2766 
      12'd1298 :  mem_out_dec = 6'b111111;
2767 
      12'd1299 :  mem_out_dec = 6'b111111;
2768 
      12'd1300 :  mem_out_dec = 6'b111111;
2769 
      12'd1301 :  mem_out_dec = 6'b111111;
2770 
      12'd1302 :  mem_out_dec = 6'b111111;
2771 
      12'd1303 :  mem_out_dec = 6'b111111;
2772 
      12'd1304 :  mem_out_dec = 6'b111111;
2773 
      12'd1305 :  mem_out_dec = 6'b111111;
2774 
      12'd1306 :  mem_out_dec = 6'b000100;
2775 
      12'd1307 :  mem_out_dec = 6'b000101;
2776 
      12'd1308 :  mem_out_dec = 6'b000110;
2777 
      12'd1309 :  mem_out_dec = 6'b000110;
2778 
      12'd1310 :  mem_out_dec = 6'b000111;
2779 
      12'd1311 :  mem_out_dec = 6'b001000;
2780 
      12'd1312 :  mem_out_dec = 6'b001000;
2781 
      12'd1313 :  mem_out_dec = 6'b001000;
2782 
      12'd1314 :  mem_out_dec = 6'b001000;
2783 
      12'd1315 :  mem_out_dec = 6'b001000;
2784 
      12'd1316 :  mem_out_dec = 6'b001000;
2785 
      12'd1317 :  mem_out_dec = 6'b001000;
2786 
      12'd1318 :  mem_out_dec = 6'b001000;
2787 
      12'd1319 :  mem_out_dec = 6'b001001;
2788 
      12'd1320 :  mem_out_dec = 6'b001001;
2789 
      12'd1321 :  mem_out_dec = 6'b001010;
2790 
      12'd1322 :  mem_out_dec = 6'b001011;
2791 
      12'd1323 :  mem_out_dec = 6'b001100;
2792 
      12'd1324 :  mem_out_dec = 6'b001100;
2793 
      12'd1325 :  mem_out_dec = 6'b001101;
2794 
      12'd1326 :  mem_out_dec = 6'b001110;
2795 
      12'd1327 :  mem_out_dec = 6'b001111;
2796 
      12'd1328 :  mem_out_dec = 6'b001111;
2797 
      12'd1329 :  mem_out_dec = 6'b001111;
2798 
      12'd1330 :  mem_out_dec = 6'b010000;
2799 
      12'd1331 :  mem_out_dec = 6'b010000;
2800 
      12'd1332 :  mem_out_dec = 6'b010001;
2801 
      12'd1333 :  mem_out_dec = 6'b010001;
2802 
      12'd1334 :  mem_out_dec = 6'b010010;
2803 
      12'd1335 :  mem_out_dec = 6'b010011;
2804 
      12'd1336 :  mem_out_dec = 6'b010010;
2805 
      12'd1337 :  mem_out_dec = 6'b010011;
2806 
      12'd1338 :  mem_out_dec = 6'b010100;
2807 
      12'd1339 :  mem_out_dec = 6'b010101;
2808 
      12'd1340 :  mem_out_dec = 6'b010110;
2809 
      12'd1341 :  mem_out_dec = 6'b010110;
2810 
      12'd1342 :  mem_out_dec = 6'b010111;
2811 
      12'd1343 :  mem_out_dec = 6'b011000;
2812 
      12'd1344 :  mem_out_dec = 6'b111111;
2813 
      12'd1345 :  mem_out_dec = 6'b111111;
2814 
      12'd1346 :  mem_out_dec = 6'b111111;
2815 
      12'd1347 :  mem_out_dec = 6'b111111;
2816 
      12'd1348 :  mem_out_dec = 6'b111111;
2817 
      12'd1349 :  mem_out_dec = 6'b111111;
2818 
      12'd1350 :  mem_out_dec = 6'b111111;
2819 
      12'd1351 :  mem_out_dec = 6'b111111;
2820 
      12'd1352 :  mem_out_dec = 6'b111111;
2821 
      12'd1353 :  mem_out_dec = 6'b111111;
2822 
      12'd1354 :  mem_out_dec = 6'b111111;
2823 
      12'd1355 :  mem_out_dec = 6'b111111;
2824 
      12'd1356 :  mem_out_dec = 6'b111111;
2825 
      12'd1357 :  mem_out_dec = 6'b111111;
2826 
      12'd1358 :  mem_out_dec = 6'b111111;
2827 
      12'd1359 :  mem_out_dec = 6'b111111;
2828 
      12'd1360 :  mem_out_dec = 6'b111111;
2829 
      12'd1361 :  mem_out_dec = 6'b111111;
2830 
      12'd1362 :  mem_out_dec = 6'b111111;
2831 
      12'd1363 :  mem_out_dec = 6'b111111;
2832 
      12'd1364 :  mem_out_dec = 6'b111111;
2833 
      12'd1365 :  mem_out_dec = 6'b111111;
2834 
      12'd1366 :  mem_out_dec = 6'b111111;
2835 
      12'd1367 :  mem_out_dec = 6'b111111;
2836 
      12'd1368 :  mem_out_dec = 6'b111111;
2837 
      12'd1369 :  mem_out_dec = 6'b111111;
2838 
      12'd1370 :  mem_out_dec = 6'b111111;
2839 
      12'd1371 :  mem_out_dec = 6'b000101;
2840 
      12'd1372 :  mem_out_dec = 6'b000101;
2841 
      12'd1373 :  mem_out_dec = 6'b000110;
2842 
      12'd1374 :  mem_out_dec = 6'b000111;
2843 
      12'd1375 :  mem_out_dec = 6'b001000;
2844 
      12'd1376 :  mem_out_dec = 6'b000111;
2845 
      12'd1377 :  mem_out_dec = 6'b000111;
2846 
      12'd1378 :  mem_out_dec = 6'b000111;
2847 
      12'd1379 :  mem_out_dec = 6'b000111;
2848 
      12'd1380 :  mem_out_dec = 6'b000111;
2849 
      12'd1381 :  mem_out_dec = 6'b000111;
2850 
      12'd1382 :  mem_out_dec = 6'b001000;
2851 
      12'd1383 :  mem_out_dec = 6'b001001;
2852 
      12'd1384 :  mem_out_dec = 6'b001001;
2853 
      12'd1385 :  mem_out_dec = 6'b001010;
2854 
      12'd1386 :  mem_out_dec = 6'b001010;
2855 
      12'd1387 :  mem_out_dec = 6'b001011;
2856 
      12'd1388 :  mem_out_dec = 6'b001100;
2857 
      12'd1389 :  mem_out_dec = 6'b001101;
2858 
      12'd1390 :  mem_out_dec = 6'b001110;
2859 
      12'd1391 :  mem_out_dec = 6'b001110;
2860 
      12'd1392 :  mem_out_dec = 6'b001111;
2861 
      12'd1393 :  mem_out_dec = 6'b001111;
2862 
      12'd1394 :  mem_out_dec = 6'b010000;
2863 
      12'd1395 :  mem_out_dec = 6'b010000;
2864 
      12'd1396 :  mem_out_dec = 6'b010001;
2865 
      12'd1397 :  mem_out_dec = 6'b010001;
2866 
      12'd1398 :  mem_out_dec = 6'b010010;
2867 
      12'd1399 :  mem_out_dec = 6'b010010;
2868 
      12'd1400 :  mem_out_dec = 6'b010010;
2869 
      12'd1401 :  mem_out_dec = 6'b010011;
2870 
      12'd1402 :  mem_out_dec = 6'b010100;
2871 
      12'd1403 :  mem_out_dec = 6'b010100;
2872 
      12'd1404 :  mem_out_dec = 6'b010101;
2873 
      12'd1405 :  mem_out_dec = 6'b010110;
2874 
      12'd1406 :  mem_out_dec = 6'b010111;
2875 
      12'd1407 :  mem_out_dec = 6'b010111;
2876 
      12'd1408 :  mem_out_dec = 6'b111111;
2877 
      12'd1409 :  mem_out_dec = 6'b111111;
2878 
      12'd1410 :  mem_out_dec = 6'b111111;
2879 
      12'd1411 :  mem_out_dec = 6'b111111;
2880 
      12'd1412 :  mem_out_dec = 6'b111111;
2881 
      12'd1413 :  mem_out_dec = 6'b111111;
2882 
      12'd1414 :  mem_out_dec = 6'b111111;
2883 
      12'd1415 :  mem_out_dec = 6'b111111;
2884 
      12'd1416 :  mem_out_dec = 6'b111111;
2885 
      12'd1417 :  mem_out_dec = 6'b111111;
2886 
      12'd1418 :  mem_out_dec = 6'b111111;
2887 
      12'd1419 :  mem_out_dec = 6'b111111;
2888 
      12'd1420 :  mem_out_dec = 6'b111111;
2889 
      12'd1421 :  mem_out_dec = 6'b111111;
2890 
      12'd1422 :  mem_out_dec = 6'b111111;
2891 
      12'd1423 :  mem_out_dec = 6'b111111;
2892 
      12'd1424 :  mem_out_dec = 6'b111111;
2893 
      12'd1425 :  mem_out_dec = 6'b111111;
2894 
      12'd1426 :  mem_out_dec = 6'b111111;
2895 
      12'd1427 :  mem_out_dec = 6'b111111;
2896 
      12'd1428 :  mem_out_dec = 6'b111111;
2897 
      12'd1429 :  mem_out_dec = 6'b111111;
2898 
      12'd1430 :  mem_out_dec = 6'b111111;
2899 
      12'd1431 :  mem_out_dec = 6'b111111;
2900 
      12'd1432 :  mem_out_dec = 6'b111111;
2901 
      12'd1433 :  mem_out_dec = 6'b111111;
2902 
      12'd1434 :  mem_out_dec = 6'b111111;
2903 
      12'd1435 :  mem_out_dec = 6'b111111;
2904 
      12'd1436 :  mem_out_dec = 6'b000101;
2905 
      12'd1437 :  mem_out_dec = 6'b000110;
2906 
      12'd1438 :  mem_out_dec = 6'b000111;
2907 
      12'd1439 :  mem_out_dec = 6'b000111;
2908 
      12'd1440 :  mem_out_dec = 6'b000110;
2909 
      12'd1441 :  mem_out_dec = 6'b000110;
2910 
      12'd1442 :  mem_out_dec = 6'b000110;
2911 
      12'd1443 :  mem_out_dec = 6'b000110;
2912 
      12'd1444 :  mem_out_dec = 6'b000110;
2913 
      12'd1445 :  mem_out_dec = 6'b000111;
2914 
      12'd1446 :  mem_out_dec = 6'b000111;
2915 
      12'd1447 :  mem_out_dec = 6'b001000;
2916 
      12'd1448 :  mem_out_dec = 6'b001001;
2917 
      12'd1449 :  mem_out_dec = 6'b001001;
2918 
      12'd1450 :  mem_out_dec = 6'b001010;
2919 
      12'd1451 :  mem_out_dec = 6'b001011;
2920 
      12'd1452 :  mem_out_dec = 6'b001100;
2921 
      12'd1453 :  mem_out_dec = 6'b001100;
2922 
      12'd1454 :  mem_out_dec = 6'b001101;
2923 
      12'd1455 :  mem_out_dec = 6'b001110;
2924 
      12'd1456 :  mem_out_dec = 6'b001110;
2925 
      12'd1457 :  mem_out_dec = 6'b001111;
2926 
      12'd1458 :  mem_out_dec = 6'b001111;
2927 
      12'd1459 :  mem_out_dec = 6'b010000;
2928 
      12'd1460 :  mem_out_dec = 6'b010000;
2929 
      12'd1461 :  mem_out_dec = 6'b010001;
2930 
      12'd1462 :  mem_out_dec = 6'b010001;
2931 
      12'd1463 :  mem_out_dec = 6'b010010;
2932 
      12'd1464 :  mem_out_dec = 6'b010010;
2933 
      12'd1465 :  mem_out_dec = 6'b010011;
2934 
      12'd1466 :  mem_out_dec = 6'b010011;
2935 
      12'd1467 :  mem_out_dec = 6'b010100;
2936 
      12'd1468 :  mem_out_dec = 6'b010101;
2937 
      12'd1469 :  mem_out_dec = 6'b010110;
2938 
      12'd1470 :  mem_out_dec = 6'b010110;
2939 
      12'd1471 :  mem_out_dec = 6'b010111;
2940 
      12'd1472 :  mem_out_dec = 6'b111111;
2941 
      12'd1473 :  mem_out_dec = 6'b111111;
2942 
      12'd1474 :  mem_out_dec = 6'b111111;
2943 
      12'd1475 :  mem_out_dec = 6'b111111;
2944 
      12'd1476 :  mem_out_dec = 6'b111111;
2945 
      12'd1477 :  mem_out_dec = 6'b111111;
2946 
      12'd1478 :  mem_out_dec = 6'b111111;
2947 
      12'd1479 :  mem_out_dec = 6'b111111;
2948 
      12'd1480 :  mem_out_dec = 6'b111111;
2949 
      12'd1481 :  mem_out_dec = 6'b111111;
2950 
      12'd1482 :  mem_out_dec = 6'b111111;
2951 
      12'd1483 :  mem_out_dec = 6'b111111;
2952 
      12'd1484 :  mem_out_dec = 6'b111111;
2953 
      12'd1485 :  mem_out_dec = 6'b111111;
2954 
      12'd1486 :  mem_out_dec = 6'b111111;
2955 
      12'd1487 :  mem_out_dec = 6'b111111;
2956 
      12'd1488 :  mem_out_dec = 6'b111111;
2957 
      12'd1489 :  mem_out_dec = 6'b111111;
2958 
      12'd1490 :  mem_out_dec = 6'b111111;
2959 
      12'd1491 :  mem_out_dec = 6'b111111;
2960 
      12'd1492 :  mem_out_dec = 6'b111111;
2961 
      12'd1493 :  mem_out_dec = 6'b111111;
2962 
      12'd1494 :  mem_out_dec = 6'b111111;
2963 
      12'd1495 :  mem_out_dec = 6'b111111;
2964 
      12'd1496 :  mem_out_dec = 6'b111111;
2965 
      12'd1497 :  mem_out_dec = 6'b111111;
2966 
      12'd1498 :  mem_out_dec = 6'b111111;
2967 
      12'd1499 :  mem_out_dec = 6'b111111;
2968 
      12'd1500 :  mem_out_dec = 6'b111111;
2969 
      12'd1501 :  mem_out_dec = 6'b000101;
2970 
      12'd1502 :  mem_out_dec = 6'b000110;
2971 
      12'd1503 :  mem_out_dec = 6'b000110;
2972 
      12'd1504 :  mem_out_dec = 6'b000110;
2973 
      12'd1505 :  mem_out_dec = 6'b000110;
2974 
      12'd1506 :  mem_out_dec = 6'b000101;
2975 
      12'd1507 :  mem_out_dec = 6'b000101;
2976 
      12'd1508 :  mem_out_dec = 6'b000110;
2977 
      12'd1509 :  mem_out_dec = 6'b000111;
2978 
      12'd1510 :  mem_out_dec = 6'b000111;
2979 
      12'd1511 :  mem_out_dec = 6'b001000;
2980 
      12'd1512 :  mem_out_dec = 6'b001000;
2981 
      12'd1513 :  mem_out_dec = 6'b001001;
2982 
      12'd1514 :  mem_out_dec = 6'b001010;
2983 
      12'd1515 :  mem_out_dec = 6'b001011;
2984 
      12'd1516 :  mem_out_dec = 6'b001011;
2985 
      12'd1517 :  mem_out_dec = 6'b001100;
2986 
      12'd1518 :  mem_out_dec = 6'b001101;
2987 
      12'd1519 :  mem_out_dec = 6'b001110;
2988 
      12'd1520 :  mem_out_dec = 6'b001110;
2989 
      12'd1521 :  mem_out_dec = 6'b001110;
2990 
      12'd1522 :  mem_out_dec = 6'b001111;
2991 
      12'd1523 :  mem_out_dec = 6'b001111;
2992 
      12'd1524 :  mem_out_dec = 6'b010000;
2993 
      12'd1525 :  mem_out_dec = 6'b010000;
2994 
      12'd1526 :  mem_out_dec = 6'b010001;
2995 
      12'd1527 :  mem_out_dec = 6'b010001;
2996 
      12'd1528 :  mem_out_dec = 6'b010001;
2997 
      12'd1529 :  mem_out_dec = 6'b010010;
2998 
      12'd1530 :  mem_out_dec = 6'b010011;
2999 
      12'd1531 :  mem_out_dec = 6'b010100;
3000 
      12'd1532 :  mem_out_dec = 6'b010101;
3001 
      12'd1533 :  mem_out_dec = 6'b010101;
3002 
      12'd1534 :  mem_out_dec = 6'b010110;
3003 
      12'd1535 :  mem_out_dec = 6'b010110;
3004 
      12'd1536 :  mem_out_dec = 6'b111111;
3005 
      12'd1537 :  mem_out_dec = 6'b111111;
3006 
      12'd1538 :  mem_out_dec = 6'b111111;
3007 
      12'd1539 :  mem_out_dec = 6'b111111;
3008 
      12'd1540 :  mem_out_dec = 6'b111111;
3009 
      12'd1541 :  mem_out_dec = 6'b111111;
3010 
      12'd1542 :  mem_out_dec = 6'b111111;
3011 
      12'd1543 :  mem_out_dec = 6'b111111;
3012 
      12'd1544 :  mem_out_dec = 6'b111111;
3013 
      12'd1545 :  mem_out_dec = 6'b111111;
3014 
      12'd1546 :  mem_out_dec = 6'b111111;
3015 
      12'd1547 :  mem_out_dec = 6'b111111;
3016 
      12'd1548 :  mem_out_dec = 6'b111111;
3017 
      12'd1549 :  mem_out_dec = 6'b111111;
3018 
      12'd1550 :  mem_out_dec = 6'b111111;
3019 
      12'd1551 :  mem_out_dec = 6'b111111;
3020 
      12'd1552 :  mem_out_dec = 6'b111111;
3021 
      12'd1553 :  mem_out_dec = 6'b111111;
3022 
      12'd1554 :  mem_out_dec = 6'b111111;
3023 
      12'd1555 :  mem_out_dec = 6'b111111;
3024 
      12'd1556 :  mem_out_dec = 6'b111111;
3025 
      12'd1557 :  mem_out_dec = 6'b111111;
3026 
      12'd1558 :  mem_out_dec = 6'b111111;
3027 
      12'd1559 :  mem_out_dec = 6'b111111;
3028 
      12'd1560 :  mem_out_dec = 6'b111111;
3029 
      12'd1561 :  mem_out_dec = 6'b111111;
3030 
      12'd1562 :  mem_out_dec = 6'b111111;
3031 
      12'd1563 :  mem_out_dec = 6'b111111;
3032 
      12'd1564 :  mem_out_dec = 6'b111111;
3033 
      12'd1565 :  mem_out_dec = 6'b111111;
3034 
      12'd1566 :  mem_out_dec = 6'b000100;
3035 
      12'd1567 :  mem_out_dec = 6'b000100;
3036 
      12'd1568 :  mem_out_dec = 6'b000100;
3037 
      12'd1569 :  mem_out_dec = 6'b000100;
3038 
      12'd1570 :  mem_out_dec = 6'b000100;
3039 
      12'd1571 :  mem_out_dec = 6'b000101;
3040 
      12'd1572 :  mem_out_dec = 6'b000101;
3041 
      12'd1573 :  mem_out_dec = 6'b000110;
3042 
      12'd1574 :  mem_out_dec = 6'b000111;
3043 
      12'd1575 :  mem_out_dec = 6'b000111;
3044 
      12'd1576 :  mem_out_dec = 6'b000111;
3045 
      12'd1577 :  mem_out_dec = 6'b001000;
3046 
      12'd1578 :  mem_out_dec = 6'b001001;
3047 
      12'd1579 :  mem_out_dec = 6'b001010;
3048 
      12'd1580 :  mem_out_dec = 6'b001010;
3049 
      12'd1581 :  mem_out_dec = 6'b001011;
3050 
      12'd1582 :  mem_out_dec = 6'b001100;
3051 
      12'd1583 :  mem_out_dec = 6'b001101;
3052 
      12'd1584 :  mem_out_dec = 6'b001101;
3053 
      12'd1585 :  mem_out_dec = 6'b001101;
3054 
      12'd1586 :  mem_out_dec = 6'b001110;
3055 
      12'd1587 :  mem_out_dec = 6'b001110;
3056 
      12'd1588 :  mem_out_dec = 6'b001111;
3057 
      12'd1589 :  mem_out_dec = 6'b001111;
3058 
      12'd1590 :  mem_out_dec = 6'b010000;
3059 
      12'd1591 :  mem_out_dec = 6'b010001;
3060 
      12'd1592 :  mem_out_dec = 6'b010001;
3061 
      12'd1593 :  mem_out_dec = 6'b010001;
3062 
      12'd1594 :  mem_out_dec = 6'b010010;
3063 
      12'd1595 :  mem_out_dec = 6'b010010;
3064 
      12'd1596 :  mem_out_dec = 6'b010011;
3065 
      12'd1597 :  mem_out_dec = 6'b010011;
3066 
      12'd1598 :  mem_out_dec = 6'b010100;
3067 
      12'd1599 :  mem_out_dec = 6'b010100;
3068 
      12'd1600 :  mem_out_dec = 6'b111111;
3069 
      12'd1601 :  mem_out_dec = 6'b111111;
3070 
      12'd1602 :  mem_out_dec = 6'b111111;
3071 
      12'd1603 :  mem_out_dec = 6'b111111;
3072 
      12'd1604 :  mem_out_dec = 6'b111111;
3073 
      12'd1605 :  mem_out_dec = 6'b111111;
3074 
      12'd1606 :  mem_out_dec = 6'b111111;
3075 
      12'd1607 :  mem_out_dec = 6'b111111;
3076 
      12'd1608 :  mem_out_dec = 6'b111111;
3077 
      12'd1609 :  mem_out_dec = 6'b111111;
3078 
      12'd1610 :  mem_out_dec = 6'b111111;
3079 
      12'd1611 :  mem_out_dec = 6'b111111;
3080 
      12'd1612 :  mem_out_dec = 6'b111111;
3081 
      12'd1613 :  mem_out_dec = 6'b111111;
3082 
      12'd1614 :  mem_out_dec = 6'b111111;
3083 
      12'd1615 :  mem_out_dec = 6'b111111;
3084 
      12'd1616 :  mem_out_dec = 6'b111111;
3085 
      12'd1617 :  mem_out_dec = 6'b111111;
3086 
      12'd1618 :  mem_out_dec = 6'b111111;
3087 
      12'd1619 :  mem_out_dec = 6'b111111;
3088 
      12'd1620 :  mem_out_dec = 6'b111111;
3089 
      12'd1621 :  mem_out_dec = 6'b111111;
3090 
      12'd1622 :  mem_out_dec = 6'b111111;
3091 
      12'd1623 :  mem_out_dec = 6'b111111;
3092 
      12'd1624 :  mem_out_dec = 6'b111111;
3093 
      12'd1625 :  mem_out_dec = 6'b111111;
3094 
      12'd1626 :  mem_out_dec = 6'b111111;
3095 
      12'd1627 :  mem_out_dec = 6'b111111;
3096 
      12'd1628 :  mem_out_dec = 6'b111111;
3097 
      12'd1629 :  mem_out_dec = 6'b111111;
3098 
      12'd1630 :  mem_out_dec = 6'b111111;
3099 
      12'd1631 :  mem_out_dec = 6'b000100;
3100 
      12'd1632 :  mem_out_dec = 6'b000011;
3101 
      12'd1633 :  mem_out_dec = 6'b000011;
3102 
      12'd1634 :  mem_out_dec = 6'b000100;
3103 
      12'd1635 :  mem_out_dec = 6'b000100;
3104 
      12'd1636 :  mem_out_dec = 6'b000101;
3105 
      12'd1637 :  mem_out_dec = 6'b000110;
3106 
      12'd1638 :  mem_out_dec = 6'b000110;
3107 
      12'd1639 :  mem_out_dec = 6'b000111;
3108 
      12'd1640 :  mem_out_dec = 6'b000111;
3109 
      12'd1641 :  mem_out_dec = 6'b001000;
3110 
      12'd1642 :  mem_out_dec = 6'b001001;
3111 
      12'd1643 :  mem_out_dec = 6'b001001;
3112 
      12'd1644 :  mem_out_dec = 6'b001010;
3113 
      12'd1645 :  mem_out_dec = 6'b001011;
3114 
      12'd1646 :  mem_out_dec = 6'b001100;
3115 
      12'd1647 :  mem_out_dec = 6'b001101;
3116 
      12'd1648 :  mem_out_dec = 6'b001101;
3117 
      12'd1649 :  mem_out_dec = 6'b001101;
3118 
      12'd1650 :  mem_out_dec = 6'b001110;
3119 
      12'd1651 :  mem_out_dec = 6'b001110;
3120 
      12'd1652 :  mem_out_dec = 6'b001110;
3121 
      12'd1653 :  mem_out_dec = 6'b001111;
3122 
      12'd1654 :  mem_out_dec = 6'b010000;
3123 
      12'd1655 :  mem_out_dec = 6'b010000;
3124 
      12'd1656 :  mem_out_dec = 6'b010001;
3125 
      12'd1657 :  mem_out_dec = 6'b010001;
3126 
      12'd1658 :  mem_out_dec = 6'b010001;
3127 
      12'd1659 :  mem_out_dec = 6'b010010;
3128 
      12'd1660 :  mem_out_dec = 6'b010010;
3129 
      12'd1661 :  mem_out_dec = 6'b010011;
3130 
      12'd1662 :  mem_out_dec = 6'b010011;
3131 
      12'd1663 :  mem_out_dec = 6'b010100;
3132 
      12'd1664 :  mem_out_dec = 6'b111111;
3133 
      12'd1665 :  mem_out_dec = 6'b111111;
3134 
      12'd1666 :  mem_out_dec = 6'b111111;
3135 
      12'd1667 :  mem_out_dec = 6'b111111;
3136 
      12'd1668 :  mem_out_dec = 6'b111111;
3137 
      12'd1669 :  mem_out_dec = 6'b111111;
3138 
      12'd1670 :  mem_out_dec = 6'b111111;
3139 
      12'd1671 :  mem_out_dec = 6'b111111;
3140 
      12'd1672 :  mem_out_dec = 6'b111111;
3141 
      12'd1673 :  mem_out_dec = 6'b111111;
3142 
      12'd1674 :  mem_out_dec = 6'b111111;
3143 
      12'd1675 :  mem_out_dec = 6'b111111;
3144 
      12'd1676 :  mem_out_dec = 6'b111111;
3145 
      12'd1677 :  mem_out_dec = 6'b111111;
3146 
      12'd1678 :  mem_out_dec = 6'b111111;
3147 
      12'd1679 :  mem_out_dec = 6'b111111;
3148 
      12'd1680 :  mem_out_dec = 6'b111111;
3149 
      12'd1681 :  mem_out_dec = 6'b111111;
3150 
      12'd1682 :  mem_out_dec = 6'b111111;
3151 
      12'd1683 :  mem_out_dec = 6'b111111;
3152 
      12'd1684 :  mem_out_dec = 6'b111111;
3153 
      12'd1685 :  mem_out_dec = 6'b111111;
3154 
      12'd1686 :  mem_out_dec = 6'b111111;
3155 
      12'd1687 :  mem_out_dec = 6'b111111;
3156 
      12'd1688 :  mem_out_dec = 6'b111111;
3157 
      12'd1689 :  mem_out_dec = 6'b111111;
3158 
      12'd1690 :  mem_out_dec = 6'b111111;
3159 
      12'd1691 :  mem_out_dec = 6'b111111;
3160 
      12'd1692 :  mem_out_dec = 6'b111111;
3161 
      12'd1693 :  mem_out_dec = 6'b111111;
3162 
      12'd1694 :  mem_out_dec = 6'b111111;
3163 
      12'd1695 :  mem_out_dec = 6'b111111;
3164 
      12'd1696 :  mem_out_dec = 6'b000011;
3165 
      12'd1697 :  mem_out_dec = 6'b000011;
3166 
      12'd1698 :  mem_out_dec = 6'b000100;
3167 
      12'd1699 :  mem_out_dec = 6'b000100;
3168 
      12'd1700 :  mem_out_dec = 6'b000101;
3169 
      12'd1701 :  mem_out_dec = 6'b000101;
3170 
      12'd1702 :  mem_out_dec = 6'b000110;
3171 
      12'd1703 :  mem_out_dec = 6'b000111;
3172 
      12'd1704 :  mem_out_dec = 6'b000111;
3173 
      12'd1705 :  mem_out_dec = 6'b001000;
3174 
      12'd1706 :  mem_out_dec = 6'b001000;
3175 
      12'd1707 :  mem_out_dec = 6'b001001;
3176 
      12'd1708 :  mem_out_dec = 6'b001010;
3177 
      12'd1709 :  mem_out_dec = 6'b001011;
3178 
      12'd1710 :  mem_out_dec = 6'b001100;
3179 
      12'd1711 :  mem_out_dec = 6'b001100;
3180 
      12'd1712 :  mem_out_dec = 6'b001100;
3181 
      12'd1713 :  mem_out_dec = 6'b001101;
3182 
      12'd1714 :  mem_out_dec = 6'b001101;
3183 
      12'd1715 :  mem_out_dec = 6'b001110;
3184 
      12'd1716 :  mem_out_dec = 6'b001110;
3185 
      12'd1717 :  mem_out_dec = 6'b001111;
3186 
      12'd1718 :  mem_out_dec = 6'b001111;
3187 
      12'd1719 :  mem_out_dec = 6'b010000;
3188 
      12'd1720 :  mem_out_dec = 6'b010000;
3189 
      12'd1721 :  mem_out_dec = 6'b010000;
3190 
      12'd1722 :  mem_out_dec = 6'b010001;
3191 
      12'd1723 :  mem_out_dec = 6'b010001;
3192 
      12'd1724 :  mem_out_dec = 6'b010010;
3193 
      12'd1725 :  mem_out_dec = 6'b010010;
3194 
      12'd1726 :  mem_out_dec = 6'b010011;
3195 
      12'd1727 :  mem_out_dec = 6'b010011;
3196 
      12'd1728 :  mem_out_dec = 6'b111111;
3197 
      12'd1729 :  mem_out_dec = 6'b111111;
3198 
      12'd1730 :  mem_out_dec = 6'b111111;
3199 
      12'd1731 :  mem_out_dec = 6'b111111;
3200 
      12'd1732 :  mem_out_dec = 6'b111111;
3201 
      12'd1733 :  mem_out_dec = 6'b111111;
3202 
      12'd1734 :  mem_out_dec = 6'b111111;
3203 
      12'd1735 :  mem_out_dec = 6'b111111;
3204 
      12'd1736 :  mem_out_dec = 6'b111111;
3205 
      12'd1737 :  mem_out_dec = 6'b111111;
3206 
      12'd1738 :  mem_out_dec = 6'b111111;
3207 
      12'd1739 :  mem_out_dec = 6'b111111;
3208 
      12'd1740 :  mem_out_dec = 6'b111111;
3209 
      12'd1741 :  mem_out_dec = 6'b111111;
3210 
      12'd1742 :  mem_out_dec = 6'b111111;
3211 
      12'd1743 :  mem_out_dec = 6'b111111;
3212 
      12'd1744 :  mem_out_dec = 6'b111111;
3213 
      12'd1745 :  mem_out_dec = 6'b111111;
3214 
      12'd1746 :  mem_out_dec = 6'b111111;
3215 
      12'd1747 :  mem_out_dec = 6'b111111;
3216 
      12'd1748 :  mem_out_dec = 6'b111111;
3217 
      12'd1749 :  mem_out_dec = 6'b111111;
3218 
      12'd1750 :  mem_out_dec = 6'b111111;
3219 
      12'd1751 :  mem_out_dec = 6'b111111;
3220 
      12'd1752 :  mem_out_dec = 6'b111111;
3221 
      12'd1753 :  mem_out_dec = 6'b111111;
3222 
      12'd1754 :  mem_out_dec = 6'b111111;
3223 
      12'd1755 :  mem_out_dec = 6'b111111;
3224 
      12'd1756 :  mem_out_dec = 6'b111111;
3225 
      12'd1757 :  mem_out_dec = 6'b111111;
3226 
      12'd1758 :  mem_out_dec = 6'b111111;
3227 
      12'd1759 :  mem_out_dec = 6'b111111;
3228 
      12'd1760 :  mem_out_dec = 6'b111111;
3229 
      12'd1761 :  mem_out_dec = 6'b000011;
3230 
      12'd1762 :  mem_out_dec = 6'b000011;
3231 
      12'd1763 :  mem_out_dec = 6'b000100;
3232 
      12'd1764 :  mem_out_dec = 6'b000101;
3233 
      12'd1765 :  mem_out_dec = 6'b000101;
3234 
      12'd1766 :  mem_out_dec = 6'b000110;
3235 
      12'd1767 :  mem_out_dec = 6'b000111;
3236 
      12'd1768 :  mem_out_dec = 6'b000111;
3237 
      12'd1769 :  mem_out_dec = 6'b000111;
3238 
      12'd1770 :  mem_out_dec = 6'b001000;
3239 
      12'd1771 :  mem_out_dec = 6'b001001;
3240 
      12'd1772 :  mem_out_dec = 6'b001010;
3241 
      12'd1773 :  mem_out_dec = 6'b001011;
3242 
      12'd1774 :  mem_out_dec = 6'b001011;
3243 
      12'd1775 :  mem_out_dec = 6'b001100;
3244 
      12'd1776 :  mem_out_dec = 6'b001100;
3245 
      12'd1777 :  mem_out_dec = 6'b001101;
3246 
      12'd1778 :  mem_out_dec = 6'b001101;
3247 
      12'd1779 :  mem_out_dec = 6'b001101;
3248 
      12'd1780 :  mem_out_dec = 6'b001110;
3249 
      12'd1781 :  mem_out_dec = 6'b001111;
3250 
      12'd1782 :  mem_out_dec = 6'b001111;
3251 
      12'd1783 :  mem_out_dec = 6'b010000;
3252 
      12'd1784 :  mem_out_dec = 6'b010000;
3253 
      12'd1785 :  mem_out_dec = 6'b010000;
3254 
      12'd1786 :  mem_out_dec = 6'b010000;
3255 
      12'd1787 :  mem_out_dec = 6'b010001;
3256 
      12'd1788 :  mem_out_dec = 6'b010001;
3257 
      12'd1789 :  mem_out_dec = 6'b010010;
3258 
      12'd1790 :  mem_out_dec = 6'b010010;
3259 
      12'd1791 :  mem_out_dec = 6'b010011;
3260 
      12'd1792 :  mem_out_dec = 6'b111111;
3261 
      12'd1793 :  mem_out_dec = 6'b111111;
3262 
      12'd1794 :  mem_out_dec = 6'b111111;
3263 
      12'd1795 :  mem_out_dec = 6'b111111;
3264 
      12'd1796 :  mem_out_dec = 6'b111111;
3265 
      12'd1797 :  mem_out_dec = 6'b111111;
3266 
      12'd1798 :  mem_out_dec = 6'b111111;
3267 
      12'd1799 :  mem_out_dec = 6'b111111;
3268 
      12'd1800 :  mem_out_dec = 6'b111111;
3269 
      12'd1801 :  mem_out_dec = 6'b111111;
3270 
      12'd1802 :  mem_out_dec = 6'b111111;
3271 
      12'd1803 :  mem_out_dec = 6'b111111;
3272 
      12'd1804 :  mem_out_dec = 6'b111111;
3273 
      12'd1805 :  mem_out_dec = 6'b111111;
3274 
      12'd1806 :  mem_out_dec = 6'b111111;
3275 
      12'd1807 :  mem_out_dec = 6'b111111;
3276 
      12'd1808 :  mem_out_dec = 6'b111111;
3277 
      12'd1809 :  mem_out_dec = 6'b111111;
3278 
      12'd1810 :  mem_out_dec = 6'b111111;
3279 
      12'd1811 :  mem_out_dec = 6'b111111;
3280 
      12'd1812 :  mem_out_dec = 6'b111111;
3281 
      12'd1813 :  mem_out_dec = 6'b111111;
3282 
      12'd1814 :  mem_out_dec = 6'b111111;
3283 
      12'd1815 :  mem_out_dec = 6'b111111;
3284 
      12'd1816 :  mem_out_dec = 6'b111111;
3285 
      12'd1817 :  mem_out_dec = 6'b111111;
3286 
      12'd1818 :  mem_out_dec = 6'b111111;
3287 
      12'd1819 :  mem_out_dec = 6'b111111;
3288 
      12'd1820 :  mem_out_dec = 6'b111111;
3289 
      12'd1821 :  mem_out_dec = 6'b111111;
3290 
      12'd1822 :  mem_out_dec = 6'b111111;
3291 
      12'd1823 :  mem_out_dec = 6'b111111;
3292 
      12'd1824 :  mem_out_dec = 6'b111111;
3293 
      12'd1825 :  mem_out_dec = 6'b111111;
3294 
      12'd1826 :  mem_out_dec = 6'b000011;
3295 
      12'd1827 :  mem_out_dec = 6'b000100;
3296 
      12'd1828 :  mem_out_dec = 6'b000100;
3297 
      12'd1829 :  mem_out_dec = 6'b000101;
3298 
      12'd1830 :  mem_out_dec = 6'b000110;
3299 
      12'd1831 :  mem_out_dec = 6'b000110;
3300 
      12'd1832 :  mem_out_dec = 6'b000110;
3301 
      12'd1833 :  mem_out_dec = 6'b000111;
3302 
      12'd1834 :  mem_out_dec = 6'b001000;
3303 
      12'd1835 :  mem_out_dec = 6'b001001;
3304 
      12'd1836 :  mem_out_dec = 6'b001010;
3305 
      12'd1837 :  mem_out_dec = 6'b001010;
3306 
      12'd1838 :  mem_out_dec = 6'b001011;
3307 
      12'd1839 :  mem_out_dec = 6'b001100;
3308 
      12'd1840 :  mem_out_dec = 6'b001100;
3309 
      12'd1841 :  mem_out_dec = 6'b001100;
3310 
      12'd1842 :  mem_out_dec = 6'b001101;
3311 
      12'd1843 :  mem_out_dec = 6'b001101;
3312 
      12'd1844 :  mem_out_dec = 6'b001110;
3313 
      12'd1845 :  mem_out_dec = 6'b001110;
3314 
      12'd1846 :  mem_out_dec = 6'b001111;
3315 
      12'd1847 :  mem_out_dec = 6'b010000;
3316 
      12'd1848 :  mem_out_dec = 6'b001111;
3317 
      12'd1849 :  mem_out_dec = 6'b001111;
3318 
      12'd1850 :  mem_out_dec = 6'b010000;
3319 
      12'd1851 :  mem_out_dec = 6'b010000;
3320 
      12'd1852 :  mem_out_dec = 6'b010001;
3321 
      12'd1853 :  mem_out_dec = 6'b010001;
3322 
      12'd1854 :  mem_out_dec = 6'b010010;
3323 
      12'd1855 :  mem_out_dec = 6'b010010;
3324 
      12'd1856 :  mem_out_dec = 6'b111111;
3325 
      12'd1857 :  mem_out_dec = 6'b111111;
3326 
      12'd1858 :  mem_out_dec = 6'b111111;
3327 
      12'd1859 :  mem_out_dec = 6'b111111;
3328 
      12'd1860 :  mem_out_dec = 6'b111111;
3329 
      12'd1861 :  mem_out_dec = 6'b111111;
3330 
      12'd1862 :  mem_out_dec = 6'b111111;
3331 
      12'd1863 :  mem_out_dec = 6'b111111;
3332 
      12'd1864 :  mem_out_dec = 6'b111111;
3333 
      12'd1865 :  mem_out_dec = 6'b111111;
3334 
      12'd1866 :  mem_out_dec = 6'b111111;
3335 
      12'd1867 :  mem_out_dec = 6'b111111;
3336 
      12'd1868 :  mem_out_dec = 6'b111111;
3337 
      12'd1869 :  mem_out_dec = 6'b111111;
3338 
      12'd1870 :  mem_out_dec = 6'b111111;
3339 
      12'd1871 :  mem_out_dec = 6'b111111;
3340 
      12'd1872 :  mem_out_dec = 6'b111111;
3341 
      12'd1873 :  mem_out_dec = 6'b111111;
3342 
      12'd1874 :  mem_out_dec = 6'b111111;
3343 
      12'd1875 :  mem_out_dec = 6'b111111;
3344 
      12'd1876 :  mem_out_dec = 6'b111111;
3345 
      12'd1877 :  mem_out_dec = 6'b111111;
3346 
      12'd1878 :  mem_out_dec = 6'b111111;
3347 
      12'd1879 :  mem_out_dec = 6'b111111;
3348 
      12'd1880 :  mem_out_dec = 6'b111111;
3349 
      12'd1881 :  mem_out_dec = 6'b111111;
3350 
      12'd1882 :  mem_out_dec = 6'b111111;
3351 
      12'd1883 :  mem_out_dec = 6'b111111;
3352 
      12'd1884 :  mem_out_dec = 6'b111111;
3353 
      12'd1885 :  mem_out_dec = 6'b111111;
3354 
      12'd1886 :  mem_out_dec = 6'b111111;
3355 
      12'd1887 :  mem_out_dec = 6'b111111;
3356 
      12'd1888 :  mem_out_dec = 6'b111111;
3357 
      12'd1889 :  mem_out_dec = 6'b111111;
3358 
      12'd1890 :  mem_out_dec = 6'b111111;
3359 
      12'd1891 :  mem_out_dec = 6'b000100;
3360 
      12'd1892 :  mem_out_dec = 6'b000100;
3361 
      12'd1893 :  mem_out_dec = 6'b000101;
3362 
      12'd1894 :  mem_out_dec = 6'b000101;
3363 
      12'd1895 :  mem_out_dec = 6'b000110;
3364 
      12'd1896 :  mem_out_dec = 6'b000110;
3365 
      12'd1897 :  mem_out_dec = 6'b000111;
3366 
      12'd1898 :  mem_out_dec = 6'b001000;
3367 
      12'd1899 :  mem_out_dec = 6'b001001;
3368 
      12'd1900 :  mem_out_dec = 6'b001001;
3369 
      12'd1901 :  mem_out_dec = 6'b001010;
3370 
      12'd1902 :  mem_out_dec = 6'b001011;
3371 
      12'd1903 :  mem_out_dec = 6'b001100;
3372 
      12'd1904 :  mem_out_dec = 6'b001100;
3373 
      12'd1905 :  mem_out_dec = 6'b001100;
3374 
      12'd1906 :  mem_out_dec = 6'b001100;
3375 
      12'd1907 :  mem_out_dec = 6'b001101;
3376 
      12'd1908 :  mem_out_dec = 6'b001110;
3377 
      12'd1909 :  mem_out_dec = 6'b001110;
3378 
      12'd1910 :  mem_out_dec = 6'b001111;
3379 
      12'd1911 :  mem_out_dec = 6'b001111;
3380 
      12'd1912 :  mem_out_dec = 6'b001111;
3381 
      12'd1913 :  mem_out_dec = 6'b001111;
3382 
      12'd1914 :  mem_out_dec = 6'b001111;
3383 
      12'd1915 :  mem_out_dec = 6'b010000;
3384 
      12'd1916 :  mem_out_dec = 6'b010000;
3385 
      12'd1917 :  mem_out_dec = 6'b010001;
3386 
      12'd1918 :  mem_out_dec = 6'b010001;
3387 
      12'd1919 :  mem_out_dec = 6'b010010;
3388 
      12'd1920 :  mem_out_dec = 6'b111111;
3389 
      12'd1921 :  mem_out_dec = 6'b111111;
3390 
      12'd1922 :  mem_out_dec = 6'b111111;
3391 
      12'd1923 :  mem_out_dec = 6'b111111;
3392 
      12'd1924 :  mem_out_dec = 6'b111111;
3393 
      12'd1925 :  mem_out_dec = 6'b111111;
3394 
      12'd1926 :  mem_out_dec = 6'b111111;
3395 
      12'd1927 :  mem_out_dec = 6'b111111;
3396 
      12'd1928 :  mem_out_dec = 6'b111111;
3397 
      12'd1929 :  mem_out_dec = 6'b111111;
3398 
      12'd1930 :  mem_out_dec = 6'b111111;
3399 
      12'd1931 :  mem_out_dec = 6'b111111;
3400 
      12'd1932 :  mem_out_dec = 6'b111111;
3401 
      12'd1933 :  mem_out_dec = 6'b111111;
3402 
      12'd1934 :  mem_out_dec = 6'b111111;
3403 
      12'd1935 :  mem_out_dec = 6'b111111;
3404 
      12'd1936 :  mem_out_dec = 6'b111111;
3405 
      12'd1937 :  mem_out_dec = 6'b111111;
3406 
      12'd1938 :  mem_out_dec = 6'b111111;
3407 
      12'd1939 :  mem_out_dec = 6'b111111;
3408 
      12'd1940 :  mem_out_dec = 6'b111111;
3409 
      12'd1941 :  mem_out_dec = 6'b111111;
3410 
      12'd1942 :  mem_out_dec = 6'b111111;
3411 
      12'd1943 :  mem_out_dec = 6'b111111;
3412 
      12'd1944 :  mem_out_dec = 6'b111111;
3413 
      12'd1945 :  mem_out_dec = 6'b111111;
3414 
      12'd1946 :  mem_out_dec = 6'b111111;
3415 
      12'd1947 :  mem_out_dec = 6'b111111;
3416 
      12'd1948 :  mem_out_dec = 6'b111111;
3417 
      12'd1949 :  mem_out_dec = 6'b111111;
3418 
      12'd1950 :  mem_out_dec = 6'b111111;
3419 
      12'd1951 :  mem_out_dec = 6'b111111;
3420 
      12'd1952 :  mem_out_dec = 6'b111111;
3421 
      12'd1953 :  mem_out_dec = 6'b111111;
3422 
      12'd1954 :  mem_out_dec = 6'b111111;
3423 
      12'd1955 :  mem_out_dec = 6'b111111;
3424 
      12'd1956 :  mem_out_dec = 6'b000100;
3425 
      12'd1957 :  mem_out_dec = 6'b000101;
3426 
      12'd1958 :  mem_out_dec = 6'b000101;
3427 
      12'd1959 :  mem_out_dec = 6'b000110;
3428 
      12'd1960 :  mem_out_dec = 6'b000110;
3429 
      12'd1961 :  mem_out_dec = 6'b000111;
3430 
      12'd1962 :  mem_out_dec = 6'b001000;
3431 
      12'd1963 :  mem_out_dec = 6'b001000;
3432 
      12'd1964 :  mem_out_dec = 6'b001001;
3433 
      12'd1965 :  mem_out_dec = 6'b001010;
3434 
      12'd1966 :  mem_out_dec = 6'b001011;
3435 
      12'd1967 :  mem_out_dec = 6'b001011;
3436 
      12'd1968 :  mem_out_dec = 6'b001011;
3437 
      12'd1969 :  mem_out_dec = 6'b001100;
3438 
      12'd1970 :  mem_out_dec = 6'b001100;
3439 
      12'd1971 :  mem_out_dec = 6'b001101;
3440 
      12'd1972 :  mem_out_dec = 6'b001101;
3441 
      12'd1973 :  mem_out_dec = 6'b001110;
3442 
      12'd1974 :  mem_out_dec = 6'b001111;
3443 
      12'd1975 :  mem_out_dec = 6'b001111;
3444 
      12'd1976 :  mem_out_dec = 6'b001110;
3445 
      12'd1977 :  mem_out_dec = 6'b001110;
3446 
      12'd1978 :  mem_out_dec = 6'b001111;
3447 
      12'd1979 :  mem_out_dec = 6'b001111;
3448 
      12'd1980 :  mem_out_dec = 6'b010000;
3449 
      12'd1981 :  mem_out_dec = 6'b010000;
3450 
      12'd1982 :  mem_out_dec = 6'b010001;
3451 
      12'd1983 :  mem_out_dec = 6'b010001;
3452 
      12'd1984 :  mem_out_dec = 6'b111111;
3453 
      12'd1985 :  mem_out_dec = 6'b111111;
3454 
      12'd1986 :  mem_out_dec = 6'b111111;
3455 
      12'd1987 :  mem_out_dec = 6'b111111;
3456 
      12'd1988 :  mem_out_dec = 6'b111111;
3457 
      12'd1989 :  mem_out_dec = 6'b111111;
3458 
      12'd1990 :  mem_out_dec = 6'b111111;
3459 
      12'd1991 :  mem_out_dec = 6'b111111;
3460 
      12'd1992 :  mem_out_dec = 6'b111111;
3461 
      12'd1993 :  mem_out_dec = 6'b111111;
3462 
      12'd1994 :  mem_out_dec = 6'b111111;
3463 
      12'd1995 :  mem_out_dec = 6'b111111;
3464 
      12'd1996 :  mem_out_dec = 6'b111111;
3465 
      12'd1997 :  mem_out_dec = 6'b111111;
3466 
      12'd1998 :  mem_out_dec = 6'b111111;
3467 
      12'd1999 :  mem_out_dec = 6'b111111;
3468 
      12'd2000 :  mem_out_dec = 6'b111111;
3469 
      12'd2001 :  mem_out_dec = 6'b111111;
3470 
      12'd2002 :  mem_out_dec = 6'b111111;
3471 
      12'd2003 :  mem_out_dec = 6'b111111;
3472 
      12'd2004 :  mem_out_dec = 6'b111111;
3473 
      12'd2005 :  mem_out_dec = 6'b111111;
3474 
      12'd2006 :  mem_out_dec = 6'b111111;
3475 
      12'd2007 :  mem_out_dec = 6'b111111;
3476 
      12'd2008 :  mem_out_dec = 6'b111111;
3477 
      12'd2009 :  mem_out_dec = 6'b111111;
3478 
      12'd2010 :  mem_out_dec = 6'b111111;
3479 
      12'd2011 :  mem_out_dec = 6'b111111;
3480 
      12'd2012 :  mem_out_dec = 6'b111111;
3481 
      12'd2013 :  mem_out_dec = 6'b111111;
3482 
      12'd2014 :  mem_out_dec = 6'b111111;
3483 
      12'd2015 :  mem_out_dec = 6'b111111;
3484 
      12'd2016 :  mem_out_dec = 6'b111111;
3485 
      12'd2017 :  mem_out_dec = 6'b111111;
3486 
      12'd2018 :  mem_out_dec = 6'b111111;
3487 
      12'd2019 :  mem_out_dec = 6'b111111;
3488 
      12'd2020 :  mem_out_dec = 6'b111111;
3489 
      12'd2021 :  mem_out_dec = 6'b000100;
3490 
      12'd2022 :  mem_out_dec = 6'b000101;
3491 
      12'd2023 :  mem_out_dec = 6'b000110;
3492 
      12'd2024 :  mem_out_dec = 6'b000110;
3493 
      12'd2025 :  mem_out_dec = 6'b000111;
3494 
      12'd2026 :  mem_out_dec = 6'b000111;
3495 
      12'd2027 :  mem_out_dec = 6'b001000;
3496 
      12'd2028 :  mem_out_dec = 6'b001001;
3497 
      12'd2029 :  mem_out_dec = 6'b001010;
3498 
      12'd2030 :  mem_out_dec = 6'b001010;
3499 
      12'd2031 :  mem_out_dec = 6'b001011;
3500 
      12'd2032 :  mem_out_dec = 6'b001011;
3501 
      12'd2033 :  mem_out_dec = 6'b001011;
3502 
      12'd2034 :  mem_out_dec = 6'b001100;
3503 
      12'd2035 :  mem_out_dec = 6'b001101;
3504 
      12'd2036 :  mem_out_dec = 6'b001101;
3505 
      12'd2037 :  mem_out_dec = 6'b001110;
3506 
      12'd2038 :  mem_out_dec = 6'b001110;
3507 
      12'd2039 :  mem_out_dec = 6'b001110;
3508 
      12'd2040 :  mem_out_dec = 6'b001101;
3509 
      12'd2041 :  mem_out_dec = 6'b001110;
3510 
      12'd2042 :  mem_out_dec = 6'b001110;
3511 
      12'd2043 :  mem_out_dec = 6'b001111;
3512 
      12'd2044 :  mem_out_dec = 6'b001111;
3513 
      12'd2045 :  mem_out_dec = 6'b010000;
3514 
      12'd2046 :  mem_out_dec = 6'b010000;
3515 
      12'd2047 :  mem_out_dec = 6'b010001;
3516 
      12'd2048 :  mem_out_dec = 6'b111111;
3517 
      12'd2049 :  mem_out_dec = 6'b111111;
3518 
      12'd2050 :  mem_out_dec = 6'b111111;
3519 
      12'd2051 :  mem_out_dec = 6'b111111;
3520 
      12'd2052 :  mem_out_dec = 6'b111111;
3521 
      12'd2053 :  mem_out_dec = 6'b111111;
3522 
      12'd2054 :  mem_out_dec = 6'b111111;
3523 
      12'd2055 :  mem_out_dec = 6'b111111;
3524 
      12'd2056 :  mem_out_dec = 6'b111111;
3525 
      12'd2057 :  mem_out_dec = 6'b111111;
3526 
      12'd2058 :  mem_out_dec = 6'b111111;
3527 
      12'd2059 :  mem_out_dec = 6'b111111;
3528 
      12'd2060 :  mem_out_dec = 6'b111111;
3529 
      12'd2061 :  mem_out_dec = 6'b111111;
3530 
      12'd2062 :  mem_out_dec = 6'b111111;
3531 
      12'd2063 :  mem_out_dec = 6'b111111;
3532 
      12'd2064 :  mem_out_dec = 6'b111111;
3533 
      12'd2065 :  mem_out_dec = 6'b111111;
3534 
      12'd2066 :  mem_out_dec = 6'b111111;
3535 
      12'd2067 :  mem_out_dec = 6'b111111;
3536 
      12'd2068 :  mem_out_dec = 6'b111111;
3537 
      12'd2069 :  mem_out_dec = 6'b111111;
3538 
      12'd2070 :  mem_out_dec = 6'b111111;
3539 
      12'd2071 :  mem_out_dec = 6'b111111;
3540 
      12'd2072 :  mem_out_dec = 6'b111111;
3541 
      12'd2073 :  mem_out_dec = 6'b111111;
3542 
      12'd2074 :  mem_out_dec = 6'b111111;
3543 
      12'd2075 :  mem_out_dec = 6'b111111;
3544 
      12'd2076 :  mem_out_dec = 6'b111111;
3545 
      12'd2077 :  mem_out_dec = 6'b111111;
3546 
      12'd2078 :  mem_out_dec = 6'b111111;
3547 
      12'd2079 :  mem_out_dec = 6'b111111;
3548 
      12'd2080 :  mem_out_dec = 6'b111111;
3549 
      12'd2081 :  mem_out_dec = 6'b111111;
3550 
      12'd2082 :  mem_out_dec = 6'b111111;
3551 
      12'd2083 :  mem_out_dec = 6'b111111;
3552 
      12'd2084 :  mem_out_dec = 6'b111111;
3553 
      12'd2085 :  mem_out_dec = 6'b111111;
3554 
      12'd2086 :  mem_out_dec = 6'b000100;
3555 
      12'd2087 :  mem_out_dec = 6'b000101;
3556 
      12'd2088 :  mem_out_dec = 6'b000101;
3557 
      12'd2089 :  mem_out_dec = 6'b000110;
3558 
      12'd2090 :  mem_out_dec = 6'b000110;
3559 
      12'd2091 :  mem_out_dec = 6'b000111;
3560 
      12'd2092 :  mem_out_dec = 6'b001000;
3561 
      12'd2093 :  mem_out_dec = 6'b001001;
3562 
      12'd2094 :  mem_out_dec = 6'b001001;
3563 
      12'd2095 :  mem_out_dec = 6'b001010;
3564 
      12'd2096 :  mem_out_dec = 6'b001010;
3565 
      12'd2097 :  mem_out_dec = 6'b001011;
3566 
      12'd2098 :  mem_out_dec = 6'b001011;
3567 
      12'd2099 :  mem_out_dec = 6'b001100;
3568 
      12'd2100 :  mem_out_dec = 6'b001100;
3569 
      12'd2101 :  mem_out_dec = 6'b001100;
3570 
      12'd2102 :  mem_out_dec = 6'b001100;
3571 
      12'd2103 :  mem_out_dec = 6'b001101;
3572 
      12'd2104 :  mem_out_dec = 6'b001100;
3573 
      12'd2105 :  mem_out_dec = 6'b001100;
3574 
      12'd2106 :  mem_out_dec = 6'b001101;
3575 
      12'd2107 :  mem_out_dec = 6'b001101;
3576 
      12'd2108 :  mem_out_dec = 6'b001110;
3577 
      12'd2109 :  mem_out_dec = 6'b001111;
3578 
      12'd2110 :  mem_out_dec = 6'b010000;
3579 
      12'd2111 :  mem_out_dec = 6'b010000;
3580 
      12'd2112 :  mem_out_dec = 6'b111111;
3581 
      12'd2113 :  mem_out_dec = 6'b111111;
3582 
      12'd2114 :  mem_out_dec = 6'b111111;
3583 
      12'd2115 :  mem_out_dec = 6'b111111;
3584 
      12'd2116 :  mem_out_dec = 6'b111111;
3585 
      12'd2117 :  mem_out_dec = 6'b111111;
3586 
      12'd2118 :  mem_out_dec = 6'b111111;
3587 
      12'd2119 :  mem_out_dec = 6'b111111;
3588 
      12'd2120 :  mem_out_dec = 6'b111111;
3589 
      12'd2121 :  mem_out_dec = 6'b111111;
3590 
      12'd2122 :  mem_out_dec = 6'b111111;
3591 
      12'd2123 :  mem_out_dec = 6'b111111;
3592 
      12'd2124 :  mem_out_dec = 6'b111111;
3593 
      12'd2125 :  mem_out_dec = 6'b111111;
3594 
      12'd2126 :  mem_out_dec = 6'b111111;
3595 
      12'd2127 :  mem_out_dec = 6'b111111;
3596 
      12'd2128 :  mem_out_dec = 6'b111111;
3597 
      12'd2129 :  mem_out_dec = 6'b111111;
3598 
      12'd2130 :  mem_out_dec = 6'b111111;
3599 
      12'd2131 :  mem_out_dec = 6'b111111;
3600 
      12'd2132 :  mem_out_dec = 6'b111111;
3601 
      12'd2133 :  mem_out_dec = 6'b111111;
3602 
      12'd2134 :  mem_out_dec = 6'b111111;
3603 
      12'd2135 :  mem_out_dec = 6'b111111;
3604 
      12'd2136 :  mem_out_dec = 6'b111111;
3605 
      12'd2137 :  mem_out_dec = 6'b111111;
3606 
      12'd2138 :  mem_out_dec = 6'b111111;
3607 
      12'd2139 :  mem_out_dec = 6'b111111;
3608 
      12'd2140 :  mem_out_dec = 6'b111111;
3609 
      12'd2141 :  mem_out_dec = 6'b111111;
3610 
      12'd2142 :  mem_out_dec = 6'b111111;
3611 
      12'd2143 :  mem_out_dec = 6'b111111;
3612 
      12'd2144 :  mem_out_dec = 6'b111111;
3613 
      12'd2145 :  mem_out_dec = 6'b111111;
3614 
      12'd2146 :  mem_out_dec = 6'b111111;
3615 
      12'd2147 :  mem_out_dec = 6'b111111;
3616 
      12'd2148 :  mem_out_dec = 6'b111111;
3617 
      12'd2149 :  mem_out_dec = 6'b111111;
3618 
      12'd2150 :  mem_out_dec = 6'b111111;
3619 
      12'd2151 :  mem_out_dec = 6'b000100;
3620 
      12'd2152 :  mem_out_dec = 6'b000100;
3621 
      12'd2153 :  mem_out_dec = 6'b000101;
3622 
      12'd2154 :  mem_out_dec = 6'b000110;
3623 
      12'd2155 :  mem_out_dec = 6'b000111;
3624 
      12'd2156 :  mem_out_dec = 6'b000111;
3625 
      12'd2157 :  mem_out_dec = 6'b001000;
3626 
      12'd2158 :  mem_out_dec = 6'b001001;
3627 
      12'd2159 :  mem_out_dec = 6'b001001;
3628 
      12'd2160 :  mem_out_dec = 6'b001010;
3629 
      12'd2161 :  mem_out_dec = 6'b001010;
3630 
      12'd2162 :  mem_out_dec = 6'b001011;
3631 
      12'd2163 :  mem_out_dec = 6'b001011;
3632 
      12'd2164 :  mem_out_dec = 6'b001011;
3633 
      12'd2165 :  mem_out_dec = 6'b001011;
3634 
      12'd2166 :  mem_out_dec = 6'b001011;
3635 
      12'd2167 :  mem_out_dec = 6'b001100;
3636 
      12'd2168 :  mem_out_dec = 6'b001011;
3637 
      12'd2169 :  mem_out_dec = 6'b001011;
3638 
      12'd2170 :  mem_out_dec = 6'b001100;
3639 
      12'd2171 :  mem_out_dec = 6'b001101;
3640 
      12'd2172 :  mem_out_dec = 6'b001110;
3641 
      12'd2173 :  mem_out_dec = 6'b001110;
3642 
      12'd2174 :  mem_out_dec = 6'b001111;
3643 
      12'd2175 :  mem_out_dec = 6'b010000;
3644 
      12'd2176 :  mem_out_dec = 6'b111111;
3645 
      12'd2177 :  mem_out_dec = 6'b111111;
3646 
      12'd2178 :  mem_out_dec = 6'b111111;
3647 
      12'd2179 :  mem_out_dec = 6'b111111;
3648 
      12'd2180 :  mem_out_dec = 6'b111111;
3649 
      12'd2181 :  mem_out_dec = 6'b111111;
3650 
      12'd2182 :  mem_out_dec = 6'b111111;
3651 
      12'd2183 :  mem_out_dec = 6'b111111;
3652 
      12'd2184 :  mem_out_dec = 6'b111111;
3653 
      12'd2185 :  mem_out_dec = 6'b111111;
3654 
      12'd2186 :  mem_out_dec = 6'b111111;
3655 
      12'd2187 :  mem_out_dec = 6'b111111;
3656 
      12'd2188 :  mem_out_dec = 6'b111111;
3657 
      12'd2189 :  mem_out_dec = 6'b111111;
3658 
      12'd2190 :  mem_out_dec = 6'b111111;
3659 
      12'd2191 :  mem_out_dec = 6'b111111;
3660 
      12'd2192 :  mem_out_dec = 6'b111111;
3661 
      12'd2193 :  mem_out_dec = 6'b111111;
3662 
      12'd2194 :  mem_out_dec = 6'b111111;
3663 
      12'd2195 :  mem_out_dec = 6'b111111;
3664 
      12'd2196 :  mem_out_dec = 6'b111111;
3665 
      12'd2197 :  mem_out_dec = 6'b111111;
3666 
      12'd2198 :  mem_out_dec = 6'b111111;
3667 
      12'd2199 :  mem_out_dec = 6'b111111;
3668 
      12'd2200 :  mem_out_dec = 6'b111111;
3669 
      12'd2201 :  mem_out_dec = 6'b111111;
3670 
      12'd2202 :  mem_out_dec = 6'b111111;
3671 
      12'd2203 :  mem_out_dec = 6'b111111;
3672 
      12'd2204 :  mem_out_dec = 6'b111111;
3673 
      12'd2205 :  mem_out_dec = 6'b111111;
3674 
      12'd2206 :  mem_out_dec = 6'b111111;
3675 
      12'd2207 :  mem_out_dec = 6'b111111;
3676 
      12'd2208 :  mem_out_dec = 6'b111111;
3677 
      12'd2209 :  mem_out_dec = 6'b111111;
3678 
      12'd2210 :  mem_out_dec = 6'b111111;
3679 
      12'd2211 :  mem_out_dec = 6'b111111;
3680 
      12'd2212 :  mem_out_dec = 6'b111111;
3681 
      12'd2213 :  mem_out_dec = 6'b111111;
3682 
      12'd2214 :  mem_out_dec = 6'b111111;
3683 
      12'd2215 :  mem_out_dec = 6'b111111;
3684 
      12'd2216 :  mem_out_dec = 6'b000100;
3685 
      12'd2217 :  mem_out_dec = 6'b000101;
3686 
      12'd2218 :  mem_out_dec = 6'b000101;
3687 
      12'd2219 :  mem_out_dec = 6'b000110;
3688 
      12'd2220 :  mem_out_dec = 6'b000111;
3689 
      12'd2221 :  mem_out_dec = 6'b000111;
3690 
      12'd2222 :  mem_out_dec = 6'b001000;
3691 
      12'd2223 :  mem_out_dec = 6'b001001;
3692 
      12'd2224 :  mem_out_dec = 6'b001001;
3693 
      12'd2225 :  mem_out_dec = 6'b001010;
3694 
      12'd2226 :  mem_out_dec = 6'b001010;
3695 
      12'd2227 :  mem_out_dec = 6'b001010;
3696 
      12'd2228 :  mem_out_dec = 6'b001010;
3697 
      12'd2229 :  mem_out_dec = 6'b001010;
3698 
      12'd2230 :  mem_out_dec = 6'b001010;
3699 
      12'd2231 :  mem_out_dec = 6'b001010;
3700 
      12'd2232 :  mem_out_dec = 6'b001010;
3701 
      12'd2233 :  mem_out_dec = 6'b001011;
3702 
      12'd2234 :  mem_out_dec = 6'b001100;
3703 
      12'd2235 :  mem_out_dec = 6'b001100;
3704 
      12'd2236 :  mem_out_dec = 6'b001101;
3705 
      12'd2237 :  mem_out_dec = 6'b001110;
3706 
      12'd2238 :  mem_out_dec = 6'b001111;
3707 
      12'd2239 :  mem_out_dec = 6'b010000;
3708 
      12'd2240 :  mem_out_dec = 6'b111111;
3709 
      12'd2241 :  mem_out_dec = 6'b111111;
3710 
      12'd2242 :  mem_out_dec = 6'b111111;
3711 
      12'd2243 :  mem_out_dec = 6'b111111;
3712 
      12'd2244 :  mem_out_dec = 6'b111111;
3713 
      12'd2245 :  mem_out_dec = 6'b111111;
3714 
      12'd2246 :  mem_out_dec = 6'b111111;
3715 
      12'd2247 :  mem_out_dec = 6'b111111;
3716 
      12'd2248 :  mem_out_dec = 6'b111111;
3717 
      12'd2249 :  mem_out_dec = 6'b111111;
3718 
      12'd2250 :  mem_out_dec = 6'b111111;
3719 
      12'd2251 :  mem_out_dec = 6'b111111;
3720 
      12'd2252 :  mem_out_dec = 6'b111111;
3721 
      12'd2253 :  mem_out_dec = 6'b111111;
3722 
      12'd2254 :  mem_out_dec = 6'b111111;
3723 
      12'd2255 :  mem_out_dec = 6'b111111;
3724 
      12'd2256 :  mem_out_dec = 6'b111111;
3725 
      12'd2257 :  mem_out_dec = 6'b111111;
3726 
      12'd2258 :  mem_out_dec = 6'b111111;
3727 
      12'd2259 :  mem_out_dec = 6'b111111;
3728 
      12'd2260 :  mem_out_dec = 6'b111111;
3729 
      12'd2261 :  mem_out_dec = 6'b111111;
3730 
      12'd2262 :  mem_out_dec = 6'b111111;
3731 
      12'd2263 :  mem_out_dec = 6'b111111;
3732 
      12'd2264 :  mem_out_dec = 6'b111111;
3733 
      12'd2265 :  mem_out_dec = 6'b111111;
3734 
      12'd2266 :  mem_out_dec = 6'b111111;
3735 
      12'd2267 :  mem_out_dec = 6'b111111;
3736 
      12'd2268 :  mem_out_dec = 6'b111111;
3737 
      12'd2269 :  mem_out_dec = 6'b111111;
3738 
      12'd2270 :  mem_out_dec = 6'b111111;
3739 
      12'd2271 :  mem_out_dec = 6'b111111;
3740 
      12'd2272 :  mem_out_dec = 6'b111111;
3741 
      12'd2273 :  mem_out_dec = 6'b111111;
3742 
      12'd2274 :  mem_out_dec = 6'b111111;
3743 
      12'd2275 :  mem_out_dec = 6'b111111;
3744 
      12'd2276 :  mem_out_dec = 6'b111111;
3745 
      12'd2277 :  mem_out_dec = 6'b111111;
3746 
      12'd2278 :  mem_out_dec = 6'b111111;
3747 
      12'd2279 :  mem_out_dec = 6'b111111;
3748 
      12'd2280 :  mem_out_dec = 6'b111111;
3749 
      12'd2281 :  mem_out_dec = 6'b000100;
3750 
      12'd2282 :  mem_out_dec = 6'b000101;
3751 
      12'd2283 :  mem_out_dec = 6'b000101;
3752 
      12'd2284 :  mem_out_dec = 6'b000110;
3753 
      12'd2285 :  mem_out_dec = 6'b000111;
3754 
      12'd2286 :  mem_out_dec = 6'b001000;
3755 
      12'd2287 :  mem_out_dec = 6'b001001;
3756 
      12'd2288 :  mem_out_dec = 6'b001001;
3757 
      12'd2289 :  mem_out_dec = 6'b001001;
3758 
      12'd2290 :  mem_out_dec = 6'b001001;
3759 
      12'd2291 :  mem_out_dec = 6'b001001;
3760 
      12'd2292 :  mem_out_dec = 6'b001001;
3761 
      12'd2293 :  mem_out_dec = 6'b001001;
3762 
      12'd2294 :  mem_out_dec = 6'b001001;
3763 
      12'd2295 :  mem_out_dec = 6'b001001;
3764 
      12'd2296 :  mem_out_dec = 6'b001010;
3765 
      12'd2297 :  mem_out_dec = 6'b001010;
3766 
      12'd2298 :  mem_out_dec = 6'b001011;
3767 
      12'd2299 :  mem_out_dec = 6'b001100;
3768 
      12'd2300 :  mem_out_dec = 6'b001101;
3769 
      12'd2301 :  mem_out_dec = 6'b001110;
3770 
      12'd2302 :  mem_out_dec = 6'b001110;
3771 
      12'd2303 :  mem_out_dec = 6'b001111;
3772 
      12'd2304 :  mem_out_dec = 6'b111111;
3773 
      12'd2305 :  mem_out_dec = 6'b111111;
3774 
      12'd2306 :  mem_out_dec = 6'b111111;
3775 
      12'd2307 :  mem_out_dec = 6'b111111;
3776 
      12'd2308 :  mem_out_dec = 6'b111111;
3777 
      12'd2309 :  mem_out_dec = 6'b111111;
3778 
      12'd2310 :  mem_out_dec = 6'b111111;
3779 
      12'd2311 :  mem_out_dec = 6'b111111;
3780 
      12'd2312 :  mem_out_dec = 6'b111111;
3781 
      12'd2313 :  mem_out_dec = 6'b111111;
3782 
      12'd2314 :  mem_out_dec = 6'b111111;
3783 
      12'd2315 :  mem_out_dec = 6'b111111;
3784 
      12'd2316 :  mem_out_dec = 6'b111111;
3785 
      12'd2317 :  mem_out_dec = 6'b111111;
3786 
      12'd2318 :  mem_out_dec = 6'b111111;
3787 
      12'd2319 :  mem_out_dec = 6'b111111;
3788 
      12'd2320 :  mem_out_dec = 6'b111111;
3789 
      12'd2321 :  mem_out_dec = 6'b111111;
3790 
      12'd2322 :  mem_out_dec = 6'b111111;
3791 
      12'd2323 :  mem_out_dec = 6'b111111;
3792 
      12'd2324 :  mem_out_dec = 6'b111111;
3793 
      12'd2325 :  mem_out_dec = 6'b111111;
3794 
      12'd2326 :  mem_out_dec = 6'b111111;
3795 
      12'd2327 :  mem_out_dec = 6'b111111;
3796 
      12'd2328 :  mem_out_dec = 6'b111111;
3797 
      12'd2329 :  mem_out_dec = 6'b111111;
3798 
      12'd2330 :  mem_out_dec = 6'b111111;
3799 
      12'd2331 :  mem_out_dec = 6'b111111;
3800 
      12'd2332 :  mem_out_dec = 6'b111111;
3801 
      12'd2333 :  mem_out_dec = 6'b111111;
3802 
      12'd2334 :  mem_out_dec = 6'b111111;
3803 
      12'd2335 :  mem_out_dec = 6'b111111;
3804 
      12'd2336 :  mem_out_dec = 6'b111111;
3805 
      12'd2337 :  mem_out_dec = 6'b111111;
3806 
      12'd2338 :  mem_out_dec = 6'b111111;
3807 
      12'd2339 :  mem_out_dec = 6'b111111;
3808 
      12'd2340 :  mem_out_dec = 6'b111111;
3809 
      12'd2341 :  mem_out_dec = 6'b111111;
3810 
      12'd2342 :  mem_out_dec = 6'b111111;
3811 
      12'd2343 :  mem_out_dec = 6'b111111;
3812 
      12'd2344 :  mem_out_dec = 6'b111111;
3813 
      12'd2345 :  mem_out_dec = 6'b111111;
3814 
      12'd2346 :  mem_out_dec = 6'b000100;
3815 
      12'd2347 :  mem_out_dec = 6'b000101;
3816 
      12'd2348 :  mem_out_dec = 6'b000110;
3817 
      12'd2349 :  mem_out_dec = 6'b000111;
3818 
      12'd2350 :  mem_out_dec = 6'b000111;
3819 
      12'd2351 :  mem_out_dec = 6'b001000;
3820 
      12'd2352 :  mem_out_dec = 6'b001000;
3821 
      12'd2353 :  mem_out_dec = 6'b001000;
3822 
      12'd2354 :  mem_out_dec = 6'b001000;
3823 
      12'd2355 :  mem_out_dec = 6'b001000;
3824 
      12'd2356 :  mem_out_dec = 6'b001000;
3825 
      12'd2357 :  mem_out_dec = 6'b001000;
3826 
      12'd2358 :  mem_out_dec = 6'b001000;
3827 
      12'd2359 :  mem_out_dec = 6'b001001;
3828 
      12'd2360 :  mem_out_dec = 6'b001001;
3829 
      12'd2361 :  mem_out_dec = 6'b001010;
3830 
      12'd2362 :  mem_out_dec = 6'b001011;
3831 
      12'd2363 :  mem_out_dec = 6'b001100;
3832 
      12'd2364 :  mem_out_dec = 6'b001100;
3833 
      12'd2365 :  mem_out_dec = 6'b001101;
3834 
      12'd2366 :  mem_out_dec = 6'b001110;
3835 
      12'd2367 :  mem_out_dec = 6'b001111;
3836 
      12'd2368 :  mem_out_dec = 6'b111111;
3837 
      12'd2369 :  mem_out_dec = 6'b111111;
3838 
      12'd2370 :  mem_out_dec = 6'b111111;
3839 
      12'd2371 :  mem_out_dec = 6'b111111;
3840 
      12'd2372 :  mem_out_dec = 6'b111111;
3841 
      12'd2373 :  mem_out_dec = 6'b111111;
3842 
      12'd2374 :  mem_out_dec = 6'b111111;
3843 
      12'd2375 :  mem_out_dec = 6'b111111;
3844 
      12'd2376 :  mem_out_dec = 6'b111111;
3845 
      12'd2377 :  mem_out_dec = 6'b111111;
3846 
      12'd2378 :  mem_out_dec = 6'b111111;
3847 
      12'd2379 :  mem_out_dec = 6'b111111;
3848 
      12'd2380 :  mem_out_dec = 6'b111111;
3849 
      12'd2381 :  mem_out_dec = 6'b111111;
3850 
      12'd2382 :  mem_out_dec = 6'b111111;
3851 
      12'd2383 :  mem_out_dec = 6'b111111;
3852 
      12'd2384 :  mem_out_dec = 6'b111111;
3853 
      12'd2385 :  mem_out_dec = 6'b111111;
3854 
      12'd2386 :  mem_out_dec = 6'b111111;
3855 
      12'd2387 :  mem_out_dec = 6'b111111;
3856 
      12'd2388 :  mem_out_dec = 6'b111111;
3857 
      12'd2389 :  mem_out_dec = 6'b111111;
3858 
      12'd2390 :  mem_out_dec = 6'b111111;
3859 
      12'd2391 :  mem_out_dec = 6'b111111;
3860 
      12'd2392 :  mem_out_dec = 6'b111111;
3861 
      12'd2393 :  mem_out_dec = 6'b111111;
3862 
      12'd2394 :  mem_out_dec = 6'b111111;
3863 
      12'd2395 :  mem_out_dec = 6'b111111;
3864 
      12'd2396 :  mem_out_dec = 6'b111111;
3865 
      12'd2397 :  mem_out_dec = 6'b111111;
3866 
      12'd2398 :  mem_out_dec = 6'b111111;
3867 
      12'd2399 :  mem_out_dec = 6'b111111;
3868 
      12'd2400 :  mem_out_dec = 6'b111111;
3869 
      12'd2401 :  mem_out_dec = 6'b111111;
3870 
      12'd2402 :  mem_out_dec = 6'b111111;
3871 
      12'd2403 :  mem_out_dec = 6'b111111;
3872 
      12'd2404 :  mem_out_dec = 6'b111111;
3873 
      12'd2405 :  mem_out_dec = 6'b111111;
3874 
      12'd2406 :  mem_out_dec = 6'b111111;
3875 
      12'd2407 :  mem_out_dec = 6'b111111;
3876 
      12'd2408 :  mem_out_dec = 6'b111111;
3877 
      12'd2409 :  mem_out_dec = 6'b111111;
3878 
      12'd2410 :  mem_out_dec = 6'b111111;
3879 
      12'd2411 :  mem_out_dec = 6'b000101;
3880 
      12'd2412 :  mem_out_dec = 6'b000101;
3881 
      12'd2413 :  mem_out_dec = 6'b000110;
3882 
      12'd2414 :  mem_out_dec = 6'b000111;
3883 
      12'd2415 :  mem_out_dec = 6'b001000;
3884 
      12'd2416 :  mem_out_dec = 6'b000111;
3885 
      12'd2417 :  mem_out_dec = 6'b000111;
3886 
      12'd2418 :  mem_out_dec = 6'b000111;
3887 
      12'd2419 :  mem_out_dec = 6'b000111;
3888 
      12'd2420 :  mem_out_dec = 6'b000111;
3889 
      12'd2421 :  mem_out_dec = 6'b000111;
3890 
      12'd2422 :  mem_out_dec = 6'b001000;
3891 
      12'd2423 :  mem_out_dec = 6'b001001;
3892 
      12'd2424 :  mem_out_dec = 6'b001001;
3893 
      12'd2425 :  mem_out_dec = 6'b001010;
3894 
      12'd2426 :  mem_out_dec = 6'b001010;
3895 
      12'd2427 :  mem_out_dec = 6'b001011;
3896 
      12'd2428 :  mem_out_dec = 6'b001100;
3897 
      12'd2429 :  mem_out_dec = 6'b001101;
3898 
      12'd2430 :  mem_out_dec = 6'b001101;
3899 
      12'd2431 :  mem_out_dec = 6'b001110;
3900 
      12'd2432 :  mem_out_dec = 6'b111111;
3901 
      12'd2433 :  mem_out_dec = 6'b111111;
3902 
      12'd2434 :  mem_out_dec = 6'b111111;
3903 
      12'd2435 :  mem_out_dec = 6'b111111;
3904 
      12'd2436 :  mem_out_dec = 6'b111111;
3905 
      12'd2437 :  mem_out_dec = 6'b111111;
3906 
      12'd2438 :  mem_out_dec = 6'b111111;
3907 
      12'd2439 :  mem_out_dec = 6'b111111;
3908 
      12'd2440 :  mem_out_dec = 6'b111111;
3909 
      12'd2441 :  mem_out_dec = 6'b111111;
3910 
      12'd2442 :  mem_out_dec = 6'b111111;
3911 
      12'd2443 :  mem_out_dec = 6'b111111;
3912 
      12'd2444 :  mem_out_dec = 6'b111111;
3913 
      12'd2445 :  mem_out_dec = 6'b111111;
3914 
      12'd2446 :  mem_out_dec = 6'b111111;
3915 
      12'd2447 :  mem_out_dec = 6'b111111;
3916 
      12'd2448 :  mem_out_dec = 6'b111111;
3917 
      12'd2449 :  mem_out_dec = 6'b111111;
3918 
      12'd2450 :  mem_out_dec = 6'b111111;
3919 
      12'd2451 :  mem_out_dec = 6'b111111;
3920 
      12'd2452 :  mem_out_dec = 6'b111111;
3921 
      12'd2453 :  mem_out_dec = 6'b111111;
3922 
      12'd2454 :  mem_out_dec = 6'b111111;
3923 
      12'd2455 :  mem_out_dec = 6'b111111;
3924 
      12'd2456 :  mem_out_dec = 6'b111111;
3925 
      12'd2457 :  mem_out_dec = 6'b111111;
3926 
      12'd2458 :  mem_out_dec = 6'b111111;
3927 
      12'd2459 :  mem_out_dec = 6'b111111;
3928 
      12'd2460 :  mem_out_dec = 6'b111111;
3929 
      12'd2461 :  mem_out_dec = 6'b111111;
3930 
      12'd2462 :  mem_out_dec = 6'b111111;
3931 
      12'd2463 :  mem_out_dec = 6'b111111;
3932 
      12'd2464 :  mem_out_dec = 6'b111111;
3933 
      12'd2465 :  mem_out_dec = 6'b111111;
3934 
      12'd2466 :  mem_out_dec = 6'b111111;
3935 
      12'd2467 :  mem_out_dec = 6'b111111;
3936 
      12'd2468 :  mem_out_dec = 6'b111111;
3937 
      12'd2469 :  mem_out_dec = 6'b111111;
3938 
      12'd2470 :  mem_out_dec = 6'b111111;
3939 
      12'd2471 :  mem_out_dec = 6'b111111;
3940 
      12'd2472 :  mem_out_dec = 6'b111111;
3941 
      12'd2473 :  mem_out_dec = 6'b111111;
3942 
      12'd2474 :  mem_out_dec = 6'b111111;
3943 
      12'd2475 :  mem_out_dec = 6'b111111;
3944 
      12'd2476 :  mem_out_dec = 6'b000101;
3945 
      12'd2477 :  mem_out_dec = 6'b000110;
3946 
      12'd2478 :  mem_out_dec = 6'b000111;
3947 
      12'd2479 :  mem_out_dec = 6'b000111;
3948 
      12'd2480 :  mem_out_dec = 6'b000110;
3949 
      12'd2481 :  mem_out_dec = 6'b000110;
3950 
      12'd2482 :  mem_out_dec = 6'b000110;
3951 
      12'd2483 :  mem_out_dec = 6'b000110;
3952 
      12'd2484 :  mem_out_dec = 6'b000110;
3953 
      12'd2485 :  mem_out_dec = 6'b000111;
3954 
      12'd2486 :  mem_out_dec = 6'b000111;
3955 
      12'd2487 :  mem_out_dec = 6'b001000;
3956 
      12'd2488 :  mem_out_dec = 6'b001001;
3957 
      12'd2489 :  mem_out_dec = 6'b001001;
3958 
      12'd2490 :  mem_out_dec = 6'b001010;
3959 
      12'd2491 :  mem_out_dec = 6'b001011;
3960 
      12'd2492 :  mem_out_dec = 6'b001011;
3961 
      12'd2493 :  mem_out_dec = 6'b001100;
3962 
      12'd2494 :  mem_out_dec = 6'b001101;
3963 
      12'd2495 :  mem_out_dec = 6'b001110;
3964 
      12'd2496 :  mem_out_dec = 6'b111111;
3965 
      12'd2497 :  mem_out_dec = 6'b111111;
3966 
      12'd2498 :  mem_out_dec = 6'b111111;
3967 
      12'd2499 :  mem_out_dec = 6'b111111;
3968 
      12'd2500 :  mem_out_dec = 6'b111111;
3969 
      12'd2501 :  mem_out_dec = 6'b111111;
3970 
      12'd2502 :  mem_out_dec = 6'b111111;
3971 
      12'd2503 :  mem_out_dec = 6'b111111;
3972 
      12'd2504 :  mem_out_dec = 6'b111111;
3973 
      12'd2505 :  mem_out_dec = 6'b111111;
3974 
      12'd2506 :  mem_out_dec = 6'b111111;
3975 
      12'd2507 :  mem_out_dec = 6'b111111;
3976 
      12'd2508 :  mem_out_dec = 6'b111111;
3977 
      12'd2509 :  mem_out_dec = 6'b111111;
3978 
      12'd2510 :  mem_out_dec = 6'b111111;
3979 
      12'd2511 :  mem_out_dec = 6'b111111;
3980 
      12'd2512 :  mem_out_dec = 6'b111111;
3981 
      12'd2513 :  mem_out_dec = 6'b111111;
3982 
      12'd2514 :  mem_out_dec = 6'b111111;
3983 
      12'd2515 :  mem_out_dec = 6'b111111;
3984 
      12'd2516 :  mem_out_dec = 6'b111111;
3985 
      12'd2517 :  mem_out_dec = 6'b111111;
3986 
      12'd2518 :  mem_out_dec = 6'b111111;
3987 
      12'd2519 :  mem_out_dec = 6'b111111;
3988 
      12'd2520 :  mem_out_dec = 6'b111111;
3989 
      12'd2521 :  mem_out_dec = 6'b111111;
3990 
      12'd2522 :  mem_out_dec = 6'b111111;
3991 
      12'd2523 :  mem_out_dec = 6'b111111;
3992 
      12'd2524 :  mem_out_dec = 6'b111111;
3993 
      12'd2525 :  mem_out_dec = 6'b111111;
3994 
      12'd2526 :  mem_out_dec = 6'b111111;
3995 
      12'd2527 :  mem_out_dec = 6'b111111;
3996 
      12'd2528 :  mem_out_dec = 6'b111111;
3997 
      12'd2529 :  mem_out_dec = 6'b111111;
3998 
      12'd2530 :  mem_out_dec = 6'b111111;
3999 
      12'd2531 :  mem_out_dec = 6'b111111;
4000 
      12'd2532 :  mem_out_dec = 6'b111111;
4001 
      12'd2533 :  mem_out_dec = 6'b111111;
4002 
      12'd2534 :  mem_out_dec = 6'b111111;
4003 
      12'd2535 :  mem_out_dec = 6'b111111;
4004 
      12'd2536 :  mem_out_dec = 6'b111111;
4005 
      12'd2537 :  mem_out_dec = 6'b111111;
4006 
      12'd2538 :  mem_out_dec = 6'b111111;
4007 
      12'd2539 :  mem_out_dec = 6'b111111;
4008 
      12'd2540 :  mem_out_dec = 6'b111111;
4009 
      12'd2541 :  mem_out_dec = 6'b000101;
4010 
      12'd2542 :  mem_out_dec = 6'b000110;
4011 
      12'd2543 :  mem_out_dec = 6'b000110;
4012 
      12'd2544 :  mem_out_dec = 6'b000110;
4013 
      12'd2545 :  mem_out_dec = 6'b000110;
4014 
      12'd2546 :  mem_out_dec = 6'b000101;
4015 
      12'd2547 :  mem_out_dec = 6'b000101;
4016 
      12'd2548 :  mem_out_dec = 6'b000110;
4017 
      12'd2549 :  mem_out_dec = 6'b000111;
4018 
      12'd2550 :  mem_out_dec = 6'b000111;
4019 
      12'd2551 :  mem_out_dec = 6'b001000;
4020 
      12'd2552 :  mem_out_dec = 6'b001000;
4021 
      12'd2553 :  mem_out_dec = 6'b001001;
4022 
      12'd2554 :  mem_out_dec = 6'b001010;
4023 
      12'd2555 :  mem_out_dec = 6'b001010;
4024 
      12'd2556 :  mem_out_dec = 6'b001011;
4025 
      12'd2557 :  mem_out_dec = 6'b001100;
4026 
      12'd2558 :  mem_out_dec = 6'b001101;
4027 
      12'd2559 :  mem_out_dec = 6'b001101;
4028 
      12'd2560 :  mem_out_dec = 6'b111111;
4029 
      12'd2561 :  mem_out_dec = 6'b111111;
4030 
      12'd2562 :  mem_out_dec = 6'b111111;
4031 
      12'd2563 :  mem_out_dec = 6'b111111;
4032 
      12'd2564 :  mem_out_dec = 6'b111111;
4033 
      12'd2565 :  mem_out_dec = 6'b111111;
4034 
      12'd2566 :  mem_out_dec = 6'b111111;
4035 
      12'd2567 :  mem_out_dec = 6'b111111;
4036 
      12'd2568 :  mem_out_dec = 6'b111111;
4037 
      12'd2569 :  mem_out_dec = 6'b111111;
4038 
      12'd2570 :  mem_out_dec = 6'b111111;
4039 
      12'd2571 :  mem_out_dec = 6'b111111;
4040 
      12'd2572 :  mem_out_dec = 6'b111111;
4041 
      12'd2573 :  mem_out_dec = 6'b111111;
4042 
      12'd2574 :  mem_out_dec = 6'b111111;
4043 
      12'd2575 :  mem_out_dec = 6'b111111;
4044 
      12'd2576 :  mem_out_dec = 6'b111111;
4045 
      12'd2577 :  mem_out_dec = 6'b111111;
4046 
      12'd2578 :  mem_out_dec = 6'b111111;
4047 
      12'd2579 :  mem_out_dec = 6'b111111;
4048 
      12'd2580 :  mem_out_dec = 6'b111111;
4049 
      12'd2581 :  mem_out_dec = 6'b111111;
4050 
      12'd2582 :  mem_out_dec = 6'b111111;
4051 
      12'd2583 :  mem_out_dec = 6'b111111;
4052 
      12'd2584 :  mem_out_dec = 6'b111111;
4053 
      12'd2585 :  mem_out_dec = 6'b111111;
4054 
      12'd2586 :  mem_out_dec = 6'b111111;
4055 
      12'd2587 :  mem_out_dec = 6'b111111;
4056 
      12'd2588 :  mem_out_dec = 6'b111111;
4057 
      12'd2589 :  mem_out_dec = 6'b111111;
4058 
      12'd2590 :  mem_out_dec = 6'b111111;
4059 
      12'd2591 :  mem_out_dec = 6'b111111;
4060 
      12'd2592 :  mem_out_dec = 6'b111111;
4061 
      12'd2593 :  mem_out_dec = 6'b111111;
4062 
      12'd2594 :  mem_out_dec = 6'b111111;
4063 
      12'd2595 :  mem_out_dec = 6'b111111;
4064 
      12'd2596 :  mem_out_dec = 6'b111111;
4065 
      12'd2597 :  mem_out_dec = 6'b111111;
4066 
      12'd2598 :  mem_out_dec = 6'b111111;
4067 
      12'd2599 :  mem_out_dec = 6'b111111;
4068 
      12'd2600 :  mem_out_dec = 6'b111111;
4069 
      12'd2601 :  mem_out_dec = 6'b111111;
4070 
      12'd2602 :  mem_out_dec = 6'b111111;
4071 
      12'd2603 :  mem_out_dec = 6'b111111;
4072 
      12'd2604 :  mem_out_dec = 6'b111111;
4073 
      12'd2605 :  mem_out_dec = 6'b111111;
4074 
      12'd2606 :  mem_out_dec = 6'b000100;
4075 
      12'd2607 :  mem_out_dec = 6'b000101;
4076 
      12'd2608 :  mem_out_dec = 6'b000100;
4077 
      12'd2609 :  mem_out_dec = 6'b000100;
4078 
      12'd2610 :  mem_out_dec = 6'b000100;
4079 
      12'd2611 :  mem_out_dec = 6'b000101;
4080 
      12'd2612 :  mem_out_dec = 6'b000101;
4081 
      12'd2613 :  mem_out_dec = 6'b000110;
4082 
      12'd2614 :  mem_out_dec = 6'b000111;
4083 
      12'd2615 :  mem_out_dec = 6'b000111;
4084 
      12'd2616 :  mem_out_dec = 6'b000111;
4085 
      12'd2617 :  mem_out_dec = 6'b001000;
4086 
      12'd2618 :  mem_out_dec = 6'b001001;
4087 
      12'd2619 :  mem_out_dec = 6'b001010;
4088 
      12'd2620 :  mem_out_dec = 6'b001010;
4089 
      12'd2621 :  mem_out_dec = 6'b001011;
4090 
      12'd2622 :  mem_out_dec = 6'b001100;
4091 
      12'd2623 :  mem_out_dec = 6'b001101;
4092 
      12'd2624 :  mem_out_dec = 6'b111111;
4093 
      12'd2625 :  mem_out_dec = 6'b111111;
4094 
      12'd2626 :  mem_out_dec = 6'b111111;
4095 
      12'd2627 :  mem_out_dec = 6'b111111;
4096 
      12'd2628 :  mem_out_dec = 6'b111111;
4097 
      12'd2629 :  mem_out_dec = 6'b111111;
4098 
      12'd2630 :  mem_out_dec = 6'b111111;
4099 
      12'd2631 :  mem_out_dec = 6'b111111;
4100 
      12'd2632 :  mem_out_dec = 6'b111111;
4101 
      12'd2633 :  mem_out_dec = 6'b111111;
4102 
      12'd2634 :  mem_out_dec = 6'b111111;
4103 
      12'd2635 :  mem_out_dec = 6'b111111;
4104 
      12'd2636 :  mem_out_dec = 6'b111111;
4105 
      12'd2637 :  mem_out_dec = 6'b111111;
4106 
      12'd2638 :  mem_out_dec = 6'b111111;
4107 
      12'd2639 :  mem_out_dec = 6'b111111;
4108 
      12'd2640 :  mem_out_dec = 6'b111111;
4109 
      12'd2641 :  mem_out_dec = 6'b111111;
4110 
      12'd2642 :  mem_out_dec = 6'b111111;
4111 
      12'd2643 :  mem_out_dec = 6'b111111;
4112 
      12'd2644 :  mem_out_dec = 6'b111111;
4113 
      12'd2645 :  mem_out_dec = 6'b111111;
4114 
      12'd2646 :  mem_out_dec = 6'b111111;
4115 
      12'd2647 :  mem_out_dec = 6'b111111;
4116 
      12'd2648 :  mem_out_dec = 6'b111111;
4117 
      12'd2649 :  mem_out_dec = 6'b111111;
4118 
      12'd2650 :  mem_out_dec = 6'b111111;
4119 
      12'd2651 :  mem_out_dec = 6'b111111;
4120 
      12'd2652 :  mem_out_dec = 6'b111111;
4121 
      12'd2653 :  mem_out_dec = 6'b111111;
4122 
      12'd2654 :  mem_out_dec = 6'b111111;
4123 
      12'd2655 :  mem_out_dec = 6'b111111;
4124 
      12'd2656 :  mem_out_dec = 6'b111111;
4125 
      12'd2657 :  mem_out_dec = 6'b111111;
4126 
      12'd2658 :  mem_out_dec = 6'b111111;
4127 
      12'd2659 :  mem_out_dec = 6'b111111;
4128 
      12'd2660 :  mem_out_dec = 6'b111111;
4129 
      12'd2661 :  mem_out_dec = 6'b111111;
4130 
      12'd2662 :  mem_out_dec = 6'b111111;
4131 
      12'd2663 :  mem_out_dec = 6'b111111;
4132 
      12'd2664 :  mem_out_dec = 6'b111111;
4133 
      12'd2665 :  mem_out_dec = 6'b111111;
4134 
      12'd2666 :  mem_out_dec = 6'b111111;
4135 
      12'd2667 :  mem_out_dec = 6'b111111;
4136 
      12'd2668 :  mem_out_dec = 6'b111111;
4137 
      12'd2669 :  mem_out_dec = 6'b111111;
4138 
      12'd2670 :  mem_out_dec = 6'b111111;
4139 
      12'd2671 :  mem_out_dec = 6'b000100;
4140 
      12'd2672 :  mem_out_dec = 6'b000011;
4141 
      12'd2673 :  mem_out_dec = 6'b000011;
4142 
      12'd2674 :  mem_out_dec = 6'b000100;
4143 
      12'd2675 :  mem_out_dec = 6'b000100;
4144 
      12'd2676 :  mem_out_dec = 6'b000101;
4145 
      12'd2677 :  mem_out_dec = 6'b000110;
4146 
      12'd2678 :  mem_out_dec = 6'b000110;
4147 
      12'd2679 :  mem_out_dec = 6'b000111;
4148 
      12'd2680 :  mem_out_dec = 6'b000111;
4149 
      12'd2681 :  mem_out_dec = 6'b001000;
4150 
      12'd2682 :  mem_out_dec = 6'b001001;
4151 
      12'd2683 :  mem_out_dec = 6'b001001;
4152 
      12'd2684 :  mem_out_dec = 6'b001010;
4153 
      12'd2685 :  mem_out_dec = 6'b001011;
4154 
      12'd2686 :  mem_out_dec = 6'b001100;
4155 
      12'd2687 :  mem_out_dec = 6'b001100;
4156 
      12'd2688 :  mem_out_dec = 6'b111111;
4157 
      12'd2689 :  mem_out_dec = 6'b111111;
4158 
      12'd2690 :  mem_out_dec = 6'b111111;
4159 
      12'd2691 :  mem_out_dec = 6'b111111;
4160 
      12'd2692 :  mem_out_dec = 6'b111111;
4161 
      12'd2693 :  mem_out_dec = 6'b111111;
4162 
      12'd2694 :  mem_out_dec = 6'b111111;
4163 
      12'd2695 :  mem_out_dec = 6'b111111;
4164 
      12'd2696 :  mem_out_dec = 6'b111111;
4165 
      12'd2697 :  mem_out_dec = 6'b111111;
4166 
      12'd2698 :  mem_out_dec = 6'b111111;
4167 
      12'd2699 :  mem_out_dec = 6'b111111;
4168 
      12'd2700 :  mem_out_dec = 6'b111111;
4169 
      12'd2701 :  mem_out_dec = 6'b111111;
4170 
      12'd2702 :  mem_out_dec = 6'b111111;
4171 
      12'd2703 :  mem_out_dec = 6'b111111;
4172 
      12'd2704 :  mem_out_dec = 6'b111111;
4173 
      12'd2705 :  mem_out_dec = 6'b111111;
4174 
      12'd2706 :  mem_out_dec = 6'b111111;
4175 
      12'd2707 :  mem_out_dec = 6'b111111;
4176 
      12'd2708 :  mem_out_dec = 6'b111111;
4177 
      12'd2709 :  mem_out_dec = 6'b111111;
4178 
      12'd2710 :  mem_out_dec = 6'b111111;
4179 
      12'd2711 :  mem_out_dec = 6'b111111;
4180 
      12'd2712 :  mem_out_dec = 6'b111111;
4181 
      12'd2713 :  mem_out_dec = 6'b111111;
4182 
      12'd2714 :  mem_out_dec = 6'b111111;
4183 
      12'd2715 :  mem_out_dec = 6'b111111;
4184 
      12'd2716 :  mem_out_dec = 6'b111111;
4185 
      12'd2717 :  mem_out_dec = 6'b111111;
4186 
      12'd2718 :  mem_out_dec = 6'b111111;
4187 
      12'd2719 :  mem_out_dec = 6'b111111;
4188 
      12'd2720 :  mem_out_dec = 6'b111111;
4189 
      12'd2721 :  mem_out_dec = 6'b111111;
4190 
      12'd2722 :  mem_out_dec = 6'b111111;
4191 
      12'd2723 :  mem_out_dec = 6'b111111;
4192 
      12'd2724 :  mem_out_dec = 6'b111111;
4193 
      12'd2725 :  mem_out_dec = 6'b111111;
4194 
      12'd2726 :  mem_out_dec = 6'b111111;
4195 
      12'd2727 :  mem_out_dec = 6'b111111;
4196 
      12'd2728 :  mem_out_dec = 6'b111111;
4197 
      12'd2729 :  mem_out_dec = 6'b111111;
4198 
      12'd2730 :  mem_out_dec = 6'b111111;
4199 
      12'd2731 :  mem_out_dec = 6'b111111;
4200 
      12'd2732 :  mem_out_dec = 6'b111111;
4201 
      12'd2733 :  mem_out_dec = 6'b111111;
4202 
      12'd2734 :  mem_out_dec = 6'b111111;
4203 
      12'd2735 :  mem_out_dec = 6'b111111;
4204 
      12'd2736 :  mem_out_dec = 6'b000011;
4205 
      12'd2737 :  mem_out_dec = 6'b000011;
4206 
      12'd2738 :  mem_out_dec = 6'b000100;
4207 
      12'd2739 :  mem_out_dec = 6'b000100;
4208 
      12'd2740 :  mem_out_dec = 6'b000101;
4209 
      12'd2741 :  mem_out_dec = 6'b000101;
4210 
      12'd2742 :  mem_out_dec = 6'b000110;
4211 
      12'd2743 :  mem_out_dec = 6'b000111;
4212 
      12'd2744 :  mem_out_dec = 6'b000111;
4213 
      12'd2745 :  mem_out_dec = 6'b001000;
4214 
      12'd2746 :  mem_out_dec = 6'b001000;
4215 
      12'd2747 :  mem_out_dec = 6'b001001;
4216 
      12'd2748 :  mem_out_dec = 6'b001010;
4217 
      12'd2749 :  mem_out_dec = 6'b001011;
4218 
      12'd2750 :  mem_out_dec = 6'b001011;
4219 
      12'd2751 :  mem_out_dec = 6'b001100;
4220 
      12'd2752 :  mem_out_dec = 6'b111111;
4221 
      12'd2753 :  mem_out_dec = 6'b111111;
4222 
      12'd2754 :  mem_out_dec = 6'b111111;
4223 
      12'd2755 :  mem_out_dec = 6'b111111;
4224 
      12'd2756 :  mem_out_dec = 6'b111111;
4225 
      12'd2757 :  mem_out_dec = 6'b111111;
4226 
      12'd2758 :  mem_out_dec = 6'b111111;
4227 
      12'd2759 :  mem_out_dec = 6'b111111;
4228 
      12'd2760 :  mem_out_dec = 6'b111111;
4229 
      12'd2761 :  mem_out_dec = 6'b111111;
4230 
      12'd2762 :  mem_out_dec = 6'b111111;
4231 
      12'd2763 :  mem_out_dec = 6'b111111;
4232 
      12'd2764 :  mem_out_dec = 6'b111111;
4233 
      12'd2765 :  mem_out_dec = 6'b111111;
4234 
      12'd2766 :  mem_out_dec = 6'b111111;
4235 
      12'd2767 :  mem_out_dec = 6'b111111;
4236 
      12'd2768 :  mem_out_dec = 6'b111111;
4237 
      12'd2769 :  mem_out_dec = 6'b111111;
4238 
      12'd2770 :  mem_out_dec = 6'b111111;
4239 
      12'd2771 :  mem_out_dec = 6'b111111;
4240 
      12'd2772 :  mem_out_dec = 6'b111111;
4241 
      12'd2773 :  mem_out_dec = 6'b111111;
4242 
      12'd2774 :  mem_out_dec = 6'b111111;
4243 
      12'd2775 :  mem_out_dec = 6'b111111;
4244 
      12'd2776 :  mem_out_dec = 6'b111111;
4245 
      12'd2777 :  mem_out_dec = 6'b111111;
4246 
      12'd2778 :  mem_out_dec = 6'b111111;
4247 
      12'd2779 :  mem_out_dec = 6'b111111;
4248 
      12'd2780 :  mem_out_dec = 6'b111111;
4249 
      12'd2781 :  mem_out_dec = 6'b111111;
4250 
      12'd2782 :  mem_out_dec = 6'b111111;
4251 
      12'd2783 :  mem_out_dec = 6'b111111;
4252 
      12'd2784 :  mem_out_dec = 6'b111111;
4253 
      12'd2785 :  mem_out_dec = 6'b111111;
4254 
      12'd2786 :  mem_out_dec = 6'b111111;
4255 
      12'd2787 :  mem_out_dec = 6'b111111;
4256 
      12'd2788 :  mem_out_dec = 6'b111111;
4257 
      12'd2789 :  mem_out_dec = 6'b111111;
4258 
      12'd2790 :  mem_out_dec = 6'b111111;
4259 
      12'd2791 :  mem_out_dec = 6'b111111;
4260 
      12'd2792 :  mem_out_dec = 6'b111111;
4261 
      12'd2793 :  mem_out_dec = 6'b111111;
4262 
      12'd2794 :  mem_out_dec = 6'b111111;
4263 
      12'd2795 :  mem_out_dec = 6'b111111;
4264 
      12'd2796 :  mem_out_dec = 6'b111111;
4265 
      12'd2797 :  mem_out_dec = 6'b111111;
4266 
      12'd2798 :  mem_out_dec = 6'b111111;
4267 
      12'd2799 :  mem_out_dec = 6'b111111;
4268 
      12'd2800 :  mem_out_dec = 6'b111111;
4269 
      12'd2801 :  mem_out_dec = 6'b000011;
4270 
      12'd2802 :  mem_out_dec = 6'b000011;
4271 
      12'd2803 :  mem_out_dec = 6'b000100;
4272 
      12'd2804 :  mem_out_dec = 6'b000101;
4273 
      12'd2805 :  mem_out_dec = 6'b000101;
4274 
      12'd2806 :  mem_out_dec = 6'b000110;
4275 
      12'd2807 :  mem_out_dec = 6'b000111;
4276 
      12'd2808 :  mem_out_dec = 6'b000111;
4277 
      12'd2809 :  mem_out_dec = 6'b000111;
4278 
      12'd2810 :  mem_out_dec = 6'b001000;
4279 
      12'd2811 :  mem_out_dec = 6'b001001;
4280 
      12'd2812 :  mem_out_dec = 6'b001010;
4281 
      12'd2813 :  mem_out_dec = 6'b001010;
4282 
      12'd2814 :  mem_out_dec = 6'b001011;
4283 
      12'd2815 :  mem_out_dec = 6'b001100;
4284 
      12'd2816 :  mem_out_dec = 6'b111111;
4285 
      12'd2817 :  mem_out_dec = 6'b111111;
4286 
      12'd2818 :  mem_out_dec = 6'b111111;
4287 
      12'd2819 :  mem_out_dec = 6'b111111;
4288 
      12'd2820 :  mem_out_dec = 6'b111111;
4289 
      12'd2821 :  mem_out_dec = 6'b111111;
4290 
      12'd2822 :  mem_out_dec = 6'b111111;
4291 
      12'd2823 :  mem_out_dec = 6'b111111;
4292 
      12'd2824 :  mem_out_dec = 6'b111111;
4293 
      12'd2825 :  mem_out_dec = 6'b111111;
4294 
      12'd2826 :  mem_out_dec = 6'b111111;
4295 
      12'd2827 :  mem_out_dec = 6'b111111;
4296 
      12'd2828 :  mem_out_dec = 6'b111111;
4297 
      12'd2829 :  mem_out_dec = 6'b111111;
4298 
      12'd2830 :  mem_out_dec = 6'b111111;
4299 
      12'd2831 :  mem_out_dec = 6'b111111;
4300 
      12'd2832 :  mem_out_dec = 6'b111111;
4301 
      12'd2833 :  mem_out_dec = 6'b111111;
4302 
      12'd2834 :  mem_out_dec = 6'b111111;
4303 
      12'd2835 :  mem_out_dec = 6'b111111;
4304 
      12'd2836 :  mem_out_dec = 6'b111111;
4305 
      12'd2837 :  mem_out_dec = 6'b111111;
4306 
      12'd2838 :  mem_out_dec = 6'b111111;
4307 
      12'd2839 :  mem_out_dec = 6'b111111;
4308 
      12'd2840 :  mem_out_dec = 6'b111111;
4309 
      12'd2841 :  mem_out_dec = 6'b111111;
4310 
      12'd2842 :  mem_out_dec = 6'b111111;
4311 
      12'd2843 :  mem_out_dec = 6'b111111;
4312 
      12'd2844 :  mem_out_dec = 6'b111111;
4313 
      12'd2845 :  mem_out_dec = 6'b111111;
4314 
      12'd2846 :  mem_out_dec = 6'b111111;
4315 
      12'd2847 :  mem_out_dec = 6'b111111;
4316 
      12'd2848 :  mem_out_dec = 6'b111111;
4317 
      12'd2849 :  mem_out_dec = 6'b111111;
4318 
      12'd2850 :  mem_out_dec = 6'b111111;
4319 
      12'd2851 :  mem_out_dec = 6'b111111;
4320 
      12'd2852 :  mem_out_dec = 6'b111111;
4321 
      12'd2853 :  mem_out_dec = 6'b111111;
4322 
      12'd2854 :  mem_out_dec = 6'b111111;
4323 
      12'd2855 :  mem_out_dec = 6'b111111;
4324 
      12'd2856 :  mem_out_dec = 6'b111111;
4325 
      12'd2857 :  mem_out_dec = 6'b111111;
4326 
      12'd2858 :  mem_out_dec = 6'b111111;
4327 
      12'd2859 :  mem_out_dec = 6'b111111;
4328 
      12'd2860 :  mem_out_dec = 6'b111111;
4329 
      12'd2861 :  mem_out_dec = 6'b111111;
4330 
      12'd2862 :  mem_out_dec = 6'b111111;
4331 
      12'd2863 :  mem_out_dec = 6'b111111;
4332 
      12'd2864 :  mem_out_dec = 6'b111111;
4333 
      12'd2865 :  mem_out_dec = 6'b111111;
4334 
      12'd2866 :  mem_out_dec = 6'b000011;
4335 
      12'd2867 :  mem_out_dec = 6'b000100;
4336 
      12'd2868 :  mem_out_dec = 6'b000100;
4337 
      12'd2869 :  mem_out_dec = 6'b000101;
4338 
      12'd2870 :  mem_out_dec = 6'b000110;
4339 
      12'd2871 :  mem_out_dec = 6'b000110;
4340 
      12'd2872 :  mem_out_dec = 6'b000110;
4341 
      12'd2873 :  mem_out_dec = 6'b000111;
4342 
      12'd2874 :  mem_out_dec = 6'b001000;
4343 
      12'd2875 :  mem_out_dec = 6'b001001;
4344 
      12'd2876 :  mem_out_dec = 6'b001001;
4345 
      12'd2877 :  mem_out_dec = 6'b001010;
4346 
      12'd2878 :  mem_out_dec = 6'b001011;
4347 
      12'd2879 :  mem_out_dec = 6'b001100;
4348 
      12'd2880 :  mem_out_dec = 6'b111111;
4349 
      12'd2881 :  mem_out_dec = 6'b111111;
4350 
      12'd2882 :  mem_out_dec = 6'b111111;
4351 
      12'd2883 :  mem_out_dec = 6'b111111;
4352 
      12'd2884 :  mem_out_dec = 6'b111111;
4353 
      12'd2885 :  mem_out_dec = 6'b111111;
4354 
      12'd2886 :  mem_out_dec = 6'b111111;
4355 
      12'd2887 :  mem_out_dec = 6'b111111;
4356 
      12'd2888 :  mem_out_dec = 6'b111111;
4357 
      12'd2889 :  mem_out_dec = 6'b111111;
4358 
      12'd2890 :  mem_out_dec = 6'b111111;
4359 
      12'd2891 :  mem_out_dec = 6'b111111;
4360 
      12'd2892 :  mem_out_dec = 6'b111111;
4361 
      12'd2893 :  mem_out_dec = 6'b111111;
4362 
      12'd2894 :  mem_out_dec = 6'b111111;
4363 
      12'd2895 :  mem_out_dec = 6'b111111;
4364 
      12'd2896 :  mem_out_dec = 6'b111111;
4365 
      12'd2897 :  mem_out_dec = 6'b111111;
4366 
      12'd2898 :  mem_out_dec = 6'b111111;
4367 
      12'd2899 :  mem_out_dec = 6'b111111;
4368 
      12'd2900 :  mem_out_dec = 6'b111111;
4369 
      12'd2901 :  mem_out_dec = 6'b111111;
4370 
      12'd2902 :  mem_out_dec = 6'b111111;
4371 
      12'd2903 :  mem_out_dec = 6'b111111;
4372 
      12'd2904 :  mem_out_dec = 6'b111111;
4373 
      12'd2905 :  mem_out_dec = 6'b111111;
4374 
      12'd2906 :  mem_out_dec = 6'b111111;
4375 
      12'd2907 :  mem_out_dec = 6'b111111;
4376 
      12'd2908 :  mem_out_dec = 6'b111111;
4377 
      12'd2909 :  mem_out_dec = 6'b111111;
4378 
      12'd2910 :  mem_out_dec = 6'b111111;
4379 
      12'd2911 :  mem_out_dec = 6'b111111;
4380 
      12'd2912 :  mem_out_dec = 6'b111111;
4381 
      12'd2913 :  mem_out_dec = 6'b111111;
4382 
      12'd2914 :  mem_out_dec = 6'b111111;
4383 
      12'd2915 :  mem_out_dec = 6'b111111;
4384 
      12'd2916 :  mem_out_dec = 6'b111111;
4385 
      12'd2917 :  mem_out_dec = 6'b111111;
4386 
      12'd2918 :  mem_out_dec = 6'b111111;
4387 
      12'd2919 :  mem_out_dec = 6'b111111;
4388 
      12'd2920 :  mem_out_dec = 6'b111111;
4389 
      12'd2921 :  mem_out_dec = 6'b111111;
4390 
      12'd2922 :  mem_out_dec = 6'b111111;
4391 
      12'd2923 :  mem_out_dec = 6'b111111;
4392 
      12'd2924 :  mem_out_dec = 6'b111111;
4393 
      12'd2925 :  mem_out_dec = 6'b111111;
4394 
      12'd2926 :  mem_out_dec = 6'b111111;
4395 
      12'd2927 :  mem_out_dec = 6'b111111;
4396 
      12'd2928 :  mem_out_dec = 6'b111111;
4397 
      12'd2929 :  mem_out_dec = 6'b111111;
4398 
      12'd2930 :  mem_out_dec = 6'b111111;
4399 
      12'd2931 :  mem_out_dec = 6'b000100;
4400 
      12'd2932 :  mem_out_dec = 6'b000100;
4401 
      12'd2933 :  mem_out_dec = 6'b000101;
4402 
      12'd2934 :  mem_out_dec = 6'b000101;
4403 
      12'd2935 :  mem_out_dec = 6'b000110;
4404 
      12'd2936 :  mem_out_dec = 6'b000110;
4405 
      12'd2937 :  mem_out_dec = 6'b000111;
4406 
      12'd2938 :  mem_out_dec = 6'b001000;
4407 
      12'd2939 :  mem_out_dec = 6'b001000;
4408 
      12'd2940 :  mem_out_dec = 6'b001001;
4409 
      12'd2941 :  mem_out_dec = 6'b001010;
4410 
      12'd2942 :  mem_out_dec = 6'b001011;
4411 
      12'd2943 :  mem_out_dec = 6'b001011;
4412 
      12'd2944 :  mem_out_dec = 6'b111111;
4413 
      12'd2945 :  mem_out_dec = 6'b111111;
4414 
      12'd2946 :  mem_out_dec = 6'b111111;
4415 
      12'd2947 :  mem_out_dec = 6'b111111;
4416 
      12'd2948 :  mem_out_dec = 6'b111111;
4417 
      12'd2949 :  mem_out_dec = 6'b111111;
4418 
      12'd2950 :  mem_out_dec = 6'b111111;
4419 
      12'd2951 :  mem_out_dec = 6'b111111;
4420 
      12'd2952 :  mem_out_dec = 6'b111111;
4421 
      12'd2953 :  mem_out_dec = 6'b111111;
4422 
      12'd2954 :  mem_out_dec = 6'b111111;
4423 
      12'd2955 :  mem_out_dec = 6'b111111;
4424 
      12'd2956 :  mem_out_dec = 6'b111111;
4425 
      12'd2957 :  mem_out_dec = 6'b111111;
4426 
      12'd2958 :  mem_out_dec = 6'b111111;
4427 
      12'd2959 :  mem_out_dec = 6'b111111;
4428 
      12'd2960 :  mem_out_dec = 6'b111111;
4429 
      12'd2961 :  mem_out_dec = 6'b111111;
4430 
      12'd2962 :  mem_out_dec = 6'b111111;
4431 
      12'd2963 :  mem_out_dec = 6'b111111;
4432 
      12'd2964 :  mem_out_dec = 6'b111111;
4433 
      12'd2965 :  mem_out_dec = 6'b111111;
4434 
      12'd2966 :  mem_out_dec = 6'b111111;
4435 
      12'd2967 :  mem_out_dec = 6'b111111;
4436 
      12'd2968 :  mem_out_dec = 6'b111111;
4437 
      12'd2969 :  mem_out_dec = 6'b111111;
4438 
      12'd2970 :  mem_out_dec = 6'b111111;
4439 
      12'd2971 :  mem_out_dec = 6'b111111;
4440 
      12'd2972 :  mem_out_dec = 6'b111111;
4441 
      12'd2973 :  mem_out_dec = 6'b111111;
4442 
      12'd2974 :  mem_out_dec = 6'b111111;
4443 
      12'd2975 :  mem_out_dec = 6'b111111;
4444 
      12'd2976 :  mem_out_dec = 6'b111111;
4445 
      12'd2977 :  mem_out_dec = 6'b111111;
4446 
      12'd2978 :  mem_out_dec = 6'b111111;
4447 
      12'd2979 :  mem_out_dec = 6'b111111;
4448 
      12'd2980 :  mem_out_dec = 6'b111111;
4449 
      12'd2981 :  mem_out_dec = 6'b111111;
4450 
      12'd2982 :  mem_out_dec = 6'b111111;
4451 
      12'd2983 :  mem_out_dec = 6'b111111;
4452 
      12'd2984 :  mem_out_dec = 6'b111111;
4453 
      12'd2985 :  mem_out_dec = 6'b111111;
4454 
      12'd2986 :  mem_out_dec = 6'b111111;
4455 
      12'd2987 :  mem_out_dec = 6'b111111;
4456 
      12'd2988 :  mem_out_dec = 6'b111111;
4457 
      12'd2989 :  mem_out_dec = 6'b111111;
4458 
      12'd2990 :  mem_out_dec = 6'b111111;
4459 
      12'd2991 :  mem_out_dec = 6'b111111;
4460 
      12'd2992 :  mem_out_dec = 6'b111111;
4461 
      12'd2993 :  mem_out_dec = 6'b111111;
4462 
      12'd2994 :  mem_out_dec = 6'b111111;
4463 
      12'd2995 :  mem_out_dec = 6'b111111;
4464 
      12'd2996 :  mem_out_dec = 6'b000100;
4465 
      12'd2997 :  mem_out_dec = 6'b000101;
4466 
      12'd2998 :  mem_out_dec = 6'b000101;
4467 
      12'd2999 :  mem_out_dec = 6'b000110;
4468 
      12'd3000 :  mem_out_dec = 6'b000110;
4469 
      12'd3001 :  mem_out_dec = 6'b000111;
4470 
      12'd3002 :  mem_out_dec = 6'b000111;
4471 
      12'd3003 :  mem_out_dec = 6'b001000;
4472 
      12'd3004 :  mem_out_dec = 6'b001001;
4473 
      12'd3005 :  mem_out_dec = 6'b001010;
4474 
      12'd3006 :  mem_out_dec = 6'b001010;
4475 
      12'd3007 :  mem_out_dec = 6'b001011;
4476 
      12'd3008 :  mem_out_dec = 6'b111111;
4477 
      12'd3009 :  mem_out_dec = 6'b111111;
4478 
      12'd3010 :  mem_out_dec = 6'b111111;
4479 
      12'd3011 :  mem_out_dec = 6'b111111;
4480 
      12'd3012 :  mem_out_dec = 6'b111111;
4481 
      12'd3013 :  mem_out_dec = 6'b111111;
4482 
      12'd3014 :  mem_out_dec = 6'b111111;
4483 
      12'd3015 :  mem_out_dec = 6'b111111;
4484 
      12'd3016 :  mem_out_dec = 6'b111111;
4485 
      12'd3017 :  mem_out_dec = 6'b111111;
4486 
      12'd3018 :  mem_out_dec = 6'b111111;
4487 
      12'd3019 :  mem_out_dec = 6'b111111;
4488 
      12'd3020 :  mem_out_dec = 6'b111111;
4489 
      12'd3021 :  mem_out_dec = 6'b111111;
4490 
      12'd3022 :  mem_out_dec = 6'b111111;
4491 
      12'd3023 :  mem_out_dec = 6'b111111;
4492 
      12'd3024 :  mem_out_dec = 6'b111111;
4493 
      12'd3025 :  mem_out_dec = 6'b111111;
4494 
      12'd3026 :  mem_out_dec = 6'b111111;
4495 
      12'd3027 :  mem_out_dec = 6'b111111;
4496 
      12'd3028 :  mem_out_dec = 6'b111111;
4497 
      12'd3029 :  mem_out_dec = 6'b111111;
4498 
      12'd3030 :  mem_out_dec = 6'b111111;
4499 
      12'd3031 :  mem_out_dec = 6'b111111;
4500 
      12'd3032 :  mem_out_dec = 6'b111111;
4501 
      12'd3033 :  mem_out_dec = 6'b111111;
4502 
      12'd3034 :  mem_out_dec = 6'b111111;
4503 
      12'd3035 :  mem_out_dec = 6'b111111;
4504 
      12'd3036 :  mem_out_dec = 6'b111111;
4505 
      12'd3037 :  mem_out_dec = 6'b111111;
4506 
      12'd3038 :  mem_out_dec = 6'b111111;
4507 
      12'd3039 :  mem_out_dec = 6'b111111;
4508 
      12'd3040 :  mem_out_dec = 6'b111111;
4509 
      12'd3041 :  mem_out_dec = 6'b111111;
4510 
      12'd3042 :  mem_out_dec = 6'b111111;
4511 
      12'd3043 :  mem_out_dec = 6'b111111;
4512 
      12'd3044 :  mem_out_dec = 6'b111111;
4513 
      12'd3045 :  mem_out_dec = 6'b111111;
4514 
      12'd3046 :  mem_out_dec = 6'b111111;
4515 
      12'd3047 :  mem_out_dec = 6'b111111;
4516 
      12'd3048 :  mem_out_dec = 6'b111111;
4517 
      12'd3049 :  mem_out_dec = 6'b111111;
4518 
      12'd3050 :  mem_out_dec = 6'b111111;
4519 
      12'd3051 :  mem_out_dec = 6'b111111;
4520 
      12'd3052 :  mem_out_dec = 6'b111111;
4521 
      12'd3053 :  mem_out_dec = 6'b111111;
4522 
      12'd3054 :  mem_out_dec = 6'b111111;
4523 
      12'd3055 :  mem_out_dec = 6'b111111;
4524 
      12'd3056 :  mem_out_dec = 6'b111111;
4525 
      12'd3057 :  mem_out_dec = 6'b111111;
4526 
      12'd3058 :  mem_out_dec = 6'b111111;
4527 
      12'd3059 :  mem_out_dec = 6'b111111;
4528 
      12'd3060 :  mem_out_dec = 6'b111111;
4529 
      12'd3061 :  mem_out_dec = 6'b000100;
4530 
      12'd3062 :  mem_out_dec = 6'b000101;
4531 
      12'd3063 :  mem_out_dec = 6'b000110;
4532 
      12'd3064 :  mem_out_dec = 6'b000110;
4533 
      12'd3065 :  mem_out_dec = 6'b000111;
4534 
      12'd3066 :  mem_out_dec = 6'b000111;
4535 
      12'd3067 :  mem_out_dec = 6'b001000;
4536 
      12'd3068 :  mem_out_dec = 6'b001001;
4537 
      12'd3069 :  mem_out_dec = 6'b001001;
4538 
      12'd3070 :  mem_out_dec = 6'b001010;
4539 
      12'd3071 :  mem_out_dec = 6'b001011;
4540 
      12'd3072 :  mem_out_dec = 6'b111111;
4541 
      12'd3073 :  mem_out_dec = 6'b111111;
4542 
      12'd3074 :  mem_out_dec = 6'b111111;
4543 
      12'd3075 :  mem_out_dec = 6'b111111;
4544 
      12'd3076 :  mem_out_dec = 6'b111111;
4545 
      12'd3077 :  mem_out_dec = 6'b111111;
4546 
      12'd3078 :  mem_out_dec = 6'b111111;
4547 
      12'd3079 :  mem_out_dec = 6'b111111;
4548 
      12'd3080 :  mem_out_dec = 6'b111111;
4549 
      12'd3081 :  mem_out_dec = 6'b111111;
4550 
      12'd3082 :  mem_out_dec = 6'b111111;
4551 
      12'd3083 :  mem_out_dec = 6'b111111;
4552 
      12'd3084 :  mem_out_dec = 6'b111111;
4553 
      12'd3085 :  mem_out_dec = 6'b111111;
4554 
      12'd3086 :  mem_out_dec = 6'b111111;
4555 
      12'd3087 :  mem_out_dec = 6'b111111;
4556 
      12'd3088 :  mem_out_dec = 6'b111111;
4557 
      12'd3089 :  mem_out_dec = 6'b111111;
4558 
      12'd3090 :  mem_out_dec = 6'b111111;
4559 
      12'd3091 :  mem_out_dec = 6'b111111;
4560 
      12'd3092 :  mem_out_dec = 6'b111111;
4561 
      12'd3093 :  mem_out_dec = 6'b111111;
4562 
      12'd3094 :  mem_out_dec = 6'b111111;
4563 
      12'd3095 :  mem_out_dec = 6'b111111;
4564 
      12'd3096 :  mem_out_dec = 6'b111111;
4565 
      12'd3097 :  mem_out_dec = 6'b111111;
4566 
      12'd3098 :  mem_out_dec = 6'b111111;
4567 
      12'd3099 :  mem_out_dec = 6'b111111;
4568 
      12'd3100 :  mem_out_dec = 6'b111111;
4569 
      12'd3101 :  mem_out_dec = 6'b111111;
4570 
      12'd3102 :  mem_out_dec = 6'b111111;
4571 
      12'd3103 :  mem_out_dec = 6'b111111;
4572 
      12'd3104 :  mem_out_dec = 6'b111111;
4573 
      12'd3105 :  mem_out_dec = 6'b111111;
4574 
      12'd3106 :  mem_out_dec = 6'b111111;
4575 
      12'd3107 :  mem_out_dec = 6'b111111;
4576 
      12'd3108 :  mem_out_dec = 6'b111111;
4577 
      12'd3109 :  mem_out_dec = 6'b111111;
4578 
      12'd3110 :  mem_out_dec = 6'b111111;
4579 
      12'd3111 :  mem_out_dec = 6'b111111;
4580 
      12'd3112 :  mem_out_dec = 6'b111111;
4581 
      12'd3113 :  mem_out_dec = 6'b111111;
4582 
      12'd3114 :  mem_out_dec = 6'b111111;
4583 
      12'd3115 :  mem_out_dec = 6'b111111;
4584 
      12'd3116 :  mem_out_dec = 6'b111111;
4585 
      12'd3117 :  mem_out_dec = 6'b111111;
4586 
      12'd3118 :  mem_out_dec = 6'b111111;
4587 
      12'd3119 :  mem_out_dec = 6'b111111;
4588 
      12'd3120 :  mem_out_dec = 6'b111111;
4589 
      12'd3121 :  mem_out_dec = 6'b111111;
4590 
      12'd3122 :  mem_out_dec = 6'b111111;
4591 
      12'd3123 :  mem_out_dec = 6'b111111;
4592 
      12'd3124 :  mem_out_dec = 6'b111111;
4593 
      12'd3125 :  mem_out_dec = 6'b111111;
4594 
      12'd3126 :  mem_out_dec = 6'b000100;
4595 
      12'd3127 :  mem_out_dec = 6'b000101;
4596 
      12'd3128 :  mem_out_dec = 6'b000101;
4597 
      12'd3129 :  mem_out_dec = 6'b000110;
4598 
      12'd3130 :  mem_out_dec = 6'b000110;
4599 
      12'd3131 :  mem_out_dec = 6'b000111;
4600 
      12'd3132 :  mem_out_dec = 6'b001000;
4601 
      12'd3133 :  mem_out_dec = 6'b001000;
4602 
      12'd3134 :  mem_out_dec = 6'b001001;
4603 
      12'd3135 :  mem_out_dec = 6'b001010;
4604 
      12'd3136 :  mem_out_dec = 6'b111111;
4605 
      12'd3137 :  mem_out_dec = 6'b111111;
4606 
      12'd3138 :  mem_out_dec = 6'b111111;
4607 
      12'd3139 :  mem_out_dec = 6'b111111;
4608 
      12'd3140 :  mem_out_dec = 6'b111111;
4609 
      12'd3141 :  mem_out_dec = 6'b111111;
4610 
      12'd3142 :  mem_out_dec = 6'b111111;
4611 
      12'd3143 :  mem_out_dec = 6'b111111;
4612 
      12'd3144 :  mem_out_dec = 6'b111111;
4613 
      12'd3145 :  mem_out_dec = 6'b111111;
4614 
      12'd3146 :  mem_out_dec = 6'b111111;
4615 
      12'd3147 :  mem_out_dec = 6'b111111;
4616 
      12'd3148 :  mem_out_dec = 6'b111111;
4617 
      12'd3149 :  mem_out_dec = 6'b111111;
4618 
      12'd3150 :  mem_out_dec = 6'b111111;
4619 
      12'd3151 :  mem_out_dec = 6'b111111;
4620 
      12'd3152 :  mem_out_dec = 6'b111111;
4621 
      12'd3153 :  mem_out_dec = 6'b111111;
4622 
      12'd3154 :  mem_out_dec = 6'b111111;
4623 
      12'd3155 :  mem_out_dec = 6'b111111;
4624 
      12'd3156 :  mem_out_dec = 6'b111111;
4625 
      12'd3157 :  mem_out_dec = 6'b111111;
4626 
      12'd3158 :  mem_out_dec = 6'b111111;
4627 
      12'd3159 :  mem_out_dec = 6'b111111;
4628 
      12'd3160 :  mem_out_dec = 6'b111111;
4629 
      12'd3161 :  mem_out_dec = 6'b111111;
4630 
      12'd3162 :  mem_out_dec = 6'b111111;
4631 
      12'd3163 :  mem_out_dec = 6'b111111;
4632 
      12'd3164 :  mem_out_dec = 6'b111111;
4633 
      12'd3165 :  mem_out_dec = 6'b111111;
4634 
      12'd3166 :  mem_out_dec = 6'b111111;
4635 
      12'd3167 :  mem_out_dec = 6'b111111;
4636 
      12'd3168 :  mem_out_dec = 6'b111111;
4637 
      12'd3169 :  mem_out_dec = 6'b111111;
4638 
      12'd3170 :  mem_out_dec = 6'b111111;
4639 
      12'd3171 :  mem_out_dec = 6'b111111;
4640 
      12'd3172 :  mem_out_dec = 6'b111111;
4641 
      12'd3173 :  mem_out_dec = 6'b111111;
4642 
      12'd3174 :  mem_out_dec = 6'b111111;
4643 
      12'd3175 :  mem_out_dec = 6'b111111;
4644 
      12'd3176 :  mem_out_dec = 6'b111111;
4645 
      12'd3177 :  mem_out_dec = 6'b111111;
4646 
      12'd3178 :  mem_out_dec = 6'b111111;
4647 
      12'd3179 :  mem_out_dec = 6'b111111;
4648 
      12'd3180 :  mem_out_dec = 6'b111111;
4649 
      12'd3181 :  mem_out_dec = 6'b111111;
4650 
      12'd3182 :  mem_out_dec = 6'b111111;
4651 
      12'd3183 :  mem_out_dec = 6'b111111;
4652 
      12'd3184 :  mem_out_dec = 6'b111111;
4653 
      12'd3185 :  mem_out_dec = 6'b111111;
4654 
      12'd3186 :  mem_out_dec = 6'b111111;
4655 
      12'd3187 :  mem_out_dec = 6'b111111;
4656 
      12'd3188 :  mem_out_dec = 6'b111111;
4657 
      12'd3189 :  mem_out_dec = 6'b111111;
4658 
      12'd3190 :  mem_out_dec = 6'b111111;
4659 
      12'd3191 :  mem_out_dec = 6'b000100;
4660 
      12'd3192 :  mem_out_dec = 6'b000100;
4661 
      12'd3193 :  mem_out_dec = 6'b000101;
4662 
      12'd3194 :  mem_out_dec = 6'b000110;
4663 
      12'd3195 :  mem_out_dec = 6'b000110;
4664 
      12'd3196 :  mem_out_dec = 6'b000111;
4665 
      12'd3197 :  mem_out_dec = 6'b001000;
4666 
      12'd3198 :  mem_out_dec = 6'b001000;
4667 
      12'd3199 :  mem_out_dec = 6'b001001;
4668 
      12'd3200 :  mem_out_dec = 6'b111111;
4669 
      12'd3201 :  mem_out_dec = 6'b111111;
4670 
      12'd3202 :  mem_out_dec = 6'b111111;
4671 
      12'd3203 :  mem_out_dec = 6'b111111;
4672 
      12'd3204 :  mem_out_dec = 6'b111111;
4673 
      12'd3205 :  mem_out_dec = 6'b111111;
4674 
      12'd3206 :  mem_out_dec = 6'b111111;
4675 
      12'd3207 :  mem_out_dec = 6'b111111;
4676 
      12'd3208 :  mem_out_dec = 6'b111111;
4677 
      12'd3209 :  mem_out_dec = 6'b111111;
4678 
      12'd3210 :  mem_out_dec = 6'b111111;
4679 
      12'd3211 :  mem_out_dec = 6'b111111;
4680 
      12'd3212 :  mem_out_dec = 6'b111111;
4681 
      12'd3213 :  mem_out_dec = 6'b111111;
4682 
      12'd3214 :  mem_out_dec = 6'b111111;
4683 
      12'd3215 :  mem_out_dec = 6'b111111;
4684 
      12'd3216 :  mem_out_dec = 6'b111111;
4685 
      12'd3217 :  mem_out_dec = 6'b111111;
4686 
      12'd3218 :  mem_out_dec = 6'b111111;
4687 
      12'd3219 :  mem_out_dec = 6'b111111;
4688 
      12'd3220 :  mem_out_dec = 6'b111111;
4689 
      12'd3221 :  mem_out_dec = 6'b111111;
4690 
      12'd3222 :  mem_out_dec = 6'b111111;
4691 
      12'd3223 :  mem_out_dec = 6'b111111;
4692 
      12'd3224 :  mem_out_dec = 6'b111111;
4693 
      12'd3225 :  mem_out_dec = 6'b111111;
4694 
      12'd3226 :  mem_out_dec = 6'b111111;
4695 
      12'd3227 :  mem_out_dec = 6'b111111;
4696 
      12'd3228 :  mem_out_dec = 6'b111111;
4697 
      12'd3229 :  mem_out_dec = 6'b111111;
4698 
      12'd3230 :  mem_out_dec = 6'b111111;
4699 
      12'd3231 :  mem_out_dec = 6'b111111;
4700 
      12'd3232 :  mem_out_dec = 6'b111111;
4701 
      12'd3233 :  mem_out_dec = 6'b111111;
4702 
      12'd3234 :  mem_out_dec = 6'b111111;
4703 
      12'd3235 :  mem_out_dec = 6'b111111;
4704 
      12'd3236 :  mem_out_dec = 6'b111111;
4705 
      12'd3237 :  mem_out_dec = 6'b111111;
4706 
      12'd3238 :  mem_out_dec = 6'b111111;
4707 
      12'd3239 :  mem_out_dec = 6'b111111;
4708 
      12'd3240 :  mem_out_dec = 6'b111111;
4709 
      12'd3241 :  mem_out_dec = 6'b111111;
4710 
      12'd3242 :  mem_out_dec = 6'b111111;
4711 
      12'd3243 :  mem_out_dec = 6'b111111;
4712 
      12'd3244 :  mem_out_dec = 6'b111111;
4713 
      12'd3245 :  mem_out_dec = 6'b111111;
4714 
      12'd3246 :  mem_out_dec = 6'b111111;
4715 
      12'd3247 :  mem_out_dec = 6'b111111;
4716 
      12'd3248 :  mem_out_dec = 6'b111111;
4717 
      12'd3249 :  mem_out_dec = 6'b111111;
4718 
      12'd3250 :  mem_out_dec = 6'b111111;
4719 
      12'd3251 :  mem_out_dec = 6'b111111;
4720 
      12'd3252 :  mem_out_dec = 6'b111111;
4721 
      12'd3253 :  mem_out_dec = 6'b111111;
4722 
      12'd3254 :  mem_out_dec = 6'b111111;
4723 
      12'd3255 :  mem_out_dec = 6'b111111;
4724 
      12'd3256 :  mem_out_dec = 6'b000100;
4725 
      12'd3257 :  mem_out_dec = 6'b000100;
4726 
      12'd3258 :  mem_out_dec = 6'b000101;
4727 
      12'd3259 :  mem_out_dec = 6'b000110;
4728 
      12'd3260 :  mem_out_dec = 6'b000110;
4729 
      12'd3261 :  mem_out_dec = 6'b000111;
4730 
      12'd3262 :  mem_out_dec = 6'b001000;
4731 
      12'd3263 :  mem_out_dec = 6'b001001;
4732 
      12'd3264 :  mem_out_dec = 6'b111111;
4733 
      12'd3265 :  mem_out_dec = 6'b111111;
4734 
      12'd3266 :  mem_out_dec = 6'b111111;
4735 
      12'd3267 :  mem_out_dec = 6'b111111;
4736 
      12'd3268 :  mem_out_dec = 6'b111111;
4737 
      12'd3269 :  mem_out_dec = 6'b111111;
4738 
      12'd3270 :  mem_out_dec = 6'b111111;
4739 
      12'd3271 :  mem_out_dec = 6'b111111;
4740 
      12'd3272 :  mem_out_dec = 6'b111111;
4741 
      12'd3273 :  mem_out_dec = 6'b111111;
4742 
      12'd3274 :  mem_out_dec = 6'b111111;
4743 
      12'd3275 :  mem_out_dec = 6'b111111;
4744 
      12'd3276 :  mem_out_dec = 6'b111111;
4745 
      12'd3277 :  mem_out_dec = 6'b111111;
4746 
      12'd3278 :  mem_out_dec = 6'b111111;
4747 
      12'd3279 :  mem_out_dec = 6'b111111;
4748 
      12'd3280 :  mem_out_dec = 6'b111111;
4749 
      12'd3281 :  mem_out_dec = 6'b111111;
4750 
      12'd3282 :  mem_out_dec = 6'b111111;
4751 
      12'd3283 :  mem_out_dec = 6'b111111;
4752 
      12'd3284 :  mem_out_dec = 6'b111111;
4753 
      12'd3285 :  mem_out_dec = 6'b111111;
4754 
      12'd3286 :  mem_out_dec = 6'b111111;
4755 
      12'd3287 :  mem_out_dec = 6'b111111;
4756 
      12'd3288 :  mem_out_dec = 6'b111111;
4757 
      12'd3289 :  mem_out_dec = 6'b111111;
4758 
      12'd3290 :  mem_out_dec = 6'b111111;
4759 
      12'd3291 :  mem_out_dec = 6'b111111;
4760 
      12'd3292 :  mem_out_dec = 6'b111111;
4761 
      12'd3293 :  mem_out_dec = 6'b111111;
4762 
      12'd3294 :  mem_out_dec = 6'b111111;
4763 
      12'd3295 :  mem_out_dec = 6'b111111;
4764 
      12'd3296 :  mem_out_dec = 6'b111111;
4765 
      12'd3297 :  mem_out_dec = 6'b111111;
4766 
      12'd3298 :  mem_out_dec = 6'b111111;
4767 
      12'd3299 :  mem_out_dec = 6'b111111;
4768 
      12'd3300 :  mem_out_dec = 6'b111111;
4769 
      12'd3301 :  mem_out_dec = 6'b111111;
4770 
      12'd3302 :  mem_out_dec = 6'b111111;
4771 
      12'd3303 :  mem_out_dec = 6'b111111;
4772 
      12'd3304 :  mem_out_dec = 6'b111111;
4773 
      12'd3305 :  mem_out_dec = 6'b111111;
4774 
      12'd3306 :  mem_out_dec = 6'b111111;
4775 
      12'd3307 :  mem_out_dec = 6'b111111;
4776 
      12'd3308 :  mem_out_dec = 6'b111111;
4777 
      12'd3309 :  mem_out_dec = 6'b111111;
4778 
      12'd3310 :  mem_out_dec = 6'b111111;
4779 
      12'd3311 :  mem_out_dec = 6'b111111;
4780 
      12'd3312 :  mem_out_dec = 6'b111111;
4781 
      12'd3313 :  mem_out_dec = 6'b111111;
4782 
      12'd3314 :  mem_out_dec = 6'b111111;
4783 
      12'd3315 :  mem_out_dec = 6'b111111;
4784 
      12'd3316 :  mem_out_dec = 6'b111111;
4785 
      12'd3317 :  mem_out_dec = 6'b111111;
4786 
      12'd3318 :  mem_out_dec = 6'b111111;
4787 
      12'd3319 :  mem_out_dec = 6'b111111;
4788 
      12'd3320 :  mem_out_dec = 6'b111111;
4789 
      12'd3321 :  mem_out_dec = 6'b000100;
4790 
      12'd3322 :  mem_out_dec = 6'b000100;
4791 
      12'd3323 :  mem_out_dec = 6'b000101;
4792 
      12'd3324 :  mem_out_dec = 6'b000110;
4793 
      12'd3325 :  mem_out_dec = 6'b000111;
4794 
      12'd3326 :  mem_out_dec = 6'b001000;
4795 
      12'd3327 :  mem_out_dec = 6'b001000;
4796 
      12'd3328 :  mem_out_dec = 6'b111111;
4797 
      12'd3329 :  mem_out_dec = 6'b111111;
4798 
      12'd3330 :  mem_out_dec = 6'b111111;
4799 
      12'd3331 :  mem_out_dec = 6'b111111;
4800 
      12'd3332 :  mem_out_dec = 6'b111111;
4801 
      12'd3333 :  mem_out_dec = 6'b111111;
4802 
      12'd3334 :  mem_out_dec = 6'b111111;
4803 
      12'd3335 :  mem_out_dec = 6'b111111;
4804 
      12'd3336 :  mem_out_dec = 6'b111111;
4805 
      12'd3337 :  mem_out_dec = 6'b111111;
4806 
      12'd3338 :  mem_out_dec = 6'b111111;
4807 
      12'd3339 :  mem_out_dec = 6'b111111;
4808 
      12'd3340 :  mem_out_dec = 6'b111111;
4809 
      12'd3341 :  mem_out_dec = 6'b111111;
4810 
      12'd3342 :  mem_out_dec = 6'b111111;
4811 
      12'd3343 :  mem_out_dec = 6'b111111;
4812 
      12'd3344 :  mem_out_dec = 6'b111111;
4813 
      12'd3345 :  mem_out_dec = 6'b111111;
4814 
      12'd3346 :  mem_out_dec = 6'b111111;
4815 
      12'd3347 :  mem_out_dec = 6'b111111;
4816 
      12'd3348 :  mem_out_dec = 6'b111111;
4817 
      12'd3349 :  mem_out_dec = 6'b111111;
4818 
      12'd3350 :  mem_out_dec = 6'b111111;
4819 
      12'd3351 :  mem_out_dec = 6'b111111;
4820 
      12'd3352 :  mem_out_dec = 6'b111111;
4821 
      12'd3353 :  mem_out_dec = 6'b111111;
4822 
      12'd3354 :  mem_out_dec = 6'b111111;
4823 
      12'd3355 :  mem_out_dec = 6'b111111;
4824 
      12'd3356 :  mem_out_dec = 6'b111111;
4825 
      12'd3357 :  mem_out_dec = 6'b111111;
4826 
      12'd3358 :  mem_out_dec = 6'b111111;
4827 
      12'd3359 :  mem_out_dec = 6'b111111;
4828 
      12'd3360 :  mem_out_dec = 6'b111111;
4829 
      12'd3361 :  mem_out_dec = 6'b111111;
4830 
      12'd3362 :  mem_out_dec = 6'b111111;
4831 
      12'd3363 :  mem_out_dec = 6'b111111;
4832 
      12'd3364 :  mem_out_dec = 6'b111111;
4833 
      12'd3365 :  mem_out_dec = 6'b111111;
4834 
      12'd3366 :  mem_out_dec = 6'b111111;
4835 
      12'd3367 :  mem_out_dec = 6'b111111;
4836 
      12'd3368 :  mem_out_dec = 6'b111111;
4837 
      12'd3369 :  mem_out_dec = 6'b111111;
4838 
      12'd3370 :  mem_out_dec = 6'b111111;
4839 
      12'd3371 :  mem_out_dec = 6'b111111;
4840 
      12'd3372 :  mem_out_dec = 6'b111111;
4841 
      12'd3373 :  mem_out_dec = 6'b111111;
4842 
      12'd3374 :  mem_out_dec = 6'b111111;
4843 
      12'd3375 :  mem_out_dec = 6'b111111;
4844 
      12'd3376 :  mem_out_dec = 6'b111111;
4845 
      12'd3377 :  mem_out_dec = 6'b111111;
4846 
      12'd3378 :  mem_out_dec = 6'b111111;
4847 
      12'd3379 :  mem_out_dec = 6'b111111;
4848 
      12'd3380 :  mem_out_dec = 6'b111111;
4849 
      12'd3381 :  mem_out_dec = 6'b111111;
4850 
      12'd3382 :  mem_out_dec = 6'b111111;
4851 
      12'd3383 :  mem_out_dec = 6'b111111;
4852 
      12'd3384 :  mem_out_dec = 6'b111111;
4853 
      12'd3385 :  mem_out_dec = 6'b111111;
4854 
      12'd3386 :  mem_out_dec = 6'b000100;
4855 
      12'd3387 :  mem_out_dec = 6'b000101;
4856 
      12'd3388 :  mem_out_dec = 6'b000110;
4857 
      12'd3389 :  mem_out_dec = 6'b000110;
4858 
      12'd3390 :  mem_out_dec = 6'b000111;
4859 
      12'd3391 :  mem_out_dec = 6'b001000;
4860 
      12'd3392 :  mem_out_dec = 6'b111111;
4861 
      12'd3393 :  mem_out_dec = 6'b111111;
4862 
      12'd3394 :  mem_out_dec = 6'b111111;
4863 
      12'd3395 :  mem_out_dec = 6'b111111;
4864 
      12'd3396 :  mem_out_dec = 6'b111111;
4865 
      12'd3397 :  mem_out_dec = 6'b111111;
4866 
      12'd3398 :  mem_out_dec = 6'b111111;
4867 
      12'd3399 :  mem_out_dec = 6'b111111;
4868 
      12'd3400 :  mem_out_dec = 6'b111111;
4869 
      12'd3401 :  mem_out_dec = 6'b111111;
4870 
      12'd3402 :  mem_out_dec = 6'b111111;
4871 
      12'd3403 :  mem_out_dec = 6'b111111;
4872 
      12'd3404 :  mem_out_dec = 6'b111111;
4873 
      12'd3405 :  mem_out_dec = 6'b111111;
4874 
      12'd3406 :  mem_out_dec = 6'b111111;
4875 
      12'd3407 :  mem_out_dec = 6'b111111;
4876 
      12'd3408 :  mem_out_dec = 6'b111111;
4877 
      12'd3409 :  mem_out_dec = 6'b111111;
4878 
      12'd3410 :  mem_out_dec = 6'b111111;
4879 
      12'd3411 :  mem_out_dec = 6'b111111;
4880 
      12'd3412 :  mem_out_dec = 6'b111111;
4881 
      12'd3413 :  mem_out_dec = 6'b111111;
4882 
      12'd3414 :  mem_out_dec = 6'b111111;
4883 
      12'd3415 :  mem_out_dec = 6'b111111;
4884 
      12'd3416 :  mem_out_dec = 6'b111111;
4885 
      12'd3417 :  mem_out_dec = 6'b111111;
4886 
      12'd3418 :  mem_out_dec = 6'b111111;
4887 
      12'd3419 :  mem_out_dec = 6'b111111;
4888 
      12'd3420 :  mem_out_dec = 6'b111111;
4889 
      12'd3421 :  mem_out_dec = 6'b111111;
4890 
      12'd3422 :  mem_out_dec = 6'b111111;
4891 
      12'd3423 :  mem_out_dec = 6'b111111;
4892 
      12'd3424 :  mem_out_dec = 6'b111111;
4893 
      12'd3425 :  mem_out_dec = 6'b111111;
4894 
      12'd3426 :  mem_out_dec = 6'b111111;
4895 
      12'd3427 :  mem_out_dec = 6'b111111;
4896 
      12'd3428 :  mem_out_dec = 6'b111111;
4897 
      12'd3429 :  mem_out_dec = 6'b111111;
4898 
      12'd3430 :  mem_out_dec = 6'b111111;
4899 
      12'd3431 :  mem_out_dec = 6'b111111;
4900 
      12'd3432 :  mem_out_dec = 6'b111111;
4901 
      12'd3433 :  mem_out_dec = 6'b111111;
4902 
      12'd3434 :  mem_out_dec = 6'b111111;
4903 
      12'd3435 :  mem_out_dec = 6'b111111;
4904 
      12'd3436 :  mem_out_dec = 6'b111111;
4905 
      12'd3437 :  mem_out_dec = 6'b111111;
4906 
      12'd3438 :  mem_out_dec = 6'b111111;
4907 
      12'd3439 :  mem_out_dec = 6'b111111;
4908 
      12'd3440 :  mem_out_dec = 6'b111111;
4909 
      12'd3441 :  mem_out_dec = 6'b111111;
4910 
      12'd3442 :  mem_out_dec = 6'b111111;
4911 
      12'd3443 :  mem_out_dec = 6'b111111;
4912 
      12'd3444 :  mem_out_dec = 6'b111111;
4913 
      12'd3445 :  mem_out_dec = 6'b111111;
4914 
      12'd3446 :  mem_out_dec = 6'b111111;
4915 
      12'd3447 :  mem_out_dec = 6'b111111;
4916 
      12'd3448 :  mem_out_dec = 6'b111111;
4917 
      12'd3449 :  mem_out_dec = 6'b111111;
4918 
      12'd3450 :  mem_out_dec = 6'b111111;
4919 
      12'd3451 :  mem_out_dec = 6'b000100;
4920 
      12'd3452 :  mem_out_dec = 6'b000101;
4921 
      12'd3453 :  mem_out_dec = 6'b000110;
4922 
      12'd3454 :  mem_out_dec = 6'b000111;
4923 
      12'd3455 :  mem_out_dec = 6'b001000;
4924 
      12'd3456 :  mem_out_dec = 6'b111111;
4925 
      12'd3457 :  mem_out_dec = 6'b111111;
4926 
      12'd3458 :  mem_out_dec = 6'b111111;
4927 
      12'd3459 :  mem_out_dec = 6'b111111;
4928 
      12'd3460 :  mem_out_dec = 6'b111111;
4929 
      12'd3461 :  mem_out_dec = 6'b111111;
4930 
      12'd3462 :  mem_out_dec = 6'b111111;
4931 
      12'd3463 :  mem_out_dec = 6'b111111;
4932 
      12'd3464 :  mem_out_dec = 6'b111111;
4933 
      12'd3465 :  mem_out_dec = 6'b111111;
4934 
      12'd3466 :  mem_out_dec = 6'b111111;
4935 
      12'd3467 :  mem_out_dec = 6'b111111;
4936 
      12'd3468 :  mem_out_dec = 6'b111111;
4937 
      12'd3469 :  mem_out_dec = 6'b111111;
4938 
      12'd3470 :  mem_out_dec = 6'b111111;
4939 
      12'd3471 :  mem_out_dec = 6'b111111;
4940 
      12'd3472 :  mem_out_dec = 6'b111111;
4941 
      12'd3473 :  mem_out_dec = 6'b111111;
4942 
      12'd3474 :  mem_out_dec = 6'b111111;
4943 
      12'd3475 :  mem_out_dec = 6'b111111;
4944 
      12'd3476 :  mem_out_dec = 6'b111111;
4945 
      12'd3477 :  mem_out_dec = 6'b111111;
4946 
      12'd3478 :  mem_out_dec = 6'b111111;
4947 
      12'd3479 :  mem_out_dec = 6'b111111;
4948 
      12'd3480 :  mem_out_dec = 6'b111111;
4949 
      12'd3481 :  mem_out_dec = 6'b111111;
4950 
      12'd3482 :  mem_out_dec = 6'b111111;
4951 
      12'd3483 :  mem_out_dec = 6'b111111;
4952 
      12'd3484 :  mem_out_dec = 6'b111111;
4953 
      12'd3485 :  mem_out_dec = 6'b111111;
4954 
      12'd3486 :  mem_out_dec = 6'b111111;
4955 
      12'd3487 :  mem_out_dec = 6'b111111;
4956 
      12'd3488 :  mem_out_dec = 6'b111111;
4957 
      12'd3489 :  mem_out_dec = 6'b111111;
4958 
      12'd3490 :  mem_out_dec = 6'b111111;
4959 
      12'd3491 :  mem_out_dec = 6'b111111;
4960 
      12'd3492 :  mem_out_dec = 6'b111111;
4961 
      12'd3493 :  mem_out_dec = 6'b111111;
4962 
      12'd3494 :  mem_out_dec = 6'b111111;
4963 
      12'd3495 :  mem_out_dec = 6'b111111;
4964 
      12'd3496 :  mem_out_dec = 6'b111111;
4965 
      12'd3497 :  mem_out_dec = 6'b111111;
4966 
      12'd3498 :  mem_out_dec = 6'b111111;
4967 
      12'd3499 :  mem_out_dec = 6'b111111;
4968 
      12'd3500 :  mem_out_dec = 6'b111111;
4969 
      12'd3501 :  mem_out_dec = 6'b111111;
4970 
      12'd3502 :  mem_out_dec = 6'b111111;
4971 
      12'd3503 :  mem_out_dec = 6'b111111;
4972 
      12'd3504 :  mem_out_dec = 6'b111111;
4973 
      12'd3505 :  mem_out_dec = 6'b111111;
4974 
      12'd3506 :  mem_out_dec = 6'b111111;
4975 
      12'd3507 :  mem_out_dec = 6'b111111;
4976 
      12'd3508 :  mem_out_dec = 6'b111111;
4977 
      12'd3509 :  mem_out_dec = 6'b111111;
4978 
      12'd3510 :  mem_out_dec = 6'b111111;
4979 
      12'd3511 :  mem_out_dec = 6'b111111;
4980 
      12'd3512 :  mem_out_dec = 6'b111111;
4981 
      12'd3513 :  mem_out_dec = 6'b111111;
4982 
      12'd3514 :  mem_out_dec = 6'b111111;
4983 
      12'd3515 :  mem_out_dec = 6'b111111;
4984 
      12'd3516 :  mem_out_dec = 6'b000101;
4985 
      12'd3517 :  mem_out_dec = 6'b000110;
4986 
      12'd3518 :  mem_out_dec = 6'b000110;
4987 
      12'd3519 :  mem_out_dec = 6'b000111;
4988 
      12'd3520 :  mem_out_dec = 6'b111111;
4989 
      12'd3521 :  mem_out_dec = 6'b111111;
4990 
      12'd3522 :  mem_out_dec = 6'b111111;
4991 
      12'd3523 :  mem_out_dec = 6'b111111;
4992 
      12'd3524 :  mem_out_dec = 6'b111111;
4993 
      12'd3525 :  mem_out_dec = 6'b111111;
4994 
      12'd3526 :  mem_out_dec = 6'b111111;
4995 
      12'd3527 :  mem_out_dec = 6'b111111;
4996 
      12'd3528 :  mem_out_dec = 6'b111111;
4997 
      12'd3529 :  mem_out_dec = 6'b111111;
4998 
      12'd3530 :  mem_out_dec = 6'b111111;
4999 
      12'd3531 :  mem_out_dec = 6'b111111;
5000 
      12'd3532 :  mem_out_dec = 6'b111111;
5001 
      12'd3533 :  mem_out_dec = 6'b111111;
5002 
      12'd3534 :  mem_out_dec = 6'b111111;
5003 
      12'd3535 :  mem_out_dec = 6'b111111;
5004 
      12'd3536 :  mem_out_dec = 6'b111111;
5005 
      12'd3537 :  mem_out_dec = 6'b111111;
5006 
      12'd3538 :  mem_out_dec = 6'b111111;
5007 
      12'd3539 :  mem_out_dec = 6'b111111;
5008 
      12'd3540 :  mem_out_dec = 6'b111111;
5009 
      12'd3541 :  mem_out_dec = 6'b111111;
5010 
      12'd3542 :  mem_out_dec = 6'b111111;
5011 
      12'd3543 :  mem_out_dec = 6'b111111;
5012 
      12'd3544 :  mem_out_dec = 6'b111111;
5013 
      12'd3545 :  mem_out_dec = 6'b111111;
5014 
      12'd3546 :  mem_out_dec = 6'b111111;
5015 
      12'd3547 :  mem_out_dec = 6'b111111;
5016 
      12'd3548 :  mem_out_dec = 6'b111111;
5017 
      12'd3549 :  mem_out_dec = 6'b111111;
5018 
      12'd3550 :  mem_out_dec = 6'b111111;
5019 
      12'd3551 :  mem_out_dec = 6'b111111;
5020 
      12'd3552 :  mem_out_dec = 6'b111111;
5021 
      12'd3553 :  mem_out_dec = 6'b111111;
5022 
      12'd3554 :  mem_out_dec = 6'b111111;
5023 
      12'd3555 :  mem_out_dec = 6'b111111;
5024 
      12'd3556 :  mem_out_dec = 6'b111111;
5025 
      12'd3557 :  mem_out_dec = 6'b111111;
5026 
      12'd3558 :  mem_out_dec = 6'b111111;
5027 
      12'd3559 :  mem_out_dec = 6'b111111;
5028 
      12'd3560 :  mem_out_dec = 6'b111111;
5029 
      12'd3561 :  mem_out_dec = 6'b111111;
5030 
      12'd3562 :  mem_out_dec = 6'b111111;
5031 
      12'd3563 :  mem_out_dec = 6'b111111;
5032 
      12'd3564 :  mem_out_dec = 6'b111111;
5033 
      12'd3565 :  mem_out_dec = 6'b111111;
5034 
      12'd3566 :  mem_out_dec = 6'b111111;
5035 
      12'd3567 :  mem_out_dec = 6'b111111;
5036 
      12'd3568 :  mem_out_dec = 6'b111111;
5037 
      12'd3569 :  mem_out_dec = 6'b111111;
5038 
      12'd3570 :  mem_out_dec = 6'b111111;
5039 
      12'd3571 :  mem_out_dec = 6'b111111;
5040 
      12'd3572 :  mem_out_dec = 6'b111111;
5041 
      12'd3573 :  mem_out_dec = 6'b111111;
5042 
      12'd3574 :  mem_out_dec = 6'b111111;
5043 
      12'd3575 :  mem_out_dec = 6'b111111;
5044 
      12'd3576 :  mem_out_dec = 6'b111111;
5045 
      12'd3577 :  mem_out_dec = 6'b111111;
5046 
      12'd3578 :  mem_out_dec = 6'b111111;
5047 
      12'd3579 :  mem_out_dec = 6'b111111;
5048 
      12'd3580 :  mem_out_dec = 6'b111111;
5049 
      12'd3581 :  mem_out_dec = 6'b000101;
5050 
      12'd3582 :  mem_out_dec = 6'b000110;
5051 
      12'd3583 :  mem_out_dec = 6'b000110;
5052 
      12'd3584 :  mem_out_dec = 6'b111111;
5053 
      12'd3585 :  mem_out_dec = 6'b111111;
5054 
      12'd3586 :  mem_out_dec = 6'b111111;
5055 
      12'd3587 :  mem_out_dec = 6'b111111;
5056 
      12'd3588 :  mem_out_dec = 6'b111111;
5057 
      12'd3589 :  mem_out_dec = 6'b111111;
5058 
      12'd3590 :  mem_out_dec = 6'b111111;
5059 
      12'd3591 :  mem_out_dec = 6'b111111;
5060 
      12'd3592 :  mem_out_dec = 6'b111111;
5061 
      12'd3593 :  mem_out_dec = 6'b111111;
5062 
      12'd3594 :  mem_out_dec = 6'b111111;
5063 
      12'd3595 :  mem_out_dec = 6'b111111;
5064 
      12'd3596 :  mem_out_dec = 6'b111111;
5065 
      12'd3597 :  mem_out_dec = 6'b111111;
5066 
      12'd3598 :  mem_out_dec = 6'b111111;
5067 
      12'd3599 :  mem_out_dec = 6'b111111;
5068 
      12'd3600 :  mem_out_dec = 6'b111111;
5069 
      12'd3601 :  mem_out_dec = 6'b111111;
5070 
      12'd3602 :  mem_out_dec = 6'b111111;
5071 
      12'd3603 :  mem_out_dec = 6'b111111;
5072 
      12'd3604 :  mem_out_dec = 6'b111111;
5073 
      12'd3605 :  mem_out_dec = 6'b111111;
5074 
      12'd3606 :  mem_out_dec = 6'b111111;
5075 
      12'd3607 :  mem_out_dec = 6'b111111;
5076 
      12'd3608 :  mem_out_dec = 6'b111111;
5077 
      12'd3609 :  mem_out_dec = 6'b111111;
5078 
      12'd3610 :  mem_out_dec = 6'b111111;
5079 
      12'd3611 :  mem_out_dec = 6'b111111;
5080 
      12'd3612 :  mem_out_dec = 6'b111111;
5081 
      12'd3613 :  mem_out_dec = 6'b111111;
5082 
      12'd3614 :  mem_out_dec = 6'b111111;
5083 
      12'd3615 :  mem_out_dec = 6'b111111;
5084 
      12'd3616 :  mem_out_dec = 6'b111111;
5085 
      12'd3617 :  mem_out_dec = 6'b111111;
5086 
      12'd3618 :  mem_out_dec = 6'b111111;
5087 
      12'd3619 :  mem_out_dec = 6'b111111;
5088 
      12'd3620 :  mem_out_dec = 6'b111111;
5089 
      12'd3621 :  mem_out_dec = 6'b111111;
5090 
      12'd3622 :  mem_out_dec = 6'b111111;
5091 
      12'd3623 :  mem_out_dec = 6'b111111;
5092 
      12'd3624 :  mem_out_dec = 6'b111111;
5093 
      12'd3625 :  mem_out_dec = 6'b111111;
5094 
      12'd3626 :  mem_out_dec = 6'b111111;
5095 
      12'd3627 :  mem_out_dec = 6'b111111;
5096 
      12'd3628 :  mem_out_dec = 6'b111111;
5097 
      12'd3629 :  mem_out_dec = 6'b111111;
5098 
      12'd3630 :  mem_out_dec = 6'b111111;
5099 
      12'd3631 :  mem_out_dec = 6'b111111;
5100 
      12'd3632 :  mem_out_dec = 6'b111111;
5101 
      12'd3633 :  mem_out_dec = 6'b111111;
5102 
      12'd3634 :  mem_out_dec = 6'b111111;
5103 
      12'd3635 :  mem_out_dec = 6'b111111;
5104 
      12'd3636 :  mem_out_dec = 6'b111111;
5105 
      12'd3637 :  mem_out_dec = 6'b111111;
5106 
      12'd3638 :  mem_out_dec = 6'b111111;
5107 
      12'd3639 :  mem_out_dec = 6'b111111;
5108 
      12'd3640 :  mem_out_dec = 6'b111111;
5109 
      12'd3641 :  mem_out_dec = 6'b111111;
5110 
      12'd3642 :  mem_out_dec = 6'b111111;
5111 
      12'd3643 :  mem_out_dec = 6'b111111;
5112 
      12'd3644 :  mem_out_dec = 6'b111111;
5113 
      12'd3645 :  mem_out_dec = 6'b111111;
5114 
      12'd3646 :  mem_out_dec = 6'b000100;
5115 
      12'd3647 :  mem_out_dec = 6'b000101;
5116 
      12'd3648 :  mem_out_dec = 6'b111111;
5117 
      12'd3649 :  mem_out_dec = 6'b111111;
5118 
      12'd3650 :  mem_out_dec = 6'b111111;
5119 
      12'd3651 :  mem_out_dec = 6'b111111;
5120 
      12'd3652 :  mem_out_dec = 6'b111111;
5121 
      12'd3653 :  mem_out_dec = 6'b111111;
5122 
      12'd3654 :  mem_out_dec = 6'b111111;
5123 
      12'd3655 :  mem_out_dec = 6'b111111;
5124 
      12'd3656 :  mem_out_dec = 6'b111111;
5125 
      12'd3657 :  mem_out_dec = 6'b111111;
5126 
      12'd3658 :  mem_out_dec = 6'b111111;
5127 
      12'd3659 :  mem_out_dec = 6'b111111;
5128 
      12'd3660 :  mem_out_dec = 6'b111111;
5129 
      12'd3661 :  mem_out_dec = 6'b111111;
5130 
      12'd3662 :  mem_out_dec = 6'b111111;
5131 
      12'd3663 :  mem_out_dec = 6'b111111;
5132 
      12'd3664 :  mem_out_dec = 6'b111111;
5133 
      12'd3665 :  mem_out_dec = 6'b111111;
5134 
      12'd3666 :  mem_out_dec = 6'b111111;
5135 
      12'd3667 :  mem_out_dec = 6'b111111;
5136 
      12'd3668 :  mem_out_dec = 6'b111111;
5137 
      12'd3669 :  mem_out_dec = 6'b111111;
5138 
      12'd3670 :  mem_out_dec = 6'b111111;
5139 
      12'd3671 :  mem_out_dec = 6'b111111;
5140 
      12'd3672 :  mem_out_dec = 6'b111111;
5141 
      12'd3673 :  mem_out_dec = 6'b111111;
5142 
      12'd3674 :  mem_out_dec = 6'b111111;
5143 
      12'd3675 :  mem_out_dec = 6'b111111;
5144 
      12'd3676 :  mem_out_dec = 6'b111111;
5145 
      12'd3677 :  mem_out_dec = 6'b111111;
5146 
      12'd3678 :  mem_out_dec = 6'b111111;
5147 
      12'd3679 :  mem_out_dec = 6'b111111;
5148 
      12'd3680 :  mem_out_dec = 6'b111111;
5149 
      12'd3681 :  mem_out_dec = 6'b111111;
5150 
      12'd3682 :  mem_out_dec = 6'b111111;
5151 
      12'd3683 :  mem_out_dec = 6'b111111;
5152 
      12'd3684 :  mem_out_dec = 6'b111111;
5153 
      12'd3685 :  mem_out_dec = 6'b111111;
5154 
      12'd3686 :  mem_out_dec = 6'b111111;
5155 
      12'd3687 :  mem_out_dec = 6'b111111;
5156 
      12'd3688 :  mem_out_dec = 6'b111111;
5157 
      12'd3689 :  mem_out_dec = 6'b111111;
5158 
      12'd3690 :  mem_out_dec = 6'b111111;
5159 
      12'd3691 :  mem_out_dec = 6'b111111;
5160 
      12'd3692 :  mem_out_dec = 6'b111111;
5161 
      12'd3693 :  mem_out_dec = 6'b111111;
5162 
      12'd3694 :  mem_out_dec = 6'b111111;
5163 
      12'd3695 :  mem_out_dec = 6'b111111;
5164 
      12'd3696 :  mem_out_dec = 6'b111111;
5165 
      12'd3697 :  mem_out_dec = 6'b111111;
5166 
      12'd3698 :  mem_out_dec = 6'b111111;
5167 
      12'd3699 :  mem_out_dec = 6'b111111;
5168 
      12'd3700 :  mem_out_dec = 6'b111111;
5169 
      12'd3701 :  mem_out_dec = 6'b111111;
5170 
      12'd3702 :  mem_out_dec = 6'b111111;
5171 
      12'd3703 :  mem_out_dec = 6'b111111;
5172 
      12'd3704 :  mem_out_dec = 6'b111111;
5173 
      12'd3705 :  mem_out_dec = 6'b111111;
5174 
      12'd3706 :  mem_out_dec = 6'b111111;
5175 
      12'd3707 :  mem_out_dec = 6'b111111;
5176 
      12'd3708 :  mem_out_dec = 6'b111111;
5177 
      12'd3709 :  mem_out_dec = 6'b111111;
5178 
      12'd3710 :  mem_out_dec = 6'b111111;
5179 
      12'd3711 :  mem_out_dec = 6'b000100;
5180 
      12'd3712 :  mem_out_dec = 6'b111111;
5181 
      12'd3713 :  mem_out_dec = 6'b111111;
5182 
      12'd3714 :  mem_out_dec = 6'b111111;
5183 
      12'd3715 :  mem_out_dec = 6'b111111;
5184 
      12'd3716 :  mem_out_dec = 6'b111111;
5185 
      12'd3717 :  mem_out_dec = 6'b111111;
5186 
      12'd3718 :  mem_out_dec = 6'b111111;
5187 
      12'd3719 :  mem_out_dec = 6'b111111;
5188 
      12'd3720 :  mem_out_dec = 6'b111111;
5189 
      12'd3721 :  mem_out_dec = 6'b111111;
5190 
      12'd3722 :  mem_out_dec = 6'b111111;
5191 
      12'd3723 :  mem_out_dec = 6'b111111;
5192 
      12'd3724 :  mem_out_dec = 6'b111111;
5193 
      12'd3725 :  mem_out_dec = 6'b111111;
5194 
      12'd3726 :  mem_out_dec = 6'b111111;
5195 
      12'd3727 :  mem_out_dec = 6'b111111;
5196 
      12'd3728 :  mem_out_dec = 6'b111111;
5197 
      12'd3729 :  mem_out_dec = 6'b111111;
5198 
      12'd3730 :  mem_out_dec = 6'b111111;
5199 
      12'd3731 :  mem_out_dec = 6'b111111;
5200 
      12'd3732 :  mem_out_dec = 6'b111111;
5201 
      12'd3733 :  mem_out_dec = 6'b111111;
5202 
      12'd3734 :  mem_out_dec = 6'b111111;
5203 
      12'd3735 :  mem_out_dec = 6'b111111;
5204 
      12'd3736 :  mem_out_dec = 6'b111111;
5205 
      12'd3737 :  mem_out_dec = 6'b111111;
5206 
      12'd3738 :  mem_out_dec = 6'b111111;
5207 
      12'd3739 :  mem_out_dec = 6'b111111;
5208 
      12'd3740 :  mem_out_dec = 6'b111111;
5209 
      12'd3741 :  mem_out_dec = 6'b111111;
5210 
      12'd3742 :  mem_out_dec = 6'b111111;
5211 
      12'd3743 :  mem_out_dec = 6'b111111;
5212 
      12'd3744 :  mem_out_dec = 6'b111111;
5213 
      12'd3745 :  mem_out_dec = 6'b111111;
5214 
      12'd3746 :  mem_out_dec = 6'b111111;
5215 
      12'd3747 :  mem_out_dec = 6'b111111;
5216 
      12'd3748 :  mem_out_dec = 6'b111111;
5217 
      12'd3749 :  mem_out_dec = 6'b111111;
5218 
      12'd3750 :  mem_out_dec = 6'b111111;
5219 
      12'd3751 :  mem_out_dec = 6'b111111;
5220 
      12'd3752 :  mem_out_dec = 6'b111111;
5221 
      12'd3753 :  mem_out_dec = 6'b111111;
5222 
      12'd3754 :  mem_out_dec = 6'b111111;
5223 
      12'd3755 :  mem_out_dec = 6'b111111;
5224 
      12'd3756 :  mem_out_dec = 6'b111111;
5225 
      12'd3757 :  mem_out_dec = 6'b111111;
5226 
      12'd3758 :  mem_out_dec = 6'b111111;
5227 
      12'd3759 :  mem_out_dec = 6'b111111;
5228 
      12'd3760 :  mem_out_dec = 6'b111111;
5229 
      12'd3761 :  mem_out_dec = 6'b111111;
5230 
      12'd3762 :  mem_out_dec = 6'b111111;
5231 
      12'd3763 :  mem_out_dec = 6'b111111;
5232 
      12'd3764 :  mem_out_dec = 6'b111111;
5233 
      12'd3765 :  mem_out_dec = 6'b111111;
5234 
      12'd3766 :  mem_out_dec = 6'b111111;
5235 
      12'd3767 :  mem_out_dec = 6'b111111;
5236 
      12'd3768 :  mem_out_dec = 6'b111111;
5237 
      12'd3769 :  mem_out_dec = 6'b111111;
5238 
      12'd3770 :  mem_out_dec = 6'b111111;
5239 
      12'd3771 :  mem_out_dec = 6'b111111;
5240 
      12'd3772 :  mem_out_dec = 6'b111111;
5241 
      12'd3773 :  mem_out_dec = 6'b111111;
5242 
      12'd3774 :  mem_out_dec = 6'b111111;
5243 
      12'd3775 :  mem_out_dec = 6'b111111;
5244 
      12'd3776 :  mem_out_dec = 6'b111111;
5245 
      12'd3777 :  mem_out_dec = 6'b111111;
5246 
      12'd3778 :  mem_out_dec = 6'b111111;
5247 
      12'd3779 :  mem_out_dec = 6'b111111;
5248 
      12'd3780 :  mem_out_dec = 6'b111111;
5249 
      12'd3781 :  mem_out_dec = 6'b111111;
5250 
      12'd3782 :  mem_out_dec = 6'b111111;
5251 
      12'd3783 :  mem_out_dec = 6'b111111;
5252 
      12'd3784 :  mem_out_dec = 6'b111111;
5253 
      12'd3785 :  mem_out_dec = 6'b111111;
5254 
      12'd3786 :  mem_out_dec = 6'b111111;
5255 
      12'd3787 :  mem_out_dec = 6'b111111;
5256 
      12'd3788 :  mem_out_dec = 6'b111111;
5257 
      12'd3789 :  mem_out_dec = 6'b111111;
5258 
      12'd3790 :  mem_out_dec = 6'b111111;
5259 
      12'd3791 :  mem_out_dec = 6'b111111;
5260 
      12'd3792 :  mem_out_dec = 6'b111111;
5261 
      12'd3793 :  mem_out_dec = 6'b111111;
5262 
      12'd3794 :  mem_out_dec = 6'b111111;
5263 
      12'd3795 :  mem_out_dec = 6'b111111;
5264 
      12'd3796 :  mem_out_dec = 6'b111111;
5265 
      12'd3797 :  mem_out_dec = 6'b111111;
5266 
      12'd3798 :  mem_out_dec = 6'b111111;
5267 
      12'd3799 :  mem_out_dec = 6'b111111;
5268 
      12'd3800 :  mem_out_dec = 6'b111111;
5269 
      12'd3801 :  mem_out_dec = 6'b111111;
5270 
      12'd3802 :  mem_out_dec = 6'b111111;
5271 
      12'd3803 :  mem_out_dec = 6'b111111;
5272 
      12'd3804 :  mem_out_dec = 6'b111111;
5273 
      12'd3805 :  mem_out_dec = 6'b111111;
5274 
      12'd3806 :  mem_out_dec = 6'b111111;
5275 
      12'd3807 :  mem_out_dec = 6'b111111;
5276 
      12'd3808 :  mem_out_dec = 6'b111111;
5277 
      12'd3809 :  mem_out_dec = 6'b111111;
5278 
      12'd3810 :  mem_out_dec = 6'b111111;
5279 
      12'd3811 :  mem_out_dec = 6'b111111;
5280 
      12'd3812 :  mem_out_dec = 6'b111111;
5281 
      12'd3813 :  mem_out_dec = 6'b111111;
5282 
      12'd3814 :  mem_out_dec = 6'b111111;
5283 
      12'd3815 :  mem_out_dec = 6'b111111;
5284 
      12'd3816 :  mem_out_dec = 6'b111111;
5285 
      12'd3817 :  mem_out_dec = 6'b111111;
5286 
      12'd3818 :  mem_out_dec = 6'b111111;
5287 
      12'd3819 :  mem_out_dec = 6'b111111;
5288 
      12'd3820 :  mem_out_dec = 6'b111111;
5289 
      12'd3821 :  mem_out_dec = 6'b111111;
5290 
      12'd3822 :  mem_out_dec = 6'b111111;
5291 
      12'd3823 :  mem_out_dec = 6'b111111;
5292 
      12'd3824 :  mem_out_dec = 6'b111111;
5293 
      12'd3825 :  mem_out_dec = 6'b111111;
5294 
      12'd3826 :  mem_out_dec = 6'b111111;
5295 
      12'd3827 :  mem_out_dec = 6'b111111;
5296 
      12'd3828 :  mem_out_dec = 6'b111111;
5297 
      12'd3829 :  mem_out_dec = 6'b111111;
5298 
      12'd3830 :  mem_out_dec = 6'b111111;
5299 
      12'd3831 :  mem_out_dec = 6'b111111;
5300 
      12'd3832 :  mem_out_dec = 6'b111111;
5301 
      12'd3833 :  mem_out_dec = 6'b111111;
5302 
      12'd3834 :  mem_out_dec = 6'b111111;
5303 
      12'd3835 :  mem_out_dec = 6'b111111;
5304 
      12'd3836 :  mem_out_dec = 6'b111111;
5305 
      12'd3837 :  mem_out_dec = 6'b111111;
5306 
      12'd3838 :  mem_out_dec = 6'b111111;
5307 
      12'd3839 :  mem_out_dec = 6'b111111;
5308 
      12'd3840 :  mem_out_dec = 6'b111111;
5309 
      12'd3841 :  mem_out_dec = 6'b111111;
5310 
      12'd3842 :  mem_out_dec = 6'b111111;
5311 
      12'd3843 :  mem_out_dec = 6'b111111;
5312 
      12'd3844 :  mem_out_dec = 6'b111111;
5313 
      12'd3845 :  mem_out_dec = 6'b111111;
5314 
      12'd3846 :  mem_out_dec = 6'b111111;
5315 
      12'd3847 :  mem_out_dec = 6'b111111;
5316 
      12'd3848 :  mem_out_dec = 6'b111111;
5317 
      12'd3849 :  mem_out_dec = 6'b111111;
5318 
      12'd3850 :  mem_out_dec = 6'b111111;
5319 
      12'd3851 :  mem_out_dec = 6'b111111;
5320 
      12'd3852 :  mem_out_dec = 6'b111111;
5321 
      12'd3853 :  mem_out_dec = 6'b111111;
5322 
      12'd3854 :  mem_out_dec = 6'b111111;
5323 
      12'd3855 :  mem_out_dec = 6'b111111;
5324 
      12'd3856 :  mem_out_dec = 6'b111111;
5325 
      12'd3857 :  mem_out_dec = 6'b111111;
5326 
      12'd3858 :  mem_out_dec = 6'b111111;
5327 
      12'd3859 :  mem_out_dec = 6'b111111;
5328 
      12'd3860 :  mem_out_dec = 6'b111111;
5329 
      12'd3861 :  mem_out_dec = 6'b111111;
5330 
      12'd3862 :  mem_out_dec = 6'b111111;
5331 
      12'd3863 :  mem_out_dec = 6'b111111;
5332 
      12'd3864 :  mem_out_dec = 6'b111111;
5333 
      12'd3865 :  mem_out_dec = 6'b111111;
5334 
      12'd3866 :  mem_out_dec = 6'b111111;
5335 
      12'd3867 :  mem_out_dec = 6'b111111;
5336 
      12'd3868 :  mem_out_dec = 6'b111111;
5337 
      12'd3869 :  mem_out_dec = 6'b111111;
5338 
      12'd3870 :  mem_out_dec = 6'b111111;
5339 
      12'd3871 :  mem_out_dec = 6'b111111;
5340 
      12'd3872 :  mem_out_dec = 6'b111111;
5341 
      12'd3873 :  mem_out_dec = 6'b111111;
5342 
      12'd3874 :  mem_out_dec = 6'b111111;
5343 
      12'd3875 :  mem_out_dec = 6'b111111;
5344 
      12'd3876 :  mem_out_dec = 6'b111111;
5345 
      12'd3877 :  mem_out_dec = 6'b111111;
5346 
      12'd3878 :  mem_out_dec = 6'b111111;
5347 
      12'd3879 :  mem_out_dec = 6'b111111;
5348 
      12'd3880 :  mem_out_dec = 6'b111111;
5349 
      12'd3881 :  mem_out_dec = 6'b111111;
5350 
      12'd3882 :  mem_out_dec = 6'b111111;
5351 
      12'd3883 :  mem_out_dec = 6'b111111;
5352 
      12'd3884 :  mem_out_dec = 6'b111111;
5353 
      12'd3885 :  mem_out_dec = 6'b111111;
5354 
      12'd3886 :  mem_out_dec = 6'b111111;
5355 
      12'd3887 :  mem_out_dec = 6'b111111;
5356 
      12'd3888 :  mem_out_dec = 6'b111111;
5357 
      12'd3889 :  mem_out_dec = 6'b111111;
5358 
      12'd3890 :  mem_out_dec = 6'b111111;
5359 
      12'd3891 :  mem_out_dec = 6'b111111;
5360 
      12'd3892 :  mem_out_dec = 6'b111111;
5361 
      12'd3893 :  mem_out_dec = 6'b111111;
5362 
      12'd3894 :  mem_out_dec = 6'b111111;
5363 
      12'd3895 :  mem_out_dec = 6'b111111;
5364 
      12'd3896 :  mem_out_dec = 6'b111111;
5365 
      12'd3897 :  mem_out_dec = 6'b111111;
5366 
      12'd3898 :  mem_out_dec = 6'b111111;
5367 
      12'd3899 :  mem_out_dec = 6'b111111;
5368 
      12'd3900 :  mem_out_dec = 6'b111111;
5369 
      12'd3901 :  mem_out_dec = 6'b111111;
5370 
      12'd3902 :  mem_out_dec = 6'b111111;
5371 
      12'd3903 :  mem_out_dec = 6'b111111;
5372 
      12'd3904 :  mem_out_dec = 6'b111111;
5373 
      12'd3905 :  mem_out_dec = 6'b111111;
5374 
      12'd3906 :  mem_out_dec = 6'b111111;
5375 
      12'd3907 :  mem_out_dec = 6'b111111;
5376 
      12'd3908 :  mem_out_dec = 6'b111111;
5377 
      12'd3909 :  mem_out_dec = 6'b111111;
5378 
      12'd3910 :  mem_out_dec = 6'b111111;
5379 
      12'd3911 :  mem_out_dec = 6'b111111;
5380 
      12'd3912 :  mem_out_dec = 6'b111111;
5381 
      12'd3913 :  mem_out_dec = 6'b111111;
5382 
      12'd3914 :  mem_out_dec = 6'b111111;
5383 
      12'd3915 :  mem_out_dec = 6'b111111;
5384 
      12'd3916 :  mem_out_dec = 6'b111111;
5385 
      12'd3917 :  mem_out_dec = 6'b111111;
5386 
      12'd3918 :  mem_out_dec = 6'b111111;
5387 
      12'd3919 :  mem_out_dec = 6'b111111;
5388 
      12'd3920 :  mem_out_dec = 6'b111111;
5389 
      12'd3921 :  mem_out_dec = 6'b111111;
5390 
      12'd3922 :  mem_out_dec = 6'b111111;
5391 
      12'd3923 :  mem_out_dec = 6'b111111;
5392 
      12'd3924 :  mem_out_dec = 6'b111111;
5393 
      12'd3925 :  mem_out_dec = 6'b111111;
5394 
      12'd3926 :  mem_out_dec = 6'b111111;
5395 
      12'd3927 :  mem_out_dec = 6'b111111;
5396 
      12'd3928 :  mem_out_dec = 6'b111111;
5397 
      12'd3929 :  mem_out_dec = 6'b111111;
5398 
      12'd3930 :  mem_out_dec = 6'b111111;
5399 
      12'd3931 :  mem_out_dec = 6'b111111;
5400 
      12'd3932 :  mem_out_dec = 6'b111111;
5401 
      12'd3933 :  mem_out_dec = 6'b111111;
5402 
      12'd3934 :  mem_out_dec = 6'b111111;
5403 
      12'd3935 :  mem_out_dec = 6'b111111;
5404 
      12'd3936 :  mem_out_dec = 6'b111111;
5405 
      12'd3937 :  mem_out_dec = 6'b111111;
5406 
      12'd3938 :  mem_out_dec = 6'b111111;
5407 
      12'd3939 :  mem_out_dec = 6'b111111;
5408 
      12'd3940 :  mem_out_dec = 6'b111111;
5409 
      12'd3941 :  mem_out_dec = 6'b111111;
5410 
      12'd3942 :  mem_out_dec = 6'b111111;
5411 
      12'd3943 :  mem_out_dec = 6'b111111;
5412 
      12'd3944 :  mem_out_dec = 6'b111111;
5413 
      12'd3945 :  mem_out_dec = 6'b111111;
5414 
      12'd3946 :  mem_out_dec = 6'b111111;
5415 
      12'd3947 :  mem_out_dec = 6'b111111;
5416 
      12'd3948 :  mem_out_dec = 6'b111111;
5417 
      12'd3949 :  mem_out_dec = 6'b111111;
5418 
      12'd3950 :  mem_out_dec = 6'b111111;
5419 
      12'd3951 :  mem_out_dec = 6'b111111;
5420 
      12'd3952 :  mem_out_dec = 6'b111111;
5421 
      12'd3953 :  mem_out_dec = 6'b111111;
5422 
      12'd3954 :  mem_out_dec = 6'b111111;
5423 
      12'd3955 :  mem_out_dec = 6'b111111;
5424 
      12'd3956 :  mem_out_dec = 6'b111111;
5425 
      12'd3957 :  mem_out_dec = 6'b111111;
5426 
      12'd3958 :  mem_out_dec = 6'b111111;
5427 
      12'd3959 :  mem_out_dec = 6'b111111;
5428 
      12'd3960 :  mem_out_dec = 6'b111111;
5429 
      12'd3961 :  mem_out_dec = 6'b111111;
5430 
      12'd3962 :  mem_out_dec = 6'b111111;
5431 
      12'd3963 :  mem_out_dec = 6'b111111;
5432 
      12'd3964 :  mem_out_dec = 6'b111111;
5433 
      12'd3965 :  mem_out_dec = 6'b111111;
5434 
      12'd3966 :  mem_out_dec = 6'b111111;
5435 
      12'd3967 :  mem_out_dec = 6'b111111;
5436 
      12'd3968 :  mem_out_dec = 6'b111111;
5437 
      12'd3969 :  mem_out_dec = 6'b111111;
5438 
      12'd3970 :  mem_out_dec = 6'b111111;
5439 
      12'd3971 :  mem_out_dec = 6'b111111;
5440 
      12'd3972 :  mem_out_dec = 6'b111111;
5441 
      12'd3973 :  mem_out_dec = 6'b111111;
5442 
      12'd3974 :  mem_out_dec = 6'b111111;
5443 
      12'd3975 :  mem_out_dec = 6'b111111;
5444 
      12'd3976 :  mem_out_dec = 6'b111111;
5445 
      12'd3977 :  mem_out_dec = 6'b111111;
5446 
      12'd3978 :  mem_out_dec = 6'b111111;
5447 
      12'd3979 :  mem_out_dec = 6'b111111;
5448 
      12'd3980 :  mem_out_dec = 6'b111111;
5449 
      12'd3981 :  mem_out_dec = 6'b111111;
5450 
      12'd3982 :  mem_out_dec = 6'b111111;
5451 
      12'd3983 :  mem_out_dec = 6'b111111;
5452 
      12'd3984 :  mem_out_dec = 6'b111111;
5453 
      12'd3985 :  mem_out_dec = 6'b111111;
5454 
      12'd3986 :  mem_out_dec = 6'b111111;
5455 
      12'd3987 :  mem_out_dec = 6'b111111;
5456 
      12'd3988 :  mem_out_dec = 6'b111111;
5457 
      12'd3989 :  mem_out_dec = 6'b111111;
5458 
      12'd3990 :  mem_out_dec = 6'b111111;
5459 
      12'd3991 :  mem_out_dec = 6'b111111;
5460 
      12'd3992 :  mem_out_dec = 6'b111111;
5461 
      12'd3993 :  mem_out_dec = 6'b111111;
5462 
      12'd3994 :  mem_out_dec = 6'b111111;
5463 
      12'd3995 :  mem_out_dec = 6'b111111;
5464 
      12'd3996 :  mem_out_dec = 6'b111111;
5465 
      12'd3997 :  mem_out_dec = 6'b111111;
5466 
      12'd3998 :  mem_out_dec = 6'b111111;
5467 
      12'd3999 :  mem_out_dec = 6'b111111;
5468 
      12'd4000 :  mem_out_dec = 6'b111111;
5469 
      12'd4001 :  mem_out_dec = 6'b111111;
5470 
      12'd4002 :  mem_out_dec = 6'b111111;
5471 
      12'd4003 :  mem_out_dec = 6'b111111;
5472 
      12'd4004 :  mem_out_dec = 6'b111111;
5473 
      12'd4005 :  mem_out_dec = 6'b111111;
5474 
      12'd4006 :  mem_out_dec = 6'b111111;
5475 
      12'd4007 :  mem_out_dec = 6'b111111;
5476 
      12'd4008 :  mem_out_dec = 6'b111111;
5477 
      12'd4009 :  mem_out_dec = 6'b111111;
5478 
      12'd4010 :  mem_out_dec = 6'b111111;
5479 
      12'd4011 :  mem_out_dec = 6'b111111;
5480 
      12'd4012 :  mem_out_dec = 6'b111111;
5481 
      12'd4013 :  mem_out_dec = 6'b111111;
5482 
      12'd4014 :  mem_out_dec = 6'b111111;
5483 
      12'd4015 :  mem_out_dec = 6'b111111;
5484 
      12'd4016 :  mem_out_dec = 6'b111111;
5485 
      12'd4017 :  mem_out_dec = 6'b111111;
5486 
      12'd4018 :  mem_out_dec = 6'b111111;
5487 
      12'd4019 :  mem_out_dec = 6'b111111;
5488 
      12'd4020 :  mem_out_dec = 6'b111111;
5489 
      12'd4021 :  mem_out_dec = 6'b111111;
5490 
      12'd4022 :  mem_out_dec = 6'b111111;
5491 
      12'd4023 :  mem_out_dec = 6'b111111;
5492 
      12'd4024 :  mem_out_dec = 6'b111111;
5493 
      12'd4025 :  mem_out_dec = 6'b111111;
5494 
      12'd4026 :  mem_out_dec = 6'b111111;
5495 
      12'd4027 :  mem_out_dec = 6'b111111;
5496 
      12'd4028 :  mem_out_dec = 6'b111111;
5497 
      12'd4029 :  mem_out_dec = 6'b111111;
5498 
      12'd4030 :  mem_out_dec = 6'b111111;
5499 
      12'd4031 :  mem_out_dec = 6'b111111;
5500 
      12'd4032 :  mem_out_dec = 6'b111111;
5501 
      12'd4033 :  mem_out_dec = 6'b111111;
5502 
      12'd4034 :  mem_out_dec = 6'b111111;
5503 
      12'd4035 :  mem_out_dec = 6'b111111;
5504 
      12'd4036 :  mem_out_dec = 6'b111111;
5505 
      12'd4037 :  mem_out_dec = 6'b111111;
5506 
      12'd4038 :  mem_out_dec = 6'b111111;
5507 
      12'd4039 :  mem_out_dec = 6'b111111;
5508 
      12'd4040 :  mem_out_dec = 6'b111111;
5509 
      12'd4041 :  mem_out_dec = 6'b111111;
5510 
      12'd4042 :  mem_out_dec = 6'b111111;
5511 
      12'd4043 :  mem_out_dec = 6'b111111;
5512 
      12'd4044 :  mem_out_dec = 6'b111111;
5513 
      12'd4045 :  mem_out_dec = 6'b111111;
5514 
      12'd4046 :  mem_out_dec = 6'b111111;
5515 
      12'd4047 :  mem_out_dec = 6'b111111;
5516 
      12'd4048 :  mem_out_dec = 6'b111111;
5517 
      12'd4049 :  mem_out_dec = 6'b111111;
5518 
      12'd4050 :  mem_out_dec = 6'b111111;
5519 
      12'd4051 :  mem_out_dec = 6'b111111;
5520 
      12'd4052 :  mem_out_dec = 6'b111111;
5521 
      12'd4053 :  mem_out_dec = 6'b111111;
5522 
      12'd4054 :  mem_out_dec = 6'b111111;
5523 
      12'd4055 :  mem_out_dec = 6'b111111;
5524 
      12'd4056 :  mem_out_dec = 6'b111111;
5525 
      12'd4057 :  mem_out_dec = 6'b111111;
5526 
      12'd4058 :  mem_out_dec = 6'b111111;
5527 
      12'd4059 :  mem_out_dec = 6'b111111;
5528 
      12'd4060 :  mem_out_dec = 6'b111111;
5529 
      12'd4061 :  mem_out_dec = 6'b111111;
5530 
      12'd4062 :  mem_out_dec = 6'b111111;
5531 
      12'd4063 :  mem_out_dec = 6'b111111;
5532 
      12'd4064 :  mem_out_dec = 6'b111111;
5533 
      12'd4065 :  mem_out_dec = 6'b111111;
5534 
      12'd4066 :  mem_out_dec = 6'b111111;
5535 
      12'd4067 :  mem_out_dec = 6'b111111;
5536 
      12'd4068 :  mem_out_dec = 6'b111111;
5537 
      12'd4069 :  mem_out_dec = 6'b111111;
5538 
      12'd4070 :  mem_out_dec = 6'b111111;
5539 
      12'd4071 :  mem_out_dec = 6'b111111;
5540 
      12'd4072 :  mem_out_dec = 6'b111111;
5541 
      12'd4073 :  mem_out_dec = 6'b111111;
5542 
      12'd4074 :  mem_out_dec = 6'b111111;
5543 
      12'd4075 :  mem_out_dec = 6'b111111;
5544 
      12'd4076 :  mem_out_dec = 6'b111111;
5545 
      12'd4077 :  mem_out_dec = 6'b111111;
5546 
      12'd4078 :  mem_out_dec = 6'b111111;
5547 
      12'd4079 :  mem_out_dec = 6'b111111;
5548 
      12'd4080 :  mem_out_dec = 6'b111111;
5549 
      12'd4081 :  mem_out_dec = 6'b111111;
5550 
      12'd4082 :  mem_out_dec = 6'b111111;
5551 
      12'd4083 :  mem_out_dec = 6'b111111;
5552 
      12'd4084 :  mem_out_dec = 6'b111111;
5553 
      12'd4085 :  mem_out_dec = 6'b111111;
5554 
      12'd4086 :  mem_out_dec = 6'b111111;
5555 
      12'd4087 :  mem_out_dec = 6'b111111;
5556 
      12'd4088 :  mem_out_dec = 6'b111111;
5557 
      12'd4089 :  mem_out_dec = 6'b111111;
5558 
      12'd4090 :  mem_out_dec = 6'b111111;
5559 
      12'd4091 :  mem_out_dec = 6'b111111;
5560 
      12'd4092 :  mem_out_dec = 6'b111111;
5561 
      12'd4093 :  mem_out_dec = 6'b111111;
5562 
      12'd4094 :  mem_out_dec = 6'b111111;
5563 
      12'd4095 :  mem_out_dec = 6'b111111;
5564 
    endcase
5565 
  end
5566 
 
5567 
  always @ (posedge clk) begin
5568 
    dec_cnt <= #TCQ mem_out_dec;
5569 
  end
5570 
endmodule

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