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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.13/] [memfifo.srcs/] [sources_1/] [ip/] [mig_7series_0/] [mig_7series_0/] [user_design/] [rtl/] [phy/] [mig_7series_v2_3_ddr_phy_top.v] - Blame information for rev 2

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//*****************************************************************************
2 
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
3 
//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
8 
//
9 
// DISCLAIMER
10 
// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
13 
// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
18 
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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//   ____  ____
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//  /   /\/   /
51 
// /___/  \  /    Vendor                : Xilinx
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// \   \   \/     Version               : 2.3
53 
//  \   \         Application           : MIG
54 
//  /   /         Filename              : ddr_phy_top.v
55 
// /___/   /\     Date Last Modified    : $date$
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// \   \  /  \    Date Created          : Aug 03 2009
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//  \___\/\___\
58 
//
59 
//Device            : 7 Series
60 
//Design Name       : DDR3 SDRAM
61 
//Purpose           : Top level memory interface block. Instantiates a clock
62 
//                    and reset generator, the memory controller, the phy and
63 
//                    the user interface blocks.
64 
//Reference         :
65 
//Revision History  :
66 
//*****************************************************************************
67 
 
68 
`timescale 1 ps / 1 ps
69 
 
70 
module mig_7series_v2_3_ddr_phy_top #
71 
  (
72 
   parameter TCQ             = 100,     // Register delay (simulation only)
73 
   parameter DDR3_VDD_OP_VOLT = 135,     // Voltage mode used for DDR3
74 
   parameter AL              = "0",     // Additive Latency option
75 
   parameter BANK_WIDTH      = 3,       // # of bank bits
76 
   parameter BURST_MODE      = "8",     // Burst length
77 
   parameter BURST_TYPE      = "SEQ",   // Burst type
78 
   parameter CA_MIRROR       = "OFF",   // C/A mirror opt for DDR3 dual rank
79 
   parameter CK_WIDTH        = 1,       // # of CK/CK# outputs to memory
80 
   parameter CL              = 5,
81 
   parameter COL_WIDTH       = 12,      // column address width
82 
   parameter CS_WIDTH        = 1,       // # of unique CS outputs
83 
   parameter CKE_WIDTH       = 1,       // # of cke outputs
84 
   parameter CWL             = 5,
85 
   parameter DM_WIDTH        = 8,       // # of DM (data mask)
86 
   parameter DQ_WIDTH        = 64,      // # of DQ (data)
87 
   parameter DQS_CNT_WIDTH   = 3,       // = ceil(log2(DQS_WIDTH))
88 
   parameter DQS_WIDTH       = 8,       // # of DQS (strobe)
89 
   parameter DRAM_TYPE       = "DDR3",
90 
   parameter DRAM_WIDTH      = 8,       // # of DQ per DQS
91 
   parameter MASTER_PHY_CTL  = 0,       // The bank number where master PHY_CONTROL resides
92 
   parameter LP_DDR_CK_WIDTH = 2,
93 
 
94 
   // Hard PHY parameters
95 
   parameter PHYCTL_CMD_FIFO = "FALSE",
96 
   // five fields, one per possible I/O bank, 4 bits in each field,
97 
   // 1 per lane data=1/ctl=0
98 
   parameter DATA_CTL_B0     = 4'hc,
99 
   parameter DATA_CTL_B1     = 4'hf,
100 
   parameter DATA_CTL_B2     = 4'hf,
101 
   parameter DATA_CTL_B3     = 4'hf,
102 
   parameter DATA_CTL_B4     = 4'hf,
103 
   // defines the byte lanes in I/O banks being used in the interface
104 
   // 1- Used, 0- Unused
105 
   parameter BYTE_LANES_B0   = 4'b1111,
106 
   parameter BYTE_LANES_B1   = 4'b0000,
107 
   parameter BYTE_LANES_B2   = 4'b0000,
108 
   parameter BYTE_LANES_B3   = 4'b0000,
109 
   parameter BYTE_LANES_B4   = 4'b0000,
110 
   // defines the bit lanes in I/O banks being used in the interface. Each
111 
   // parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
112 
   parameter PHY_0_BITLANES  = 48'h0000_0000_0000,
113 
   parameter PHY_1_BITLANES  = 48'h0000_0000_0000,
114 
   parameter PHY_2_BITLANES  = 48'h0000_0000_0000,
115 
 
116 
   // control/address/data pin mapping parameters
117 
   parameter CK_BYTE_MAP
118 
     = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
119 
   parameter ADDR_MAP
120 
     = 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
121 
   parameter BANK_MAP   = 36'h000_000_000,
122 
   parameter CAS_MAP    = 12'h000,
123 
   parameter CKE_ODT_BYTE_MAP = 8'h00,
124 
   parameter CKE_MAP    = 96'h000_000_000_000_000_000_000_000,
125 
   parameter ODT_MAP    = 96'h000_000_000_000_000_000_000_000,
126 
   parameter CKE_ODT_AUX = "FALSE",
127 
   parameter CS_MAP     = 120'h000_000_000_000_000_000_000_000_000_000,
128 
   parameter PARITY_MAP = 12'h000,
129 
   parameter RAS_MAP    = 12'h000,
130 
   parameter WE_MAP     = 12'h000,
131 
   parameter DQS_BYTE_MAP
132 
     = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
133 
   parameter DATA0_MAP  = 96'h000_000_000_000_000_000_000_000,
134 
   parameter DATA1_MAP  = 96'h000_000_000_000_000_000_000_000,
135 
   parameter DATA2_MAP  = 96'h000_000_000_000_000_000_000_000,
136 
   parameter DATA3_MAP  = 96'h000_000_000_000_000_000_000_000,
137 
   parameter DATA4_MAP  = 96'h000_000_000_000_000_000_000_000,
138 
   parameter DATA5_MAP  = 96'h000_000_000_000_000_000_000_000,
139 
   parameter DATA6_MAP  = 96'h000_000_000_000_000_000_000_000,
140 
   parameter DATA7_MAP  = 96'h000_000_000_000_000_000_000_000,
141 
   parameter DATA8_MAP  = 96'h000_000_000_000_000_000_000_000,
142 
   parameter DATA9_MAP  = 96'h000_000_000_000_000_000_000_000,
143 
   parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
144 
   parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
145 
   parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
146 
   parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
147 
   parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
148 
   parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
149 
   parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
150 
   parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
151 
   parameter MASK0_MAP  = 108'h000_000_000_000_000_000_000_000_000,
152 
   parameter MASK1_MAP  = 108'h000_000_000_000_000_000_000_000_000,
153 
 
154 
   // This parameter must be set based on memory clock frequency
155 
   // It must be set to 4 for frequencies above 533 MHz?? (undecided)
156 
   // and set to 2 for 533 MHz and below
157 
   parameter PRE_REV3ES      = "OFF",   // Delay O/Ps using Phaser_Out fine dly
158 
   parameter nCK_PER_CLK     = 2,       // # of memory CKs per fabric CLK
159 
   parameter nCS_PER_RANK    = 1,       // # of unique CS outputs per rank
160 
   parameter ADDR_CMD_MODE   = "1T",    // ADDR/CTRL timing: "2T", "1T"
161 
   parameter BANK_TYPE       = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
162 
   parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
163 
   parameter DATA_IO_IDLE_PWRDWN = "ON",  // "ON" or "OFF"
164 
   parameter IODELAY_GRP     = "IODELAY_MIG",
165 
   parameter FPGA_SPEED_GRADE = 1,
166 
   parameter IBUF_LPWR_MODE  = "OFF",   // input buffer low power option
167 
   parameter OUTPUT_DRV      = "HIGH",  // to calib_top
168 
   parameter REG_CTRL        = "OFF",   // to calib_top
169 
   parameter RTT_NOM         = "60",    // to calib_top
170 
   parameter RTT_WR          = "120",   // to calib_top
171 
   parameter tCK             = 2500,    // pS
172 
   parameter tRFC            = 110000,  // pS
173 
   parameter tREFI           = 7800000, // pS
174 
   parameter DDR2_DQSN_ENABLE = "YES",  // Enable differential DQS for DDR2
175 
   parameter WRLVL           = "OFF",   // to calib_top
176 
   parameter DEBUG_PORT      = "OFF",   // to calib_top
177 
   parameter RANKS           = 4,
178 
   parameter ODT_WIDTH       = 1,
179 
   parameter ROW_WIDTH       = 16,      // DRAM address bus width
180 
   parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
181 
   // calibration Address. The address given below will be used for calibration
182 
   // read and write operations.
183 
   parameter CALIB_ROW_ADD   = 16'h0000,// Calibration row address
184 
   parameter CALIB_COL_ADD   = 12'h000, // Calibration column address
185 
   parameter CALIB_BA_ADD    = 3'h0,    // Calibration bank address
186 
   // Simulation /debug options
187 
   parameter SIM_BYPASS_INIT_CAL = "OFF",
188 
                                        // Parameter used to force skipping
189 
                                        // or abbreviation of initialization
190 
                                        // and calibration. Overrides
191 
                                        // SIM_INIT_OPTION, SIM_CAL_OPTION,
192 
                                        // and disables various other blocks
193 
   //parameter SIM_INIT_OPTION = "SKIP_PU_DLY", // Skip various init steps
194 
   //parameter SIM_CAL_OPTION  = "NONE",        // Skip various calib steps
195 
   parameter REFCLK_FREQ     = 200.0,         // IODELAY ref clock freq (MHz)
196 
   parameter USE_CS_PORT     = 1,             // Support chip select output
197 
   parameter USE_DM_PORT     = 1,             // Support data mask output
198 
   parameter USE_ODT_PORT    = 1,             // Support ODT output
199 
   parameter RD_PATH_REG     = 0,              // optional registers in the read path
200 
                                              // to MC for timing improvement.
201 
                                              // =1 enabled, = 0 disabled
202 
   parameter IDELAY_ADJ       = "ON",          //ON : IDELAY-1, OFF: No change
203 
   parameter FINE_PER_BIT     = "ON",          //ON : Use per bit calib for complex rdlvl
204 
   parameter CENTER_COMP_MODE = "ON",        //ON: use PI stg2 tap compensation
205 
   parameter PI_VAL_ADJ       = "ON",        //ON: PI stg2 tap -1 for centering
206 
   parameter TAPSPERKCLK      = 56,
207 
   parameter POC_USE_METASTABLE_SAMP = "FALSE"
208 
  )
209 
  (
210 
   input                     clk,            // Fabric logic clock
211 
                                             // To MC, calib_top, hard PHY
212 
   input                     clk_ref,        // Idelay_ctrl reference clock
213 
                                             // To hard PHY (external source)
214 
   input                     freq_refclk,    // To hard PHY for Phasers
215 
   input                     mem_refclk,     // Memory clock to hard PHY
216 
   input                     pll_lock,       // System PLL lock signal
217 
   input                     sync_pulse,     // 1/N sync pulse used to synchronize all PHASERS
218 
   input                     mmcm_ps_clk,    // Phase shift clock for oclk stg3 centering
219 
   input                     poc_sample_pd,  // Tell POC how to avoid metastability.
220 
 
221 
   input                     error,          // Support for TG error detect
222 
   output                    rst_tg_mc,      // Support for TG error detect
223 
 
224 
   input  [11:0]             device_temp,
225 
   input                     tempmon_sample_en,
226 
 
227 
   input                     dbg_sel_pi_incdec,
228 
   input                     dbg_sel_po_incdec,
229 
   input [DQS_CNT_WIDTH:0]   dbg_byte_sel,
230 
   input                     dbg_pi_f_inc,
231 
   input                     dbg_pi_f_dec,
232 
   input                     dbg_po_f_inc,
233 
   input                     dbg_po_f_stg23_sel,
234 
   input                     dbg_po_f_dec,
235 
   input                     dbg_idel_down_all,
236 
   input                     dbg_idel_down_cpt,
237 
   input                     dbg_idel_up_all,
238 
   input                     dbg_idel_up_cpt,
239 
   input                     dbg_sel_all_idel_cpt,
240 
   input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
241 
   input                     rst,
242 
   input                     iddr_rst,
243 
   input [7:0]               slot_0_present,
244 
   input [7:0]               slot_1_present,
245 
   // From MC
246 
   input [nCK_PER_CLK-1:0]   mc_ras_n,
247 
   input [nCK_PER_CLK-1:0]   mc_cas_n,
248 
   input [nCK_PER_CLK-1:0]   mc_we_n,
249 
   input [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address,
250 
   input [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank,
251 
   input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n,
252 
   input                     mc_reset_n,
253 
   input [1:0]                mc_odt,
254 
   input [nCK_PER_CLK-1:0]   mc_cke,
255 
   // AUX - For ODT and CKE assertion during reads and writes
256 
   input [3:0]               mc_aux_out0,
257 
   input [3:0]               mc_aux_out1,
258 
   input                     mc_cmd_wren,
259 
   input                     mc_ctl_wren,
260 
   input [2:0]               mc_cmd,
261 
   input [1:0]               mc_cas_slot,
262 
   input [5:0]               mc_data_offset,
263 
   input [5:0]               mc_data_offset_1,
264 
   input [5:0]               mc_data_offset_2,
265 
   input [1:0]               mc_rank_cnt,
266 
   // Write
267 
   input                     mc_wrdata_en,
268 
   input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata,
269 
   input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mc_wrdata_mask,
270 
   input                     idle,
271 
   // DDR bus signals
272 
   output [ROW_WIDTH-1:0]              ddr_addr,
273 
   output [BANK_WIDTH-1:0]             ddr_ba,
274 
   output                              ddr_cas_n,
275 
   output [CK_WIDTH-1:0]               ddr_ck_n,
276 
   output [CK_WIDTH-1:0]               ddr_ck,
277 
   output [CKE_WIDTH-1:0]              ddr_cke,
278 
   output [CS_WIDTH*nCS_PER_RANK-1:0]  ddr_cs_n,
279 
   output [DM_WIDTH-1:0]               ddr_dm,
280 
   output [ODT_WIDTH-1:0]              ddr_odt,
281 
   output                              ddr_ras_n,
282 
   output                              ddr_reset_n,
283 
   output                              ddr_parity,
284 
   output                              ddr_we_n,
285 
   inout [DQ_WIDTH-1:0]                ddr_dq,
286 
   inout [DQS_WIDTH-1:0]               ddr_dqs_n,
287 
   inout [DQS_WIDTH-1:0]               ddr_dqs,
288 
 
289 
   //phase shift clock control
290 
   output                              psen,
291 
   output                              psincdec,
292 
   input                               psdone,
293 
   // Debug Port Outputs
294 
   output [255:0]                      dbg_calib_top,
295 
   output [6*DQS_WIDTH*RANKS-1:0]      dbg_cpt_first_edge_cnt,
296 
   output [6*DQS_WIDTH*RANKS-1:0]      dbg_cpt_second_edge_cnt,
297 
   output [6*DQS_WIDTH*RANKS-1:0]      dbg_cpt_tap_cnt,
298 
   output [5*DQS_WIDTH*RANKS-1:0]      dbg_dq_idelay_tap_cnt,
299 
   output [255:0]                      dbg_phy_rdlvl,
300 
   output [99:0]                       dbg_phy_wrcal,
301 
   output [6*DQS_WIDTH-1:0]            dbg_final_po_fine_tap_cnt,
302 
   output [3*DQS_WIDTH-1:0]            dbg_final_po_coarse_tap_cnt,
303 
   output [DQS_WIDTH-1:0]              dbg_rd_data_edge_detect,
304 
   output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
305 
   output                              dbg_rddata_valid,
306 
   output [1:0]                        dbg_rdlvl_done,
307 
   output [1:0]                        dbg_rdlvl_err,
308 
   output [1:0]                        dbg_rdlvl_start,
309 
   output [5:0]                        dbg_tap_cnt_during_wrlvl,
310 
   output                              dbg_wl_edge_detect_valid,
311 
   output                              dbg_wrlvl_done,
312 
   output                              dbg_wrlvl_err,
313 
   output                              dbg_wrlvl_start,
314 
   output [6*DQS_WIDTH-1:0]            dbg_wrlvl_fine_tap_cnt,
315 
   output [3*DQS_WIDTH-1:0]            dbg_wrlvl_coarse_tap_cnt,
316 
   output [255:0]                      dbg_phy_wrlvl,
317 
   output                              dbg_pi_phaselock_start,
318 
   output                              dbg_pi_phaselocked_done,
319 
   output                              dbg_pi_phaselock_err,
320 
   output [11:0]                       dbg_pi_phase_locked_phy4lanes,
321 
   output                              dbg_pi_dqsfound_start,
322 
   output                              dbg_pi_dqsfound_done,
323 
   output                              dbg_pi_dqsfound_err,
324 
   output [11:0]                       dbg_pi_dqs_found_lanes_phy4lanes,
325 
   output                              dbg_wrcal_start,
326 
   output                              dbg_wrcal_done,
327 
   output                              dbg_wrcal_err,
328 
   // FIFO status flags
329 
   output                              phy_mc_ctl_full,
330 
   output                              phy_mc_cmd_full,
331 
   output                              phy_mc_data_full,
332 
   // Calibration status and resultant outputs
333 
   output                              init_calib_complete,
334 
   output                              init_wrcal_complete,
335 
   output [6*RANKS-1:0]                calib_rd_data_offset_0,
336 
   output [6*RANKS-1:0]                calib_rd_data_offset_1,
337 
   output [6*RANKS-1:0]                calib_rd_data_offset_2,
338 
   output                              phy_rddata_valid,
339 
   output [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data,
340 
 
341 
   output                              ref_dll_lock,
342 
   input                               rst_phaser_ref,
343 
   output [6*RANKS-1:0]                dbg_rd_data_offset,
344 
   output [255:0]                      dbg_phy_init,
345 
   output [255:0]                      dbg_prbs_rdlvl,
346 
   output [255:0]                      dbg_dqs_found_cal,
347 
   output [5:0]                        dbg_pi_counter_read_val,
348 
   output [8:0]                        dbg_po_counter_read_val,
349 
   output                              dbg_oclkdelay_calib_start,
350 
   output                              dbg_oclkdelay_calib_done,
351 
   output [255:0]                      dbg_phy_oclkdelay_cal,
352 
   output [DRAM_WIDTH*16 -1:0]         dbg_oclkdelay_rd_data,
353 
   output [6*DQS_WIDTH*RANKS-1:0]      prbs_final_dqs_tap_cnt_r,
354 
   output [6*DQS_WIDTH*RANKS-1:0]      dbg_prbs_first_edge_taps,
355 
   output [6*DQS_WIDTH*RANKS-1:0]      dbg_prbs_second_edge_taps
356 
   );
357 
 
358 
  // Calculate number of slots in the system
359 
  localparam nSLOTS  = 1 + (|SLOT_1_CONFIG ? 1 : 0);
360 
  localparam CLK_PERIOD = tCK * nCK_PER_CLK;
361 
 
362 
  // Parameter used to force skipping or abbreviation of initialization
363 
  // and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
364 
  // disables various other blocks depending on the option selected
365 
  // This option should only be used during simulation. In the case of
366 
  // the "SKIP" option, the testbench used should also not be modeling
367 
  // propagation delays.
368 
  // Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
369 
  //  "NONE"     = options determined by the individual parameter settings
370 
  //  "SIM_FULL" = skip power-up delay. FULL calibration performed without
371 
  //               averaging algorithm turned ON during window detection.
372 
  //  "SKIP"     = skip power-up delay. Skip calibration not yet supported.
373 
  //  "FAST"     = skip power-up delay, and calibrate (read leveling, write
374 
  //               leveling, and phase detector) only using one DQS group, and
375 
  //               apply the results to all other DQS groups.
376 
  localparam SIM_INIT_OPTION
377 
             = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_INIT" :
378 
               ((SIM_BYPASS_INIT_CAL == "FAST") ||
379 
                (SIM_BYPASS_INIT_CAL == "SIM_FULL")) ? "SKIP_PU_DLY" :
380 
                "NONE");
381 
  localparam SIM_CAL_OPTION
382 
             = ((SIM_BYPASS_INIT_CAL == "SKIP") ? "SKIP_CAL" :
383 
                (SIM_BYPASS_INIT_CAL == "FAST") ? "FAST_CAL" :
384 
               ((SIM_BYPASS_INIT_CAL == "SIM_FULL") ||
385 
                (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")) ? "FAST_WIN_DETECT" :
386 
                "NONE");
387 
  localparam WRLVL_W
388 
             = (SIM_BYPASS_INIT_CAL == "SKIP") ? "OFF" : WRLVL;
389 
 
390 
  localparam HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 :
391 
                            (BYTE_LANES_B2 != 0 ? 3 :
392 
                            (BYTE_LANES_B1 != 0  ? 2 : 1))));
393 
 
394 
  localparam HIGHEST_LANE_B0  =  BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 :
395 
                                 BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 :
396 
                                 0;
397 
  localparam HIGHEST_LANE_B1  =  BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 :
398 
                                 BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 :
399 
                                 0;
400 
  localparam HIGHEST_LANE_B2  =  BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 :
401 
                                 BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 :
402 
                                 0;
403 
  localparam HIGHEST_LANE_B3  =  BYTE_LANES_B3[3] ? 4 : BYTE_LANES_B3[2] ? 3 :
404 
                                 BYTE_LANES_B3[1] ? 2 : BYTE_LANES_B3[0] ? 1 :
405 
                                 0;
406 
  localparam HIGHEST_LANE_B4  =  BYTE_LANES_B4[3] ? 4 : BYTE_LANES_B4[2] ? 3 :
407 
                                 BYTE_LANES_B4[1] ? 2 : BYTE_LANES_B4[0] ? 1 :
408 
                                 0;
409 
  localparam HIGHEST_LANE =
410 
             (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) :
411 
             ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) :
412 
              ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8)  :
413 
               ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) :
414 
                HIGHEST_LANE_B0)));
415 
 
416 
  localparam N_CTL_LANES = ((0+(!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) +
417 
                           (0+(!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) +
418 
                           (0+(!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) +
419 
                           (0+(!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) +
420 
                           ((0+(!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) +
421 
                           (0+(!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) +
422 
                           (0+(!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) +
423 
                           (0+(!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) +
424 
                           ((0+(!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) +
425 
                           (0+(!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) +
426 
                           (0+(!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) +
427 
                           (0+(!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) +
428 
                           ((0+(!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) +
429 
                           (0+(!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) +
430 
                           (0+(!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) +
431 
                           (0+(!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) +
432 
                           ((0+(!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) +
433 
                           (0+(!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) +
434 
                           (0+(!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) +
435 
                           (0+(!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]));
436 
 
437 
  // Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
438 
  // This should be the case since the PLL should be placed adjacent
439 
  // to the same IO Bank as Ck/Addr/Cmd and Control
440 
  localparam [2:0] CTL_BANK  = (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0]) |
441 
                                ((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
442 
                                ((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
443 
                                ((!DATA_CTL_B0[3]) & BYTE_LANES_B0[3])) ?
444 
                                3'b000 :
445 
                               (((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0]) |
446 
                                ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
447 
                                ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
448 
                                ((!DATA_CTL_B1[3]) & BYTE_LANES_B1[3])) ?
449 
                                3'b001 :
450 
                               (((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0]) |
451 
                                ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
452 
                                ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
453 
                                ((!DATA_CTL_B2[3]) & BYTE_LANES_B2[3])) ?
454 
                                3'b010 :
455 
                               (((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0]) |
456 
                                ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
457 
                                ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
458 
                                ((!DATA_CTL_B3[3]) & BYTE_LANES_B3[3])) ?
459 
                                3'b011 :
460 
                               (((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0]) |
461 
                                ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]) |
462 
                                ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]) |
463 
                                ((!DATA_CTL_B4[3]) & BYTE_LANES_B4[3])) ?
464 
                                3'b100 : 3'b000;
465 
 
466 
  localparam [7:0] CTL_BYTE_LANE  = (N_CTL_LANES == 4) ? 8'b11_10_01_00 :
467 
                                    ((N_CTL_LANES == 3) &
468 
                                     (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
469 
                                       (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
470 
                                       (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
471 
                                      ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
472 
                                       (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
473 
                                       (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
474 
                                      ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
475 
                                       (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
476 
                                       (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
477 
                                      ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
478 
                                       (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
479 
                                       (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
480 
                                      ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
481 
                                       (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
482 
                                       (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
483 
                                    8'b00_10_01_00 :
484 
                                    ((N_CTL_LANES == 3) &
485 
                                     (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
486 
                                       (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
487 
                                       (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
488 
                                      ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
489 
                                       (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
490 
                                       (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
491 
                                      ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
492 
                                       (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
493 
                                       (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
494 
                                      ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
495 
                                       (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
496 
                                       (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
497 
                                      ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
498 
                                       (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
499 
                                       (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
500 
                                    8'b00_11_01_00 :
501 
                                    ((N_CTL_LANES == 3) &
502 
                                     (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
503 
                                       (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
504 
                                       (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
505 
                                      ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
506 
                                       (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
507 
                                       (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
508 
                                      ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
509 
                                       (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
510 
                                       (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
511 
                                      ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
512 
                                       (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
513 
                                       (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
514 
                                      ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
515 
                                       (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
516 
                                       (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
517 
                                    8'b00_11_10_00 :
518 
                                    ((N_CTL_LANES == 3) &
519 
                                     (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
520 
                                       (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
521 
                                       (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
522 
                                      ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
523 
                                       (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
524 
                                       (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
525 
                                      ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
526 
                                       (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
527 
                                       (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
528 
                                      ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
529 
                                       (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
530 
                                       (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
531 
                                      ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
532 
                                       (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
533 
                                       (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
534 
                                    8'b00_11_10_01 :
535 
                                    ((N_CTL_LANES == 2) &
536 
                                     (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
537 
                                       (!DATA_CTL_B0[1]) & BYTE_LANES_B0[1]) |
538 
                                      ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
539 
                                       (!DATA_CTL_B1[1]) & BYTE_LANES_B1[1]) |
540 
                                      ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
541 
                                       (!DATA_CTL_B2[1]) & BYTE_LANES_B2[1]) |
542 
                                      ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
543 
                                       (!DATA_CTL_B3[1]) & BYTE_LANES_B3[1]) |
544 
                                      ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
545 
                                       (!DATA_CTL_B4[1]) & BYTE_LANES_B4[1]))) ?
546 
                                    8'b00_00_01_00 :
547 
                                    ((N_CTL_LANES == 2) &
548 
                                     (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
549 
                                       (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
550 
                                      ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
551 
                                       (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
552 
                                      ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
553 
                                       (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
554 
                                      ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
555 
                                       (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
556 
                                      ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
557 
                                       (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
558 
                                    8'b00_00_11_00 :
559 
                                    ((N_CTL_LANES == 2) &
560 
                                     (((!DATA_CTL_B0[2]) & BYTE_LANES_B0[2] &
561 
                                       (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
562 
                                      ((!DATA_CTL_B1[2]) & BYTE_LANES_B1[2] &
563 
                                       (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
564 
                                      ((!DATA_CTL_B2[2]) & BYTE_LANES_B2[2] &
565 
                                       (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
566 
                                      ((!DATA_CTL_B3[2]) & BYTE_LANES_B3[2] &
567 
                                       (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
568 
                                      ((!DATA_CTL_B4[2]) & BYTE_LANES_B4[2] &
569 
                                       (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
570 
                                    8'b00_00_11_10 :
571 
                                    ((N_CTL_LANES == 2) &
572 
                                     (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
573 
                                       (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
574 
                                      ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
575 
                                       (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
576 
                                      ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
577 
                                       (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
578 
                                      ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
579 
                                       (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
580 
                                      ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
581 
                                       (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
582 
                                    8'b00_00_10_01 :
583 
                                    ((N_CTL_LANES == 2) &
584 
                                     (((!DATA_CTL_B0[1]) & BYTE_LANES_B0[1] &
585 
                                       (!DATA_CTL_B0[3]) & BYTE_LANES_B0[3]) |
586 
                                      ((!DATA_CTL_B1[1]) & BYTE_LANES_B1[1] &
587 
                                       (!DATA_CTL_B1[3]) & BYTE_LANES_B1[3]) |
588 
                                      ((!DATA_CTL_B2[1]) & BYTE_LANES_B2[1] &
589 
                                       (!DATA_CTL_B2[3]) & BYTE_LANES_B2[3]) |
590 
                                      ((!DATA_CTL_B3[1]) & BYTE_LANES_B3[1] &
591 
                                       (!DATA_CTL_B3[3]) & BYTE_LANES_B3[3]) |
592 
                                      ((!DATA_CTL_B4[1]) & BYTE_LANES_B4[1] &
593 
                                       (!DATA_CTL_B4[3]) & BYTE_LANES_B4[3]))) ?
594 
                                    8'b00_00_11_01 :
595 
                                    ((N_CTL_LANES == 2) &
596 
                                     (((!DATA_CTL_B0[0]) & BYTE_LANES_B0[0] &
597 
                                       (!DATA_CTL_B0[2]) & BYTE_LANES_B0[2]) |
598 
                                      ((!DATA_CTL_B1[0]) & BYTE_LANES_B1[0] &
599 
                                       (!DATA_CTL_B1[2]) & BYTE_LANES_B1[2]) |
600 
                                      ((!DATA_CTL_B2[0]) & BYTE_LANES_B2[0] &
601 
                                       (!DATA_CTL_B2[2]) & BYTE_LANES_B2[2]) |
602 
                                      ((!DATA_CTL_B3[0]) & BYTE_LANES_B3[0] &
603 
                                       (!DATA_CTL_B3[2]) & BYTE_LANES_B3[2]) |
604 
                                      ((!DATA_CTL_B4[0]) & BYTE_LANES_B4[0] &
605 
                                       (!DATA_CTL_B4[2]) & BYTE_LANES_B4[2]))) ?
606 
                                    8'b00_00_10_00 : 8'b11_10_01_00;
607 
 
608 
 
609 
 
610 
 
611 
  wire [HIGHEST_LANE*80-1:0]            phy_din;
612 
  wire [HIGHEST_LANE*80-1:0]            phy_dout;
613 
  wire [(HIGHEST_LANE*12)-1:0]          ddr_cmd_ctl_data;
614 
  wire [(((HIGHEST_LANE+3)/4)*4)-1:0]   aux_out;
615 
  wire [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk;
616 
  wire                                  phy_mc_go;
617 
  wire                                  phy_ctl_full;
618 
  wire                                  phy_cmd_full;
619 
  wire                                  phy_data_full;
620 
  wire                                  phy_pre_data_a_full;
621 
  wire                                  if_empty /* synthesis syn_maxfan = 3 */;
622 
  wire                                  phy_write_calib;
623 
  wire                                  phy_read_calib;
624 
  wire [HIGHEST_BANK-1:0]               rst_stg1_cal;
625 
  wire [5:0]                            calib_sel;
626 
  wire                                  calib_in_common /* synthesis syn_maxfan = 10 */;
627 
  wire [HIGHEST_BANK-1:0]               calib_zero_inputs;
628 
  wire [HIGHEST_BANK-1:0]               calib_zero_ctrl;
629 
  wire                                  pi_phase_locked;
630 
  wire                                  pi_phase_locked_all;
631 
  wire                                  pi_found_dqs;
632 
  wire                                  pi_dqs_found_all;
633 
  wire                                  pi_dqs_out_of_range;
634 
  wire                                  pi_enstg2_f;
635 
  wire                                  pi_stg2_fincdec;
636 
  wire                                  pi_stg2_load;
637 
  wire [5:0]                            pi_stg2_reg_l;
638 
  wire                                  idelay_ce;
639 
  wire                                  idelay_inc;
640 
  wire                                  idelay_ld;
641 
  wire [2:0]                            po_sel_stg2stg3;
642 
  wire [2:0]                            po_stg2_cincdec;
643 
  wire [2:0]                            po_enstg2_c;
644 
  wire [2:0]                            po_stg2_fincdec;
645 
  wire [2:0]                            po_enstg2_f;
646 
  wire [8:0]                            po_counter_read_val;
647 
  wire [5:0]                            pi_counter_read_val;
648 
  wire [2*nCK_PER_CLK*DQ_WIDTH-1:0]     phy_wrdata;
649 
  reg [nCK_PER_CLK-1:0]                 parity;
650 
  wire [nCK_PER_CLK*ROW_WIDTH-1:0]      phy_address;
651 
  wire [nCK_PER_CLK*BANK_WIDTH-1:0]     phy_bank;
652 
  wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n;
653 
  wire [nCK_PER_CLK-1:0]                phy_ras_n;
654 
  wire [nCK_PER_CLK-1:0]                phy_cas_n;
655 
  wire [nCK_PER_CLK-1:0]                phy_we_n;
656 
  wire                                  phy_reset_n;
657 
  wire [3:0]                            calib_aux_out;
658 
  wire [nCK_PER_CLK-1:0]                calib_cke;
659 
  wire [1:0]                            calib_odt;
660 
  wire                                  calib_ctl_wren;
661 
  wire                                  calib_cmd_wren;
662 
  wire                                  calib_wrdata_en;
663 
  wire [2:0]                            calib_cmd;
664 
  wire [1:0]                            calib_seq;
665 
  wire [5:0]                            calib_data_offset_0;
666 
  wire [5:0]                            calib_data_offset_1;
667 
  wire [5:0]                            calib_data_offset_2;
668 
  wire [1:0]                            calib_rank_cnt;
669 
  wire [1:0]                            calib_cas_slot;
670 
  wire [nCK_PER_CLK*ROW_WIDTH-1:0]      mux_address;
671 
  wire [3:0]                            mux_aux_out;
672 
  wire [3:0]                            aux_out_map;
673 
  wire [nCK_PER_CLK*BANK_WIDTH-1:0]     mux_bank;
674 
  wire [2:0]                            mux_cmd;
675 
  wire                                  mux_cmd_wren;
676 
  wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n;
677 
  wire                                  mux_ctl_wren;
678 
  wire [1:0]                            mux_cas_slot;
679 
  wire [5:0]                            mux_data_offset;
680 
  wire [5:0]                            mux_data_offset_1;
681 
  wire [5:0]                            mux_data_offset_2;
682 
  wire [nCK_PER_CLK-1:0]                mux_ras_n;
683 
  wire [nCK_PER_CLK-1:0]                mux_cas_n;
684 
  wire [1:0]                            mux_rank_cnt;
685 
  wire                                  mux_reset_n;
686 
  wire [nCK_PER_CLK-1:0]                mux_we_n;
687 
  wire [2*nCK_PER_CLK*DQ_WIDTH-1:0]     mux_wrdata;
688 
  wire [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask;
689 
  wire                                  mux_wrdata_en;
690 
  wire [nCK_PER_CLK-1:0]                 mux_cke ;
691 
  wire [1:0]                             mux_odt ;
692 
  wire                                  phy_if_empty_def;
693 
  wire                                  phy_if_reset;
694 
  wire                                  phy_init_data_sel;
695 
  wire [2*nCK_PER_CLK*DQ_WIDTH-1:0]     rd_data_map;
696 
  wire                                  phy_rddata_valid_w;
697 
  reg                                   rddata_valid_reg;
698 
  reg  [2*nCK_PER_CLK*DQ_WIDTH-1:0]     rd_data_reg;
699 
  wire [4:0]                            idelaye2_init_val;
700 
  wire [5:0]                            oclkdelay_init_val;
701 
  wire                                  po_counter_load_en;
702 
  wire [DQS_CNT_WIDTH:0]                byte_sel_cnt;
703 
  wire [DRAM_WIDTH-1:0]                 fine_delay_incdec_pb;
704 
  wire                                  fine_delay_sel;
705 
  wire                                  pd_out;
706 
 
707 
  //***************************************************************************
708 
 
709 
  assign dbg_rddata_valid = rddata_valid_reg;
710 
  assign dbg_rddata       = rd_data_reg;
711 
 
712 
  assign dbg_rd_data_offset = calib_rd_data_offset_0;
713 
  assign dbg_pi_phaselocked_done = pi_phase_locked_all;
714 
 
715 
  assign dbg_po_counter_read_val = po_counter_read_val;
716 
  assign dbg_pi_counter_read_val = pi_counter_read_val;
717 
 
718 
  //***************************************************************************
719 
 
720 
  genvar i;
721 
  generate
722 
     for (i = 0; i < CK_WIDTH; i = i+1) begin: clock_gen
723 
        assign ddr_ck[i]   = ddr_clk[LP_DDR_CK_WIDTH * i];
724 
        assign ddr_ck_n[i] = ddr_clk[(LP_DDR_CK_WIDTH * i) + 1];
725 
     end
726 
  endgenerate
727 
 
728 
  //***************************************************************************
729 
  // During memory initialization and calibration the calibration logic drives
730 
  // the memory signals. After calibration is complete the memory controller
731 
  // drives the memory signals.
732 
  // Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
733 
  //***************************************************************************
734 
 
735 
  wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n_temp ;
736 
  genvar v ;
737 
 
738 
  generate
739 
    if((REG_CTRL == "ON") && (DRAM_TYPE == "DDR3") && (RANKS == 1) && (nCS_PER_RANK ==2)) begin : cs_rdimm
740 
      for(v = 0 ; v < CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK ; v = v+1 ) begin
741 
        if((v%(CS_WIDTH*nCS_PER_RANK)) == 0) begin
742 
         assign mc_cs_n_temp[v] = mc_cs_n[v] ;
743 
        end else begin
744 
         assign mc_cs_n_temp[v] = 'b1 ;
745 
        end
746 
      end
747 
    end else begin
748 
      assign mc_cs_n_temp = mc_cs_n ;
749 
    end
750 
  endgenerate
751 
 
752 
  assign mux_wrdata      = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata : phy_wrdata;
753 
  assign mux_wrdata_mask = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_mask : 'b0;
754 
  assign mux_address     = (phy_init_data_sel | init_wrcal_complete) ? mc_address : phy_address;
755 
  assign mux_bank        = (phy_init_data_sel | init_wrcal_complete) ? mc_bank : phy_bank;
756 
  assign mux_cs_n        = (phy_init_data_sel | init_wrcal_complete) ? mc_cs_n_temp : phy_cs_n;
757 
  assign mux_ras_n       = (phy_init_data_sel | init_wrcal_complete) ? mc_ras_n : phy_ras_n;
758 
  assign mux_cas_n       = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_n : phy_cas_n;
759 
  assign mux_we_n        = (phy_init_data_sel | init_wrcal_complete) ? mc_we_n : phy_we_n;
760 
  assign mux_reset_n     = (phy_init_data_sel | init_wrcal_complete) ? mc_reset_n : phy_reset_n;
761 
  assign mux_aux_out     = (phy_init_data_sel | init_wrcal_complete) ? mc_aux_out0 : calib_aux_out;
762 
  assign mux_odt         = (phy_init_data_sel | init_wrcal_complete) ? mc_odt      : calib_odt    ;
763 
  assign mux_cke         = (phy_init_data_sel | init_wrcal_complete) ? mc_cke      : calib_cke    ;
764 
  assign mux_cmd_wren    = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd_wren :
765 
                                                 calib_cmd_wren;
766 
  assign mux_ctl_wren  =   (phy_init_data_sel | init_wrcal_complete) ? mc_ctl_wren :
767 
                                                 calib_ctl_wren;
768 
  assign mux_wrdata_en   = (phy_init_data_sel | init_wrcal_complete) ? mc_wrdata_en :
769 
                                                 calib_wrdata_en;
770 
  assign mux_cmd         = (phy_init_data_sel | init_wrcal_complete) ? mc_cmd : calib_cmd;
771 
  assign mux_cas_slot    = (phy_init_data_sel | init_wrcal_complete) ? mc_cas_slot : calib_cas_slot;
772 
  assign mux_data_offset = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset :
773 
                                                 calib_data_offset_0;
774 
  assign mux_data_offset_1 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_1 :
775 
                                                 calib_data_offset_1;
776 
  assign mux_data_offset_2 = (phy_init_data_sel | init_wrcal_complete) ? mc_data_offset_2 :
777 
                                                 calib_data_offset_2;
778 
  // Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
779 
  assign mux_rank_cnt    = 2'b00;
780 
 
781 
 
782 
  // Assigning cke & odt for DDR2 & DDR3
783 
  // No changes for DDR3 & DDR2 dual rank
784 
  // DDR2 single rank systems might potentially need 3 odt signals.
785 
  // Aux_out[2] will have the odt toggled by phy and controller
786 
  // wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
787 
  // all of the three odt bits or some of them might be used.
788 
  // mapping done in mc_phy_wrapper module
789 
   generate
790 
     if(CKE_ODT_AUX == "TRUE") begin
791 
       assign aux_out_map = ((DRAM_TYPE == "DDR2") && (RANKS == 1)) ?
792 
       {mux_aux_out[1],mux_aux_out[1],mux_aux_out[1],mux_aux_out[0]} :
793 
            mux_aux_out;
794 
     end else begin
795 
       assign aux_out_map = 4'b0000 ;
796 
     end
797 
  endgenerate
798 
 
799 
  assign init_calib_complete = phy_init_data_sel;
800 
 
801 
  assign phy_mc_ctl_full  = phy_ctl_full;
802 
  assign phy_mc_cmd_full  = phy_cmd_full;
803 
  assign phy_mc_data_full = phy_pre_data_a_full;
804 
 
805 
  //***************************************************************************
806 
  // Generate parity for DDR3 RDIMM.
807 
  //***************************************************************************
808 
 
809 
  generate
810 
    if ((DRAM_TYPE == "DDR3") && (REG_CTRL == "ON")) begin: gen_ddr3_parity
811 
      if (nCK_PER_CLK == 4) begin
812 
        always @(posedge clk) begin
813 
          parity[0] <= #TCQ (^{mux_address[(ROW_WIDTH*4)-1:ROW_WIDTH*3],
814 
                               mux_bank[(BANK_WIDTH*4)-1:BANK_WIDTH*3],
815 
                               mux_cas_n[3], mux_ras_n[3], mux_we_n[3]});
816 
        end
817 
        always @(*) begin
818 
          parity[1] = (^{mux_address[ROW_WIDTH-1:0], mux_bank[BANK_WIDTH-1:0],
819 
                         mux_cas_n[0],mux_ras_n[0], mux_we_n[0]});
820 
          parity[2] = (^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
821 
                         mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
822 
                         mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
823 
          parity[3] = (^{mux_address[(ROW_WIDTH*3)-1:ROW_WIDTH*2],
824 
                         mux_bank[(BANK_WIDTH*3)-1:BANK_WIDTH*2],
825 
                         mux_cas_n[2],mux_ras_n[2], mux_we_n[2]});
826 
        end
827 
      end else begin
828 
        always @(posedge clk) begin
829 
        parity[0] <= #TCQ(^{mux_address[(ROW_WIDTH*2)-1:ROW_WIDTH],
830 
                            mux_bank[(BANK_WIDTH*2)-1:BANK_WIDTH],
831 
                            mux_cas_n[1], mux_ras_n[1], mux_we_n[1]});
832 
        end
833 
        always @(*) begin
834 
          parity[1] = (^{mux_address[ROW_WIDTH-1:0],
835 
                         mux_bank[BANK_WIDTH-1:0],
836 
                         mux_cas_n[0], mux_ras_n[0], mux_we_n[0]});
837 
        end
838 
      end
839 
    end else begin: gen_ddr3_noparity
840 
      if (nCK_PER_CLK == 4) begin
841 
        always @(posedge clk) begin
842 
          parity[0] <= #TCQ 1'b0;
843 
          parity[1] <= #TCQ 1'b0;
844 
          parity[2] <= #TCQ 1'b0;
845 
          parity[3] <= #TCQ 1'b0;
846 
        end
847 
      end else begin
848 
        always @(posedge clk) begin
849 
          parity[0] <= #TCQ 1'b0;
850 
          parity[1] <= #TCQ 1'b0;
851 
        end
852 
      end
853 
    end
854 
  endgenerate
855 
 
856 
  //***************************************************************************
857 
  // Code for optional register stage in read path to MC for timing
858 
  //***************************************************************************
859 
  generate
860 
    if(RD_PATH_REG == 1)begin:RD_REG_TIMING
861 
      always @(posedge clk)begin
862 
        rddata_valid_reg <= #TCQ phy_rddata_valid_w;
863 
        rd_data_reg <= #TCQ rd_data_map;
864 
      end // always @ (posedge clk)
865 
    end else begin : RD_REG_NO_TIMING // block: RD_REG_TIMING
866 
      always @(phy_rddata_valid_w or rd_data_map)begin
867 
        rddata_valid_reg = phy_rddata_valid_w;
868 
        rd_data_reg = rd_data_map;
869 
      end
870 
    end
871 
  endgenerate
872 
 
873 
  assign phy_rddata_valid = rddata_valid_reg;
874 
  assign phy_rd_data = rd_data_reg;
875 
 
876 
  //***************************************************************************
877 
  // Hard PHY and accompanying bit mapping logic
878 
  //***************************************************************************
879 
 
880 
  mig_7series_v2_3_ddr_mc_phy_wrapper #
881 
    (
882 
     .TCQ                (TCQ),
883 
     .tCK                (tCK),
884 
     .BANK_TYPE          (BANK_TYPE),
885 
     .DATA_IO_PRIM_TYPE  (DATA_IO_PRIM_TYPE),
886 
     .DATA_IO_IDLE_PWRDWN(DATA_IO_IDLE_PWRDWN),
887 
     .IODELAY_GRP        (IODELAY_GRP),
888 
     .FPGA_SPEED_GRADE   (FPGA_SPEED_GRADE),
889 
     .nCK_PER_CLK        (nCK_PER_CLK),
890 
     .nCS_PER_RANK       (nCS_PER_RANK),
891 
     .BANK_WIDTH         (BANK_WIDTH),
892 
     .CKE_WIDTH          (CKE_WIDTH),
893 
     .CS_WIDTH           (CS_WIDTH),
894 
     .CK_WIDTH           (CK_WIDTH),
895 
     .LP_DDR_CK_WIDTH    (LP_DDR_CK_WIDTH),
896 
     .DDR2_DQSN_ENABLE   (DDR2_DQSN_ENABLE),
897 
     .CWL                (CWL),
898 
     .DM_WIDTH           (DM_WIDTH),
899 
     .DQ_WIDTH           (DQ_WIDTH),
900 
     .DQS_CNT_WIDTH      (DQS_CNT_WIDTH),
901 
     .DQS_WIDTH          (DQS_WIDTH),
902 
     .DRAM_TYPE          (DRAM_TYPE),
903 
     .RANKS              (RANKS),
904 
     .ODT_WIDTH          (ODT_WIDTH),
905 
     .REG_CTRL           (REG_CTRL),
906 
     .ROW_WIDTH          (ROW_WIDTH),
907 
     .USE_CS_PORT        (USE_CS_PORT),
908 
     .USE_DM_PORT        (USE_DM_PORT),
909 
     .USE_ODT_PORT       (USE_ODT_PORT),
910 
     .IBUF_LPWR_MODE     (IBUF_LPWR_MODE),
911 
     .PHYCTL_CMD_FIFO    (PHYCTL_CMD_FIFO),
912 
     .DATA_CTL_B0        (DATA_CTL_B0),
913 
     .DATA_CTL_B1        (DATA_CTL_B1),
914 
     .DATA_CTL_B2        (DATA_CTL_B2),
915 
     .DATA_CTL_B3        (DATA_CTL_B3),
916 
     .DATA_CTL_B4        (DATA_CTL_B4),
917 
     .BYTE_LANES_B0      (BYTE_LANES_B0),
918 
     .BYTE_LANES_B1      (BYTE_LANES_B1),
919 
     .BYTE_LANES_B2      (BYTE_LANES_B2),
920 
     .BYTE_LANES_B3      (BYTE_LANES_B3),
921 
     .BYTE_LANES_B4      (BYTE_LANES_B4),
922 
     .PHY_0_BITLANES     (PHY_0_BITLANES),
923 
     .PHY_1_BITLANES     (PHY_1_BITLANES),
924 
     .PHY_2_BITLANES     (PHY_2_BITLANES),
925 
     .HIGHEST_BANK       (HIGHEST_BANK),
926 
     .HIGHEST_LANE       (HIGHEST_LANE),
927 
     .CK_BYTE_MAP        (CK_BYTE_MAP),
928 
     .ADDR_MAP           (ADDR_MAP),
929 
     .BANK_MAP           (BANK_MAP),
930 
     .CAS_MAP            (CAS_MAP),
931 
     .CKE_ODT_BYTE_MAP   (CKE_ODT_BYTE_MAP),
932 
     .CKE_MAP            (CKE_MAP),
933 
     .ODT_MAP            (ODT_MAP),
934 
     .CKE_ODT_AUX        (CKE_ODT_AUX),
935 
     .CS_MAP             (CS_MAP),
936 
     .PARITY_MAP         (PARITY_MAP),
937 
     .RAS_MAP            (RAS_MAP),
938 
     .WE_MAP             (WE_MAP),
939 
     .DQS_BYTE_MAP       (DQS_BYTE_MAP),
940 
     .DATA0_MAP          (DATA0_MAP),
941 
     .DATA1_MAP          (DATA1_MAP),
942 
     .DATA2_MAP          (DATA2_MAP),
943 
     .DATA3_MAP          (DATA3_MAP),
944 
     .DATA4_MAP          (DATA4_MAP),
945 
     .DATA5_MAP          (DATA5_MAP),
946 
     .DATA6_MAP          (DATA6_MAP),
947 
     .DATA7_MAP          (DATA7_MAP),
948 
     .DATA8_MAP          (DATA8_MAP),
949 
     .DATA9_MAP          (DATA9_MAP),
950 
     .DATA10_MAP         (DATA10_MAP),
951 
     .DATA11_MAP         (DATA11_MAP),
952 
     .DATA12_MAP         (DATA12_MAP),
953 
     .DATA13_MAP         (DATA13_MAP),
954 
     .DATA14_MAP         (DATA14_MAP),
955 
     .DATA15_MAP         (DATA15_MAP),
956 
     .DATA16_MAP         (DATA16_MAP),
957 
     .DATA17_MAP         (DATA17_MAP),
958 
     .MASK0_MAP          (MASK0_MAP),
959 
     .MASK1_MAP          (MASK1_MAP),
960 
     .SIM_CAL_OPTION     (SIM_CAL_OPTION),
961 
     .MASTER_PHY_CTL     (MASTER_PHY_CTL),
962 
     .DRAM_WIDTH         (DRAM_WIDTH),
963 
     .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
964 
     )
965 
    u_ddr_mc_phy_wrapper
966 
      (
967 
       .rst                 (rst),
968 
       .iddr_rst            (iddr_rst),
969 
       .clk                 (clk),
970 
       // For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
971 
       // For memory frequencies below 400 MHz mem_refclk = mem_refclk and
972 
       // freq_refclk = 2x or 4x mem_refclk such that it remains in the
973 
       // 400~1066 MHz range
974 
       .freq_refclk         (freq_refclk),
975 
       .mem_refclk          (mem_refclk),
976 
       .mmcm_ps_clk         (mmcm_ps_clk),
977 
       .pll_lock            (pll_lock),
978 
       .sync_pulse          (sync_pulse),
979 
       .idelayctrl_refclk   (clk_ref),
980 
       .phy_cmd_wr_en       (mux_cmd_wren),
981 
       .phy_data_wr_en      (mux_wrdata_en),
982 
       // phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
983 
       //               DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
984 
       //               AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
985 
       // The fields ACTPRE, and BankCount are only used
986 
       // when the hard PHY counters are used by the MC.
987 
       .phy_ctl_wd             ({5'd0, mux_cas_slot, calib_seq, mux_data_offset,
988 
                                 mux_rank_cnt, 3'd0, aux_out_map,
989 
                                 5'd0, mux_cmd}),
990 
       .phy_ctl_wr             (mux_ctl_wren),
991 
       .phy_if_empty_def       (phy_if_empty_def),
992 
       .phy_if_reset           (phy_if_reset),
993 
       .data_offset_1          (mux_data_offset_1),
994 
       .data_offset_2          (mux_data_offset_2),
995 
       .aux_in_1               (aux_out_map),
996 
       .aux_in_2               (aux_out_map),
997 
       .idelaye2_init_val      (idelaye2_init_val),
998 
       .oclkdelay_init_val     (oclkdelay_init_val),
999 
       .if_empty               (if_empty),
1000 
       .phy_ctl_full           (phy_ctl_full),
1001 
       .phy_cmd_full           (phy_cmd_full),
1002 
       .phy_data_full          (phy_data_full),
1003 
       .phy_pre_data_a_full    (phy_pre_data_a_full),
1004 
       .ddr_clk                (ddr_clk),
1005 
       .phy_mc_go              (phy_mc_go),
1006 
       .phy_write_calib        (phy_write_calib),
1007 
       .phy_read_calib         (phy_read_calib),
1008 
       .po_fine_enable         (po_enstg2_f),
1009 
       .po_coarse_enable       (po_enstg2_c),
1010 
       .po_fine_inc            (po_stg2_fincdec),
1011 
       .po_coarse_inc          (po_stg2_cincdec),
1012 
       .po_counter_load_en     (po_counter_load_en),
1013 
       .po_counter_read_en     (1'b1),
1014 
       .po_sel_fine_oclk_delay (po_sel_stg2stg3),
1015 
       .po_counter_load_val    (),
1016 
       .po_counter_read_val    (po_counter_read_val),
1017 
       .pi_rst_dqs_find        (rst_stg1_cal),
1018 
       .pi_fine_enable         (pi_enstg2_f),
1019 
       .pi_fine_inc            (pi_stg2_fincdec),
1020 
       .pi_counter_load_en     (pi_stg2_load),
1021 
       .pi_counter_load_val    (pi_stg2_reg_l),
1022 
       .pi_counter_read_val    (pi_counter_read_val),
1023 
       .idelay_ce              (idelay_ce),
1024 
       .idelay_inc             (idelay_inc),
1025 
       .idelay_ld              (idelay_ld),
1026 
       .pi_phase_locked        (pi_phase_locked),
1027 
       .pi_phase_locked_all    (pi_phase_locked_all),
1028 
       .pi_dqs_found           (pi_found_dqs),
1029 
       .pi_dqs_found_all       (pi_dqs_found_all),
1030 
       // Currently not being used. May be used in future if periodic reads
1031 
       // become a requirement. This output could also be used to signal a
1032 
       // catastrophic failure in read capture and the need for re-cal
1033 
       .pi_dqs_out_of_range    (pi_dqs_out_of_range),
1034 
       .phy_init_data_sel      (phy_init_data_sel),
1035 
       .calib_sel              (calib_sel),
1036 
       .calib_in_common        (calib_in_common),
1037 
       .calib_zero_inputs      (calib_zero_inputs),
1038 
       .calib_zero_ctrl        (calib_zero_ctrl),
1039 
       .mux_address            (mux_address),
1040 
       .mux_bank               (mux_bank),
1041 
       .mux_cs_n               (mux_cs_n),
1042 
       .mux_ras_n              (mux_ras_n),
1043 
       .mux_cas_n              (mux_cas_n),
1044 
       .mux_we_n               (mux_we_n),
1045 
       .mux_reset_n            (mux_reset_n),
1046 
       .parity_in              (parity),
1047 
       .mux_wrdata             (mux_wrdata),
1048 
       .mux_wrdata_mask        (mux_wrdata_mask),
1049 
       .mux_odt                (mux_odt),
1050 
       .mux_cke                (mux_cke),
1051 
       .idle                   (idle),
1052 
       .rd_data                (rd_data_map),
1053 
       .ddr_addr               (ddr_addr),
1054 
       .ddr_ba                 (ddr_ba),
1055 
       .ddr_cas_n              (ddr_cas_n),
1056 
       .ddr_cke                (ddr_cke),
1057 
       .ddr_cs_n               (ddr_cs_n),
1058 
       .ddr_dm                 (ddr_dm),
1059 
       .ddr_odt                (ddr_odt),
1060 
       .ddr_parity             (ddr_parity),
1061 
       .ddr_ras_n              (ddr_ras_n),
1062 
       .ddr_we_n               (ddr_we_n),
1063 
       .ddr_dq                 (ddr_dq),
1064 
       .ddr_dqs                (ddr_dqs),
1065 
       .ddr_dqs_n              (ddr_dqs_n),
1066 
       .ddr_reset_n            (ddr_reset_n),
1067 
       .dbg_pi_counter_read_en (1'b1),
1068 
       .ref_dll_lock           (ref_dll_lock),
1069 
       .rst_phaser_ref         (rst_phaser_ref),
1070 
       .dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
1071 
       .dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
1072 
       .byte_sel_cnt           (byte_sel_cnt),
1073 
       .pd_out                 (pd_out),
1074 
       .fine_delay_incdec_pb   (fine_delay_incdec_pb),
1075 
       .fine_delay_sel         (fine_delay_sel)
1076 
       );
1077 
 
1078 
  //***************************************************************************
1079 
  // Soft memory initialization and calibration logic
1080 
  //***************************************************************************
1081 
 
1082 
  mig_7series_v2_3_ddr_calib_top #
1083 
    (
1084 
     .TCQ              (TCQ),
1085 
     .DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
1086 
     .nCK_PER_CLK      (nCK_PER_CLK),
1087 
     .PRE_REV3ES       (PRE_REV3ES),
1088 
     .tCK              (tCK),
1089 
     .CLK_PERIOD       (CLK_PERIOD),
1090 
     .N_CTL_LANES      (N_CTL_LANES),
1091 
     .CTL_BYTE_LANE    (CTL_BYTE_LANE),
1092 
     .CTL_BANK         (CTL_BANK),
1093 
     .DRAM_TYPE        (DRAM_TYPE),
1094 
     .PRBS_WIDTH       (8),
1095 
     .DQS_BYTE_MAP     (DQS_BYTE_MAP),
1096 
     .HIGHEST_BANK     (HIGHEST_BANK),
1097 
     .BANK_TYPE        (BANK_TYPE),
1098 
     .HIGHEST_LANE     (HIGHEST_LANE),
1099 
     .BYTE_LANES_B0    (BYTE_LANES_B0),
1100 
     .BYTE_LANES_B1    (BYTE_LANES_B1),
1101 
     .BYTE_LANES_B2    (BYTE_LANES_B2),
1102 
     .BYTE_LANES_B3    (BYTE_LANES_B3),
1103 
     .BYTE_LANES_B4    (BYTE_LANES_B4),
1104 
     .DATA_CTL_B0      (DATA_CTL_B0),
1105 
     .DATA_CTL_B1      (DATA_CTL_B1),
1106 
     .DATA_CTL_B2      (DATA_CTL_B2),
1107 
     .DATA_CTL_B3      (DATA_CTL_B3),
1108 
     .DATA_CTL_B4      (DATA_CTL_B4),
1109 
     .SLOT_1_CONFIG    (SLOT_1_CONFIG),
1110 
     .BANK_WIDTH       (BANK_WIDTH),
1111 
     .CA_MIRROR        (CA_MIRROR),
1112 
     .COL_WIDTH        (COL_WIDTH),
1113 
     .CKE_ODT_AUX      (CKE_ODT_AUX),
1114 
     .nCS_PER_RANK     (nCS_PER_RANK),
1115 
     .DQ_WIDTH         (DQ_WIDTH),
1116 
     .DQS_CNT_WIDTH    (DQS_CNT_WIDTH),
1117 
     .DQS_WIDTH        (DQS_WIDTH),
1118 
     .DRAM_WIDTH       (DRAM_WIDTH),
1119 
     .ROW_WIDTH        (ROW_WIDTH),
1120 
     .RANKS            (RANKS),
1121 
     .CS_WIDTH         (CS_WIDTH),
1122 
     .CKE_WIDTH        (CKE_WIDTH),
1123 
     .DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
1124 
     .PER_BIT_DESKEW   ("OFF"),
1125 
     .CALIB_ROW_ADD    (CALIB_ROW_ADD),
1126 
     .CALIB_COL_ADD    (CALIB_COL_ADD),
1127 
     .CALIB_BA_ADD     (CALIB_BA_ADD),
1128 
     .AL               (AL),
1129 
     .BURST_MODE       (BURST_MODE),
1130 
     .BURST_TYPE       (BURST_TYPE),
1131 
     .nCL              (CL),
1132 
     .nCWL             (CWL),
1133 
     .tRFC             (tRFC),
1134 
         .tREFI            (tREFI),
1135 
     .OUTPUT_DRV       (OUTPUT_DRV),
1136 
     .REG_CTRL         (REG_CTRL),
1137 
     .ADDR_CMD_MODE    (ADDR_CMD_MODE),
1138 
     .RTT_NOM          (RTT_NOM),
1139 
     .RTT_WR           (RTT_WR),
1140 
     .WRLVL            (WRLVL_W),
1141 
     .USE_ODT_PORT     (USE_ODT_PORT),
1142 
     .SIM_INIT_OPTION  (SIM_INIT_OPTION),
1143 
     .SIM_CAL_OPTION   (SIM_CAL_OPTION),
1144 
     .DEBUG_PORT       (DEBUG_PORT),
1145 
     .IDELAY_ADJ       (IDELAY_ADJ),
1146 
     .FINE_PER_BIT     (FINE_PER_BIT),
1147 
     .CENTER_COMP_MODE (CENTER_COMP_MODE),
1148 
     .PI_VAL_ADJ       (PI_VAL_ADJ),
1149 
     .TAPSPERKCLK      (TAPSPERKCLK),
1150 
     .POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
1151 
     )
1152 
    u_ddr_calib_top
1153 
      (
1154 
       .clk                         (clk),
1155 
       .rst                         (rst),
1156 
 
1157 
       .tg_err                      (error),
1158 
       .rst_tg_mc                   (rst_tg_mc),
1159 
 
1160 
       .slot_0_present              (slot_0_present),
1161 
       .slot_1_present              (slot_1_present),
1162 
       // PHY Control Block and IN_FIFO status
1163 
       .phy_ctl_ready               (phy_mc_go),
1164 
       .phy_ctl_full                (1'b0),
1165 
       .phy_cmd_full                (1'b0),
1166 
       .phy_data_full               (1'b0),
1167 
       .phy_if_empty                (if_empty),
1168 
       .idelaye2_init_val           (idelaye2_init_val),
1169 
       .oclkdelay_init_val          (oclkdelay_init_val),
1170 
       // From calib logic To data IN_FIFO
1171 
       // DQ IDELAY tap value from Calib logic
1172 
       // port to be added to mc_phy by Gary
1173 
       .dlyval_dq                   (),
1174 
       // hard PHY calibration modes
1175 
       .write_calib                 (phy_write_calib),
1176 
       .read_calib                  (phy_read_calib),
1177 
       // DQS count and ck/addr/cmd to be mapped to calib_sel
1178 
       // based on parameter that defines placement of ctl lanes
1179 
       // and DQS byte groups in each bank. When phy_write_calib
1180 
       // is de-asserted calib_sel should select CK/addr/cmd/ctl.
1181 
       .calib_sel                   (calib_sel),
1182 
       .calib_in_common             (calib_in_common),
1183 
       .calib_zero_inputs           (calib_zero_inputs),
1184 
       .calib_zero_ctrl             (calib_zero_ctrl),
1185 
       .phy_if_empty_def            (phy_if_empty_def),
1186 
       .phy_if_reset                (phy_if_reset),
1187 
       // Signals from calib logic to be MUXED with MC
1188 
       // signals before sending to hard PHY
1189 
       .calib_ctl_wren              (calib_ctl_wren),
1190 
       .calib_cmd_wren              (calib_cmd_wren),
1191 
       .calib_seq                   (calib_seq),
1192 
       .calib_aux_out               (calib_aux_out),
1193 
       .calib_odt                   (calib_odt),
1194 
       .calib_cke                   (calib_cke),
1195 
       .calib_cmd                   (calib_cmd),
1196 
       .calib_wrdata_en             (calib_wrdata_en),
1197 
       .calib_rank_cnt              (calib_rank_cnt),
1198 
       .calib_cas_slot              (calib_cas_slot),
1199 
       .calib_data_offset_0         (calib_data_offset_0),
1200 
       .calib_data_offset_1         (calib_data_offset_1),
1201 
       .calib_data_offset_2         (calib_data_offset_2),
1202 
       .phy_reset_n                 (phy_reset_n),
1203 
       .phy_address                 (phy_address),
1204 
       .phy_bank                    (phy_bank),
1205 
       .phy_cs_n                    (phy_cs_n),
1206 
       .phy_ras_n                   (phy_ras_n),
1207 
       .phy_cas_n                   (phy_cas_n),
1208 
       .phy_we_n                    (phy_we_n),
1209 
       .phy_wrdata                  (phy_wrdata),
1210 
       // DQS Phaser_IN calibration/status signals
1211 
       .pi_phaselocked              (pi_phase_locked),
1212 
       .pi_phase_locked_all         (pi_phase_locked_all),
1213 
       .pi_found_dqs                (pi_found_dqs),
1214 
       .pi_dqs_found_all            (pi_dqs_found_all),
1215 
       .pi_dqs_found_lanes          (dbg_pi_dqs_found_lanes_phy4lanes),
1216 
       .pi_rst_stg1_cal             (rst_stg1_cal),
1217 
       .pi_en_stg2_f                (pi_enstg2_f),
1218 
       .pi_stg2_f_incdec            (pi_stg2_fincdec),
1219 
       .pi_stg2_load                (pi_stg2_load),
1220 
       .pi_stg2_reg_l               (pi_stg2_reg_l),
1221 
       .pi_counter_read_val      (pi_counter_read_val),
1222 
       .device_temp                 (device_temp),
1223 
       .tempmon_sample_en           (tempmon_sample_en),
1224 
       // IDELAY tap enable and inc signals
1225 
       .idelay_ce                   (idelay_ce),
1226 
       .idelay_inc                  (idelay_inc),
1227 
       .idelay_ld                   (idelay_ld),
1228 
       // DQS Phaser_OUT calibration/status signals
1229 
       .po_sel_stg2stg3             (po_sel_stg2stg3),
1230 
       .po_stg2_c_incdec            (po_stg2_cincdec),
1231 
       .po_en_stg2_c                (po_enstg2_c),
1232 
       .po_stg2_f_incdec            (po_stg2_fincdec),
1233 
       .po_en_stg2_f                (po_enstg2_f),
1234 
       .po_counter_load_en          (po_counter_load_en),
1235 
       .po_counter_read_val         (po_counter_read_val),
1236 
       // From data IN_FIFO To Calib logic and MC/UI
1237 
       .phy_rddata                  (rd_data_map),
1238 
       // From calib logic To MC
1239 
       .phy_rddata_valid            (phy_rddata_valid_w),
1240 
       .calib_rd_data_offset_0      (calib_rd_data_offset_0),
1241 
       .calib_rd_data_offset_1      (calib_rd_data_offset_1),
1242 
       .calib_rd_data_offset_2      (calib_rd_data_offset_2),
1243 
       .calib_writes                (),
1244 
       // Mem Init and Calibration status To MC
1245 
       .init_calib_complete         (phy_init_data_sel),
1246 
       .init_wrcal_complete         (init_wrcal_complete),
1247 
       // Debug Error signals
1248 
       .pi_phase_locked_err         (dbg_pi_phaselock_err),
1249 
       .pi_dqsfound_err             (dbg_pi_dqsfound_err),
1250 
       .wrcal_err                   (dbg_wrcal_err),
1251 
       //used for oclk stg3 centering
1252 
       .pd_out                           (pd_out),
1253 
       .psen                             (psen),
1254 
       .psincdec                         (psincdec),
1255 
       .psdone                           (psdone),
1256 
       .poc_sample_pd                    (poc_sample_pd),
1257 
       // Debug Signals
1258 
       .dbg_pi_phaselock_start      (dbg_pi_phaselock_start),
1259 
       .dbg_pi_dqsfound_start       (dbg_pi_dqsfound_start),
1260 
       .dbg_pi_dqsfound_done        (dbg_pi_dqsfound_done),
1261 
       .dbg_wrlvl_start             (dbg_wrlvl_start),
1262 
       .dbg_wrlvl_done              (dbg_wrlvl_done),
1263 
       .dbg_wrlvl_err               (dbg_wrlvl_err),
1264 
       .dbg_wrlvl_fine_tap_cnt      (dbg_wrlvl_fine_tap_cnt),
1265 
       .dbg_wrlvl_coarse_tap_cnt    (dbg_wrlvl_coarse_tap_cnt),
1266 
       .dbg_phy_wrlvl               (dbg_phy_wrlvl),
1267 
       .dbg_tap_cnt_during_wrlvl    (dbg_tap_cnt_during_wrlvl),
1268 
       .dbg_wl_edge_detect_valid    (dbg_wl_edge_detect_valid),
1269 
       .dbg_rd_data_edge_detect     (dbg_rd_data_edge_detect),
1270 
       .dbg_wrcal_start             (dbg_wrcal_start),
1271 
       .dbg_wrcal_done              (dbg_wrcal_done),
1272 
       .dbg_phy_wrcal               (dbg_phy_wrcal),
1273 
       .dbg_final_po_fine_tap_cnt   (dbg_final_po_fine_tap_cnt),
1274 
       .dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
1275 
       .dbg_rdlvl_start             (dbg_rdlvl_start),
1276 
       .dbg_rdlvl_done              (dbg_rdlvl_done),
1277 
       .dbg_rdlvl_err               (dbg_rdlvl_err),
1278 
       .dbg_cpt_first_edge_cnt      (dbg_cpt_first_edge_cnt),
1279 
       .dbg_cpt_second_edge_cnt     (dbg_cpt_second_edge_cnt),
1280 
       .dbg_cpt_tap_cnt             (dbg_cpt_tap_cnt),
1281 
       .dbg_dq_idelay_tap_cnt       (dbg_dq_idelay_tap_cnt),
1282 
       .dbg_sel_pi_incdec           (dbg_sel_pi_incdec),
1283 
       .dbg_sel_po_incdec           (dbg_sel_po_incdec),
1284 
       .dbg_byte_sel                (dbg_byte_sel),
1285 
       .dbg_pi_f_inc                (dbg_pi_f_inc),
1286 
       .dbg_pi_f_dec                (dbg_pi_f_dec),
1287 
       .dbg_po_f_inc                (dbg_po_f_inc),
1288 
       .dbg_po_f_stg23_sel          (dbg_po_f_stg23_sel),
1289 
       .dbg_po_f_dec                (dbg_po_f_dec),
1290 
       .dbg_idel_up_all             (dbg_idel_up_all),
1291 
       .dbg_idel_down_all           (dbg_idel_down_all),
1292 
       .dbg_idel_up_cpt             (dbg_idel_up_cpt),
1293 
       .dbg_idel_down_cpt           (dbg_idel_down_cpt),
1294 
       .dbg_sel_idel_cpt            (dbg_sel_idel_cpt),
1295 
       .dbg_sel_all_idel_cpt        (dbg_sel_all_idel_cpt),
1296 
       .dbg_phy_rdlvl               (dbg_phy_rdlvl),
1297 
       .dbg_calib_top               (dbg_calib_top),
1298 
       .dbg_phy_init                (dbg_phy_init),
1299 
       .dbg_prbs_rdlvl              (dbg_prbs_rdlvl),
1300 
       .dbg_dqs_found_cal           (dbg_dqs_found_cal),
1301 
       .dbg_phy_oclkdelay_cal       (dbg_phy_oclkdelay_cal),
1302 
       .dbg_oclkdelay_rd_data       (dbg_oclkdelay_rd_data),
1303 
       .dbg_oclkdelay_calib_start   (dbg_oclkdelay_calib_start),
1304 
       .dbg_oclkdelay_calib_done    (dbg_oclkdelay_calib_done),
1305 
       .prbs_final_dqs_tap_cnt_r (prbs_final_dqs_tap_cnt_r),
1306 
       .dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
1307 
       .dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
1308 
       .byte_sel_cnt           (byte_sel_cnt),
1309 
       .fine_delay_incdec_pb   (fine_delay_incdec_pb),
1310 
       .fine_delay_sel         (fine_delay_sel)
1311 
       );
1312 
 
1313 
endmodule

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