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URL https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk

Subversion Repositories usb_fpga_2_14

[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.13/] [memfifo.srcs/] [sources_1/] [ip/] [mig_7series_0/] [tcl.log] - Blame information for rev 2

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Line No. Rev Author Line
1 2 ZTEX 
MIG: 19:12:40 : Running customizer.xit
2 
MIG: 19:12:40 : ################# RUNNING MIG INTERACTIVE ###################
3 
MIG: 19:12:40 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /home/stefan/.Xil/Vivado-1881-ws2/coregen/mig_7series_0
4 
MIG: 19:12:40 : synp_flow:  -- synthesis_mode: Other
5 
MIG: 19:12:40 : outputDirectory: /home/stefan/.Xil/Vivado-1881-ws2/coregen/mig_7series_0/_tmp/
6 
MIG: 19:12:40 : vivado_mode: xpg_pa
7 
MIG: 19:12:40 : HDL Language: Verilog
8 
MIG: 19:12:40 : compInfo: true
9 
MIG: 19:12:40 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-1881-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-1881-ws2/coregen/mig_7series_0/xil_txt.out ...
10 
MIG: 19:17:35 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-1881-ws2/coregen/mig_7series_0/mig_a.prj
11 
MIG: 19:17:35 : Component_Name: mig_7series_0
12 
MIG: 19:17:35 : Moving mig_7series_0.veo ...
13 
MIG: 19:17:35 : Moving mig_7series_0 ...
14 
MIG: 19:17:35 : Moving mig_7series_0_xmdf.tcl ...
15 
MIG: 19:17:35 : Sending back 0
16 
MIG: 19:17:43 : xml_input_file: mig_a.prj
17 
MIG: 19:17:43 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
18 
MIG: 19:17:43 : xml_input_file: mig_a.prj
19 
MIG: 19:17:43 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
20 
MIG: 19:17:43 : In updateAllModelParams
21 
MIG: 19:17:43 : IGN:     mig_7series_0 <==>     mig_7series_0
22 
MIG: 19:17:43 : IGN:          <==>
23 
MIG: 19:17:43 : XGUI hdlLanguage: Verilog
24 
MIG: 19:17:43 : xgui vivado_mode: xpg_pa
25 
MIG: 19:17:43 : xgui hdlLanguage: Verilog -- hdlExt: v
26 
MIG: 19:17:43 : Reading /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ...
27 
MIG: 19:17:44 : 1
28 
MIG: 19:17:44 : Inside fn mem: DDR3
29 
MIG: 19:17:44 : QDRII+ Inside fn ui: 100000000
30 
MIG: 19:17:44 :
31 
MIG: 19:17:44 :
32 
MIG: 19:17:44 : 100000000
33 
MIG: 19:17:44 :
34 
MIG: 19:17:44 :  polarity_value: 1
35 
MIG: 19:17:44 :
36 
MIG: 19:17:44 :
37 
MIG: 19:17:44 :
38 
MIG: 19:17:44 :  Valid Param: DDR3_BANK_WIDTH ==> 3
39 
MIG: 19:17:44 :
40 
MIG: 19:17:44 :  Valid Param: DDR3_CK_WIDTH ==> 1
41 
MIG: 19:17:44 :  Invalid Param: DDR3_COL_WIDTH ==> 10
42 
MIG: 19:17:44 :
43 
MIG: 19:17:44 :  Valid Param: DDR3_CS_WIDTH ==> 1
44 
MIG: 19:17:44 :
45 
MIG: 19:17:44 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
46 
MIG: 19:17:44 :
47 
MIG: 19:17:44 :  Valid Param: DDR3_CKE_WIDTH ==> 1
48 
MIG: 19:17:44 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
49 
MIG: 19:17:44 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
50 
MIG: 19:17:44 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
51 
MIG: 19:17:44 : 2
52 
MIG: 19:17:44 :  Valid Param: DDR3_DM_WIDTH ==> 2
53 
MIG: 19:17:44 : 16
54 
MIG: 19:17:44 :  Valid Param: DDR3_DQ_WIDTH ==> 16
55 
MIG: 19:17:44 : 2
56 
MIG: 19:17:44 :  Valid Param: DDR3_DQS_WIDTH ==> 2
57 
MIG: 19:17:44 :
58 
MIG: 19:17:44 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
59 
MIG: 19:17:44 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
60 
MIG: 19:17:44 :
61 
MIG: 19:17:44 :  Valid Param: ECC ==> OFF
62 
MIG: 19:17:44 : 16
63 
MIG: 19:17:44 :  Valid Param: DDR3_DATA_WIDTH ==> 16
64 
MIG: 19:17:44 :  Invalid Param: ECC_TEST ==> "OFF"
65 
MIG: 19:17:44 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
66 
MIG: 19:17:44 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
67 
MIG: 19:17:44 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
68 
MIG: 19:17:44 :  Invalid Param: DDR3_RANKS ==> 1
69 
MIG: 19:17:44 :
70 
MIG: 19:17:44 :  Valid Param: DDR3_ODT_WIDTH ==> 1
71 
MIG: 19:17:44 :
72 
MIG: 19:17:44 :  Valid Param: DDR3_ROW_WIDTH ==> 14
73 
MIG: 19:17:44 : 28
74 
MIG: 19:17:44 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
75 
MIG: 19:17:44 : 0
76 
MIG: 19:17:44 :  Valid Param: DDR3_USE_CS_PORT ==> 0
77 
MIG: 19:17:44 :
78 
MIG: 19:17:44 :  Valid Param: DDR3_USE_DM_PORT ==> 1
79 
MIG: 19:17:44 :
80 
MIG: 19:17:44 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
81 
MIG: 19:17:44 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
82 
MIG: 19:17:44 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
83 
MIG: 19:17:44 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
84 
MIG: 19:17:44 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
85 
MIG: 19:17:44 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
86 
MIG: 19:17:44 :  Invalid Param: DDR3_AL ==> "0"
87 
MIG: 19:17:44 :  Invalid Param: DDR3_nAL ==> 0
88 
MIG: 19:17:44 :  Invalid Param: DDR3_BURST_MODE ==> "8"
89 
MIG: 19:17:44 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
90 
MIG: 19:17:44 :  Invalid Param: DDR3_CL ==> 6
91 
MIG: 19:17:44 :  Invalid Param: DDR3_CWL ==> 5
92 
MIG: 19:17:44 :  Invalid Param: DDR3_OUTPUT_DRV ==> "LOW"
93 
MIG: 19:17:44 :  Invalid Param: DDR3_RTT_NOM ==> "40"
94 
MIG: 19:17:44 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
95 
MIG: 19:17:44 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
96 
MIG: 19:17:45 :
97 
MIG: 19:17:45 :  Valid Param: DDR3_REG_CTRL ==> OFF
98 
MIG: 19:17:45 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
99 
MIG: 19:17:45 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
100 
MIG: 19:17:45 :  Invalid Param: DDR3_CLKIN_PERIOD ==> -2147483647
101 
MIG: 19:17:45 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 0
102 
MIG: 19:17:45 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 0
103 
MIG: 19:17:45 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
104 
MIG: 19:17:45 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 0
105 
MIG: 19:17:45 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 0
106 
MIG: 19:17:45 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 0
107 
MIG: 19:17:45 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 0
108 
MIG: 19:17:45 :  Invalid Param: DDR3_tCKE ==> 5000
109 
MIG: 19:17:45 :  Invalid Param: DDR3_tFAW ==> 40000
110 
MIG: 19:17:45 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
111 
MIG: 19:17:45 :  Invalid Param: DDR3_tRAS ==> 35000
112 
MIG: 19:17:45 :  Invalid Param: DDR3_tRCD ==> 13750
113 
MIG: 19:17:45 :  Invalid Param: DDR3_tREFI ==> 7800000
114 
MIG: 19:17:45 :  Invalid Param: DDR3_tRFC ==> 160000
115 
MIG: 19:17:45 :  Invalid Param: DDR3_tRP ==> 13750
116 
MIG: 19:17:45 :  Invalid Param: DDR3_tRRD ==> 7500
117 
MIG: 19:17:45 :  Invalid Param: DDR3_tRTP ==> 7500
118 
MIG: 19:17:45 :  Invalid Param: DDR3_tWTR ==> 7500
119 
MIG: 19:17:45 :  Invalid Param: DDR3_tZQI ==> 128_000_000
120 
MIG: 19:17:45 :  Invalid Param: DDR3_tZQCS ==> 64
121 
MIG: 19:17:45 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
122 
MIG: 19:17:45 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
123 
MIG: 19:17:45 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
124 
MIG: 19:17:45 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
125 
MIG: 19:17:45 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
126 
MIG: 19:17:45 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
127 
MIG: 19:17:45 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
128 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
129 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
130 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
131 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
132 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
133 
MIG: 19:17:45 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_CFF_3DF_2FF
134 
MIG: 19:17:45 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
135 
MIG: 19:17:45 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
136 
MIG: 19:17:45 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
137 
MIG: 19:17:45 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038
138 
MIG: 19:17:45 :  Invalid Param: DDR3_BANK_MAP ==> 36'h033_02A_032
139 
MIG: 19:17:45 :  Invalid Param: DDR3_CAS_MAP ==> 12'h020
140 
MIG: 19:17:45 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
141 
MIG: 19:17:45 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_02B
142 
MIG: 19:17:45 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
143 
MIG: 19:17:45 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
144 
MIG: 19:17:45 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
145 
MIG: 19:17:45 :  Invalid Param: DDR3_RAS_MAP ==> 12'h021
146 
MIG: 19:17:45 :  Invalid Param: DDR3_WE_MAP ==> 12'h022
147 
MIG: 19:17:45 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
148 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h016_018_014_019_010_017_011_013
149 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h003_002_005_004_001_006_000_007
150 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
151 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
152 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
153 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
154 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
155 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
156 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
157 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
158 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
159 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
160 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
161 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
162 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
163 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
164 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
165 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
166 
MIG: 19:17:45 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_012
167 
MIG: 19:17:45 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
168 
MIG: 19:17:45 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
169 
MIG: 19:17:45 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
170 
MIG: 19:17:45 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
171 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
172 
MIG: 19:17:45 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
173 
MIG: 19:17:45 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
174 
MIG: 19:17:45 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
175 
MIG: 19:17:45 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
176 
MIG: 19:17:45 :  Invalid Param: DDR3_WRLVL ==> "ON"
177 
MIG: 19:17:45 :  Invalid Param: DDR3_ORDERING ==> "NORM"
178 
MIG: 19:17:45 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
179 
MIG: 19:17:45 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
180 
MIG: 19:17:45 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
181 
MIG: 19:17:45 :  Invalid Param: DDR3_TCQ ==> 100
182 
MIG: 19:17:45 :  Invalid Param: DDR3_IODELAY_GRP ==> "MIG_7SERIES_0_IODELAY_MIG"
183 
MIG: 19:17:45 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
184 
MIG: 19:17:45 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
185 
MIG: 19:17:45 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
186 
MIG: 19:17:45 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
187 
MIG: 19:17:45 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
188 
MIG: 19:17:45 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
189 
MIG: 19:17:45 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
190 
MIG: 19:17:45 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
191 
MIG: 19:17:45 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
192 
MIG: 19:17:45 :  Invalid Param: DDR3_tCK ==> 2500
193 
MIG: 19:17:45 : 4
194 
MIG: 19:17:45 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
195 
MIG: 19:17:45 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
196 
MIG: 19:17:45 :
197 
MIG: 19:17:45 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
198 
MIG: 19:17:45 :
199 
MIG: 19:17:45 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
200 
MIG: 19:17:45 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
201 
MIG: 19:17:45 : NOBUF
202 
MIG: 19:17:45 : NOBUF
203 
MIG: 19:17:45 :
204 
MIG: 19:17:45 : Same Interface
205 
MIG: 19:18:02 : Running synthesis.xit
206 
MIG: 19:18:02 : IGN:     mig_7series_0 <==>     mig_7series_0
207 
MIG: 19:18:02 : IGN:          <==>
208 
MIG: 19:18:02 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
209 
MIG: 19:18:02 : Running vlog_synth_rpr.xit
210 
MIG: 19:18:02 : IGN:     mig_7series_0 <==>     mig_7series_0
211 
MIG: 19:18:02 : IGN:          <==>
212 
MIG: 19:18:02 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
213 
MIG: 19:18:02 : Running implementation.xit
214 
MIG: 19:18:02 : IGN:     mig_7series_0 <==>     mig_7series_0
215 
MIG: 19:18:02 : IGN:          <==>
216 
MIG: 19:18:02 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
217 
MIG: 19:18:02 : Running vlog_synth_rpr.xit
218 
MIG: 19:18:02 : IGN:     mig_7series_0 <==>     mig_7series_0
219 
MIG: 19:18:02 : IGN:          <==>
220 
MIG: 19:18:02 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
221 
MIG: 19:18:03 : Running simulation.xit
222 
MIG: 19:18:03 : IGN:     mig_7series_0 <==>     mig_7series_0
223 
MIG: 19:18:03 : IGN:          <==>
224 
MIG: 19:18:04 : Added 67  files from /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
225 
MIG: 19:18:04 : Running vlog_sim_rpr.xit
226 
MIG: 19:18:04 : IGN:     mig_7series_0 <==>     mig_7series_0
227 
MIG: 19:18:04 : IGN:          <==>
228 
MIG: 19:18:04 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
229 
MIG: 19:18:04 : Running vlog_sim_rpr.xit
230 
MIG: 19:18:04 : IGN:     mig_7series_0 <==>     mig_7series_0
231 
MIG: 19:18:04 : IGN:          <==>
232 
MIG: 19:18:04 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d/memtest-vivado2/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
233 
MIG: 13:53:58 : xml_input_file: mig_a.prj
234 
MIG: 13:53:58 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
235 
MIG: 13:53:58 : xml_input_file: mig_a.prj
236 
MIG: 13:53:58 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
237 
MIG: 13:54:31 : Running customizer.xit
238 
MIG: 13:54:31 : ################# RUNNING MIG INTERACTIVE ###################
239 
MIG: 13:54:31 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0
240 
MIG: 13:54:31 : synp_flow:  -- synthesis_mode: Other
241 
MIG: 13:54:31 : outputDirectory: /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0/_tmp/
242 
MIG: 13:54:31 : vivado_mode: xpg_pa
243 
MIG: 13:54:31 : HDL Language: Verilog
244 
MIG: 13:54:31 : compInfo: false
245 
MIG: 13:54:31 : Vivado Options xc7a100t csg324 -2
246 
MIG: 13:54:31 : 1: xc7a100t 2: csg324 3: -2
247 
MIG: 13:54:31 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0/xil_txt.out ...
248 
MIG: 14:00:06 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0/mig_a.prj
249 
MIG: 14:00:06 : Component_Name: mig_7series_0
250 
MIG: 14:00:06 : Moving mig_7series_0.veo ...
251 
MIG: 14:00:06 : Moving mig_7series_0 ...
252 
MIG: 14:00:06 : Moving mig_7series_0_xmdf.tcl ...
253 
MIG: 14:00:06 : Sending back 0
254 
MIG: 14:03:45 : Running synthesis.xit
255 
MIG: 14:03:45 : ################# RUNNING MIG BATCH ###################
256 
MIG: 14:03:45 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
257 
MIG: 14:03:45 : synp_flow:  -- synthesis_mode: Other
258 
MIG: 14:03:45 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
259 
MIG: 14:03:45 : vivado_mode: xpg_pa
260 
MIG: 14:03:45 : HDL Language: Verilog
261 
MIG: 14:03:45 : compInfo: false
262 
MIG: 14:03:45 : Vivado Options xc7a100t csg324 -2
263 
MIG: 14:03:45 : 1: xc7a100t 2: csg324 3: -2
264 
MIG: 14:03:45 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
265 
MIG: 14:03:59 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
266 
MIG: 14:03:59 : Component_Name: mig_7series_0
267 
MIG: 14:03:59 : Moving mig_7series_0_xmdf.tcl ...
268 
MIG: 14:03:59 : Moving mig_7series_0 ...
269 
MIG: 14:03:59 : Moving mig_7series_0.veo ...
270 
MIG: 14:03:59 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
271 
MIG: 14:04:00 : Running vlog_synth_rpr.xit
272 
MIG: 14:04:00 : IGN:     mig_7series_0 <==>     mig_7series_0
273 
MIG: 14:04:00 : IGN:          <==>         320
274 
MIG: 14:04:00 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
275 
MIG: 14:04:00 : Running implementation.xit
276 
MIG: 14:04:00 : IGN:     mig_7series_0 <==>     mig_7series_0
277 
MIG: 14:04:00 : IGN:          <==>         320
278 
MIG: 14:04:00 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
279 
MIG: 14:04:00 : Running vlog_synth_rpr.xit
280 
MIG: 14:04:00 : IGN:     mig_7series_0 <==>     mig_7series_0
281 
MIG: 14:04:00 : IGN:          <==>         320
282 
MIG: 14:04:00 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
283 
MIG: 14:04:01 : Running simulation.xit
284 
MIG: 14:04:01 : IGN:     mig_7series_0 <==>     mig_7series_0
285 
MIG: 14:04:01 : IGN:          <==>         320
286 
MIG: 14:04:01 : Added 50  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
287 
MIG: 14:04:01 : Running vlog_sim_rpr.xit
288 
MIG: 14:04:01 : IGN:     mig_7series_0 <==>     mig_7series_0
289 
MIG: 14:04:01 : IGN:          <==>         320
290 
MIG: 14:04:01 : Added 0  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
291 
MIG: 14:04:01 : Running vlog_sim_rpr.xit
292 
MIG: 14:04:01 : IGN:     mig_7series_0 <==>     mig_7series_0
293 
MIG: 14:04:01 : IGN:          <==>         320
294 
MIG: 14:04:01 : Added 0  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
295 
MIG: 14:07:25 : Running customizer.xit
296 
MIG: 14:07:25 : ################# RUNNING MIG INTERACTIVE ###################
297 
MIG: 14:07:25 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0_0
298 
MIG: 14:07:25 : synp_flow:  -- synthesis_mode: Other
299 
MIG: 14:07:25 : outputDirectory: /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0_0/_tmp/
300 
MIG: 14:07:25 : vivado_mode: xpg_pa
301 
MIG: 14:07:25 : HDL Language: Verilog
302 
MIG: 14:07:25 : compInfo: false
303 
MIG: 14:07:25 : Vivado Options xc7a100t csg324 -2
304 
MIG: 14:07:25 : 1: xc7a100t 2: csg324 3: -2
305 
MIG: 14:07:25 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0_0/xil_txt.out ...
306 
MIG: 14:11:42 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-27763-ws2/coregen/mig_7series_0_0/mig_a.prj
307 
MIG: 14:11:42 : Component_Name: mig_7series_0
308 
MIG: 14:11:42 : Moving mig_7series_0.veo ...
309 
MIG: 14:11:42 : Moving mig_7series_0 ...
310 
MIG: 14:11:42 : Moving mig_7series_0_xmdf.tcl ...
311 
MIG: 14:11:42 : Sending back 0
312 
MIG: 14:12:05 : Running synthesis.xit
313 
MIG: 14:12:05 : ################# RUNNING MIG BATCH ###################
314 
MIG: 14:12:05 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
315 
MIG: 14:12:05 : synp_flow:  -- synthesis_mode: Other
316 
MIG: 14:12:05 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
317 
MIG: 14:12:05 : vivado_mode: xpg_pa
318 
MIG: 14:12:05 : HDL Language: Verilog
319 
MIG: 14:12:05 : compInfo: false
320 
MIG: 14:12:05 : Vivado Options xc7a100t csg324 -2
321 
MIG: 14:12:05 : 1: xc7a100t 2: csg324 3: -2
322 
MIG: 14:12:05 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
323 
MIG: 14:12:21 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
324 
MIG: 14:12:21 : Component_Name: mig_7series_0
325 
MIG: 14:12:21 : Moving mig_7series_0_xmdf.tcl ...
326 
MIG: 14:12:21 : Moving mig_7series_0 ...
327 
MIG: 14:12:21 : Moving mig_7series_0.veo ...
328 
MIG: 14:12:21 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
329 
MIG: 14:12:21 : Running vlog_synth_rpr.xit
330 
MIG: 14:12:21 : IGN:     mig_7series_0 <==>     mig_7series_0
331 
MIG: 14:12:21 : IGN:          <==>         303.03
332 
MIG: 14:12:21 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
333 
MIG: 14:12:21 : Running implementation.xit
334 
MIG: 14:12:21 : IGN:     mig_7series_0 <==>     mig_7series_0
335 
MIG: 14:12:21 : IGN:          <==>         303.03
336 
MIG: 14:12:21 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
337 
MIG: 14:12:21 : Running vlog_synth_rpr.xit
338 
MIG: 14:12:21 : IGN:     mig_7series_0 <==>     mig_7series_0
339 
MIG: 14:12:21 : IGN:          <==>         303.03
340 
MIG: 14:12:21 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
341 
MIG: 14:12:23 : Running simulation.xit
342 
MIG: 14:12:23 : IGN:     mig_7series_0 <==>     mig_7series_0
343 
MIG: 14:12:23 : IGN:          <==>         303.03
344 
MIG: 14:12:23 : Added 67  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
345 
MIG: 14:12:23 : Running vlog_sim_rpr.xit
346 
MIG: 14:12:23 : IGN:     mig_7series_0 <==>     mig_7series_0
347 
MIG: 14:12:23 : IGN:          <==>         303.03
348 
MIG: 14:12:23 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
349 
MIG: 14:12:23 : Running vlog_sim_rpr.xit
350 
MIG: 14:12:23 : IGN:     mig_7series_0 <==>     mig_7series_0
351 
MIG: 14:12:23 : IGN:          <==>         303.03
352 
MIG: 14:12:23 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
353 
MIG: 15:33:53 : xml_input_file: mig_a.prj
354 
MIG: 15:33:53 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
355 
MIG: 15:33:53 : xml_input_file: mig_a.prj
356 
MIG: 15:33:53 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
357 
MIG: 15:34:25 : Running customizer.xit
358 
MIG: 15:34:25 : ################# RUNNING MIG INTERACTIVE ###################
359 
MIG: 15:34:25 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0
360 
MIG: 15:34:25 : synp_flow:  -- synthesis_mode: Other
361 
MIG: 15:34:25 : outputDirectory: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0/_tmp/
362 
MIG: 15:34:25 : vivado_mode: xpg_pa
363 
MIG: 15:34:25 : HDL Language: Verilog
364 
MIG: 15:34:25 : compInfo: false
365 
MIG: 15:34:25 : Vivado Options xc7a100t csg324 -2
366 
MIG: 15:34:25 : 1: xc7a100t 2: csg324 3: -2
367 
MIG: 15:34:25 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0/xil_txt.out ...
368 
MIG: 15:37:52 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0/mig_a.prj
369 
MIG: 15:37:52 : Component_Name: mig_7series_0
370 
MIG: 15:37:52 : Moving mig_7series_0.veo ...
371 
MIG: 15:37:52 : Moving mig_7series_0 ...
372 
MIG: 15:37:52 : Moving mig_7series_0_xmdf.tcl ...
373 
MIG: 15:37:52 : Sending back 0
374 
MIG: 15:38:12 : Running synthesis.xit
375 
MIG: 15:38:12 : ################# RUNNING MIG BATCH ###################
376 
MIG: 15:38:12 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
377 
MIG: 15:38:12 : synp_flow:  -- synthesis_mode: Other
378 
MIG: 15:38:12 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
379 
MIG: 15:38:12 : vivado_mode: xpg_pa
380 
MIG: 15:38:12 : HDL Language: Verilog
381 
MIG: 15:38:12 : compInfo: false
382 
MIG: 15:38:12 : Vivado Options xc7a100t csg324 -2
383 
MIG: 15:38:12 : 1: xc7a100t 2: csg324 3: -2
384 
MIG: 15:38:12 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
385 
MIG: 15:38:27 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
386 
MIG: 15:38:27 : Component_Name: mig_7series_0
387 
MIG: 15:38:27 : Moving mig_7series_0_xmdf.tcl ...
388 
MIG: 15:38:27 : Moving mig_7series_0 ...
389 
MIG: 15:38:27 : Moving mig_7series_0.veo ...
390 
MIG: 15:38:27 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
391 
MIG: 15:38:27 : Running vlog_synth_rpr.xit
392 
MIG: 15:38:27 : IGN:     mig_7series_0 <==>     mig_7series_0
393 
MIG: 15:38:27 : IGN:          <==>         303.03
394 
MIG: 15:38:27 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
395 
MIG: 15:38:28 : Running implementation.xit
396 
MIG: 15:38:28 : IGN:     mig_7series_0 <==>     mig_7series_0
397 
MIG: 15:38:28 : IGN:          <==>         303.03
398 
MIG: 15:38:28 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
399 
MIG: 15:38:28 : Running vlog_synth_rpr.xit
400 
MIG: 15:38:28 : IGN:     mig_7series_0 <==>     mig_7series_0
401 
MIG: 15:38:28 : IGN:          <==>         303.03
402 
MIG: 15:38:28 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
403 
MIG: 15:38:29 : Running simulation.xit
404 
MIG: 15:38:29 : IGN:     mig_7series_0 <==>     mig_7series_0
405 
MIG: 15:38:29 : IGN:          <==>         303.03
406 
MIG: 15:38:29 : Added 50  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
407 
MIG: 15:38:29 : Running vlog_sim_rpr.xit
408 
MIG: 15:38:29 : IGN:     mig_7series_0 <==>     mig_7series_0
409 
MIG: 15:38:29 : IGN:          <==>         303.03
410 
MIG: 15:38:29 : Added 0  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
411 
MIG: 15:38:29 : Running vlog_sim_rpr.xit
412 
MIG: 15:38:29 : IGN:     mig_7series_0 <==>     mig_7series_0
413 
MIG: 15:38:29 : IGN:          <==>         303.03
414 
MIG: 15:38:29 : Added 0  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
415 
MIG: 15:56:26 : Running customizer.xit
416 
MIG: 15:56:26 : ################# RUNNING MIG INTERACTIVE ###################
417 
MIG: 15:56:26 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_0
418 
MIG: 15:56:26 : synp_flow:  -- synthesis_mode: Other
419 
MIG: 15:56:26 : outputDirectory: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_0/_tmp/
420 
MIG: 15:56:26 : vivado_mode: xpg_pa
421 
MIG: 15:56:26 : HDL Language: Verilog
422 
MIG: 15:56:26 : compInfo: false
423 
MIG: 15:56:26 : Vivado Options xc7a100t csg324 -2
424 
MIG: 15:56:26 : 1: xc7a100t 2: csg324 3: -2
425 
MIG: 15:56:26 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_0/xil_txt.out ...
426 
MIG: 15:58:02 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_0/mig_a.prj
427 
MIG: 15:58:02 : Component_Name: mig_7series_0
428 
MIG: 15:58:02 : Moving mig_7series_0.veo ...
429 
MIG: 15:58:02 : Moving mig_7series_0 ...
430 
MIG: 15:58:02 : Moving mig_7series_0_xmdf.tcl ...
431 
MIG: 15:58:02 : Sending back 0
432 
MIG: 15:58:19 : Running synthesis.xit
433 
MIG: 15:58:19 : ################# RUNNING MIG BATCH ###################
434 
MIG: 15:58:19 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
435 
MIG: 15:58:19 : synp_flow:  -- synthesis_mode: Other
436 
MIG: 15:58:19 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
437 
MIG: 15:58:19 : vivado_mode: xpg_pa
438 
MIG: 15:58:19 : HDL Language: Verilog
439 
MIG: 15:58:19 : compInfo: false
440 
MIG: 15:58:19 : Vivado Options xc7a100t csg324 -2
441 
MIG: 15:58:19 : 1: xc7a100t 2: csg324 3: -2
442 
MIG: 15:58:19 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
443 
MIG: 15:58:35 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
444 
MIG: 15:58:35 : Component_Name: mig_7series_0
445 
MIG: 15:58:35 : Moving mig_7series_0_xmdf.tcl ...
446 
MIG: 15:58:35 : Moving mig_7series_0 ...
447 
MIG: 15:58:35 : Moving mig_7series_0.veo ...
448 
MIG: 15:58:35 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
449 
MIG: 15:58:35 : Running vlog_synth_rpr.xit
450 
MIG: 15:58:35 : IGN:     mig_7series_0 <==>     mig_7series_0
451 
MIG: 15:58:35 : IGN:          <==>         400
452 
MIG: 15:58:35 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
453 
MIG: 15:58:35 : Running implementation.xit
454 
MIG: 15:58:35 : IGN:     mig_7series_0 <==>     mig_7series_0
455 
MIG: 15:58:35 : IGN:          <==>         400
456 
MIG: 15:58:35 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
457 
MIG: 15:58:35 : Running vlog_synth_rpr.xit
458 
MIG: 15:58:35 : IGN:     mig_7series_0 <==>     mig_7series_0
459 
MIG: 15:58:35 : IGN:          <==>         400
460 
MIG: 15:58:35 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
461 
MIG: 15:58:37 : Running simulation.xit
462 
MIG: 15:58:37 : IGN:     mig_7series_0 <==>     mig_7series_0
463 
MIG: 15:58:37 : IGN:          <==>         400
464 
MIG: 15:58:37 : Added 67  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
465 
MIG: 15:58:37 : Running vlog_sim_rpr.xit
466 
MIG: 15:58:37 : IGN:     mig_7series_0 <==>     mig_7series_0
467 
MIG: 15:58:37 : IGN:          <==>         400
468 
MIG: 15:58:37 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
469 
MIG: 15:58:37 : Running vlog_sim_rpr.xit
470 
MIG: 15:58:37 : IGN:     mig_7series_0 <==>     mig_7series_0
471 
MIG: 15:58:37 : IGN:          <==>         400
472 
MIG: 15:58:37 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
473 
MIG: 19:56:47 : Running customizer.xit
474 
MIG: 19:56:47 : ################# RUNNING MIG INTERACTIVE ###################
475 
MIG: 19:56:47 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_2
476 
MIG: 19:56:47 : synp_flow:  -- synthesis_mode: Other
477 
MIG: 19:56:47 : outputDirectory: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_2/_tmp/
478 
MIG: 19:56:47 : vivado_mode: xpg_pa
479 
MIG: 19:56:47 : HDL Language: Verilog
480 
MIG: 19:56:47 : compInfo: false
481 
MIG: 19:56:47 : Vivado Options xc7a100t csg324 -3
482 
MIG: 19:56:47 : 1: xc7a100t 2: csg324 3: -2
483 
MIG: 19:56:47 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_2/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_2/xil_txt.out ...
484 
MIG: 19:59:36 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_2/mig_a.prj
485 
MIG: 19:59:36 : Component_Name: mig_7series_0
486 
MIG: 19:59:36 : Moving mig_7series_0.veo ...
487 
MIG: 19:59:36 : Moving mig_7series_0 ...
488 
MIG: 19:59:36 : Moving mig_7series_0_xmdf.tcl ...
489 
MIG: 19:59:36 : Sending back 0
490 
MIG: 20:02:52 : xml_input_file: mig_a.prj
491 
MIG: 20:02:52 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
492 
MIG: 20:02:52 : xml_input_file: mig_a.prj
493 
MIG: 20:02:52 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
494 
MIG: 20:02:52 : In updateAllModelParams
495 
MIG: 20:02:52 : ################# RUNNING MIG BATCH ###################
496 
MIG: 20:02:52 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
497 
MIG: 20:02:52 : synp_flow:  -- synthesis_mode: Other
498 
MIG: 20:02:52 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
499 
MIG: 20:02:52 : vivado_mode: xpg_pa
500 
MIG: 20:02:52 : HDL Language: Verilog
501 
MIG: 20:02:52 : compInfo: true
502 
MIG: 20:02:52 : Vivado Options xc7a100t csg324 -3
503 
MIG: 20:02:52 : 1: xc7a100t 2: csg324 3: -3
504 
MIG: 20:02:52 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
505 
MIG: 20:03:06 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
506 
MIG: 20:03:06 : Component_Name: mig_7series_0
507 
MIG: 20:03:06 : Moving mig_7series_0_xmdf.tcl ...
508 
MIG: 20:03:06 : Moving mig_7series_0 ...
509 
MIG: 20:03:06 : Moving mig_7series_0.veo ...
510 
MIG: 20:03:06 : XGUI hdlLanguage: Verilog
511 
MIG: 20:03:06 : xgui vivado_mode: xpg_pa
512 
MIG: 20:03:06 : xgui hdlLanguage: Verilog -- hdlExt: v
513 
MIG: 20:03:06 : Reading /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ...
514 
MIG: 20:03:07 : 1
515 
MIG: 20:03:07 : Inside fn mem: DDR3
516 
MIG: 20:03:07 : QDRII+ Inside fn ui: 133250000
517 
MIG: 20:03:07 :
518 
MIG: 20:03:07 :
519 
MIG: 20:03:07 : 133250000
520 
MIG: 20:03:07 :
521 
MIG: 20:03:07 :  polarity_value: 1
522 
MIG: 20:03:07 :
523 
MIG: 20:03:07 :
524 
MIG: 20:03:07 :
525 
MIG: 20:03:07 :  Valid Param: DDR3_BANK_WIDTH ==> 3
526 
MIG: 20:03:07 :
527 
MIG: 20:03:07 :  Valid Param: DDR3_CK_WIDTH ==> 1
528 
MIG: 20:03:07 :  Invalid Param: DDR3_COL_WIDTH ==> 10
529 
MIG: 20:03:07 :
530 
MIG: 20:03:07 :  Valid Param: DDR3_CS_WIDTH ==> 1
531 
MIG: 20:03:07 :
532 
MIG: 20:03:07 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
533 
MIG: 20:03:07 :
534 
MIG: 20:03:07 :  Valid Param: DDR3_CKE_WIDTH ==> 1
535 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
536 
MIG: 20:03:07 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
537 
MIG: 20:03:07 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
538 
MIG: 20:03:07 : 2
539 
MIG: 20:03:07 :  Valid Param: DDR3_DM_WIDTH ==> 2
540 
MIG: 20:03:07 : 16
541 
MIG: 20:03:07 :  Valid Param: DDR3_DQ_WIDTH ==> 16
542 
MIG: 20:03:07 : 2
543 
MIG: 20:03:07 :  Valid Param: DDR3_DQS_WIDTH ==> 2
544 
MIG: 20:03:07 :
545 
MIG: 20:03:07 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
546 
MIG: 20:03:07 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
547 
MIG: 20:03:07 :
548 
MIG: 20:03:07 :  Valid Param: ECC ==> OFF
549 
MIG: 20:03:07 : 16
550 
MIG: 20:03:07 :  Valid Param: DDR3_DATA_WIDTH ==> 16
551 
MIG: 20:03:07 :  Invalid Param: ECC_TEST ==> "OFF"
552 
MIG: 20:03:07 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
553 
MIG: 20:03:07 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
554 
MIG: 20:03:07 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
555 
MIG: 20:03:07 :  Invalid Param: DDR3_RANKS ==> 1
556 
MIG: 20:03:07 :
557 
MIG: 20:03:07 :  Valid Param: DDR3_ODT_WIDTH ==> 1
558 
MIG: 20:03:07 :
559 
MIG: 20:03:07 :  Valid Param: DDR3_ROW_WIDTH ==> 14
560 
MIG: 20:03:07 : 28
561 
MIG: 20:03:07 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
562 
MIG: 20:03:07 : 0
563 
MIG: 20:03:07 :  Valid Param: DDR3_USE_CS_PORT ==> 0
564 
MIG: 20:03:07 :
565 
MIG: 20:03:07 :  Valid Param: DDR3_USE_DM_PORT ==> 1
566 
MIG: 20:03:07 :
567 
MIG: 20:03:07 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
568 
MIG: 20:03:07 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
569 
MIG: 20:03:07 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
570 
MIG: 20:03:07 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
571 
MIG: 20:03:07 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
572 
MIG: 20:03:07 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
573 
MIG: 20:03:07 :  Invalid Param: DDR3_AL ==> "0"
574 
MIG: 20:03:07 :  Invalid Param: DDR3_nAL ==> 0
575 
MIG: 20:03:07 :  Invalid Param: DDR3_BURST_MODE ==> "8"
576 
MIG: 20:03:07 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
577 
MIG: 20:03:07 :  Invalid Param: DDR3_CL ==> 7
578 
MIG: 20:03:07 :  Invalid Param: DDR3_CWL ==> 6
579 
MIG: 20:03:07 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
580 
MIG: 20:03:07 :  Invalid Param: DDR3_RTT_NOM ==> "40"
581 
MIG: 20:03:07 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
582 
MIG: 20:03:07 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
583 
MIG: 20:03:07 :
584 
MIG: 20:03:07 :  Valid Param: DDR3_REG_CTRL ==> OFF
585 
MIG: 20:03:07 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
586 
MIG: 20:03:07 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
587 
MIG: 20:03:07 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 1875
588 
MIG: 20:03:07 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 2
589 
MIG: 20:03:07 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
590 
MIG: 20:03:07 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
591 
MIG: 20:03:07 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
592 
MIG: 20:03:07 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
593 
MIG: 20:03:07 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
594 
MIG: 20:03:07 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
595 
MIG: 20:03:07 :  Invalid Param: DDR3_tCKE ==> 5000
596 
MIG: 20:03:07 :  Invalid Param: DDR3_tFAW ==> 40000
597 
MIG: 20:03:07 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
598 
MIG: 20:03:07 :  Invalid Param: DDR3_tRAS ==> 35000
599 
MIG: 20:03:07 :  Invalid Param: DDR3_tRCD ==> 13750
600 
MIG: 20:03:07 :  Invalid Param: DDR3_tREFI ==> 7800000
601 
MIG: 20:03:07 :  Invalid Param: DDR3_tRFC ==> 160000
602 
MIG: 20:03:07 :  Invalid Param: DDR3_tRP ==> 13750
603 
MIG: 20:03:07 :  Invalid Param: DDR3_tRRD ==> 7500
604 
MIG: 20:03:07 :  Invalid Param: DDR3_tRTP ==> 7500
605 
MIG: 20:03:07 :  Invalid Param: DDR3_tWTR ==> 7500
606 
MIG: 20:03:07 :  Invalid Param: DDR3_tZQI ==> 128_000_000
607 
MIG: 20:03:07 :  Invalid Param: DDR3_tZQCS ==> 64
608 
MIG: 20:03:07 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
609 
MIG: 20:03:07 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
610 
MIG: 20:03:07 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
611 
MIG: 20:03:07 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
612 
MIG: 20:03:07 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
613 
MIG: 20:03:07 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
614 
MIG: 20:03:07 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
615 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
616 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
617 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
618 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
619 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
620 
MIG: 20:03:07 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_CFF_3DF_2FF
621 
MIG: 20:03:07 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
622 
MIG: 20:03:07 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
623 
MIG: 20:03:07 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
624 
MIG: 20:03:07 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038
625 
MIG: 20:03:07 :  Invalid Param: DDR3_BANK_MAP ==> 36'h033_02A_032
626 
MIG: 20:03:07 :  Invalid Param: DDR3_CAS_MAP ==> 12'h020
627 
MIG: 20:03:07 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
628 
MIG: 20:03:07 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_02B
629 
MIG: 20:03:07 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
630 
MIG: 20:03:07 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
631 
MIG: 20:03:07 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
632 
MIG: 20:03:07 :  Invalid Param: DDR3_RAS_MAP ==> 12'h021
633 
MIG: 20:03:07 :  Invalid Param: DDR3_WE_MAP ==> 12'h022
634 
MIG: 20:03:07 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
635 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h016_018_014_019_010_017_011_013
636 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h003_002_005_004_001_006_000_007
637 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
638 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
639 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
640 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
641 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
642 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
643 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
644 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
645 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
646 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
647 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
648 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
649 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
650 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
651 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
652 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
653 
MIG: 20:03:07 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_012
654 
MIG: 20:03:07 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
655 
MIG: 20:03:07 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
656 
MIG: 20:03:07 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
657 
MIG: 20:03:07 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
658 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
659 
MIG: 20:03:07 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
660 
MIG: 20:03:07 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
661 
MIG: 20:03:07 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
662 
MIG: 20:03:07 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
663 
MIG: 20:03:07 :  Invalid Param: DDR3_WRLVL ==> "ON"
664 
MIG: 20:03:07 :  Invalid Param: DDR3_ORDERING ==> "NORM"
665 
MIG: 20:03:07 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
666 
MIG: 20:03:07 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
667 
MIG: 20:03:07 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
668 
MIG: 20:03:07 :  Invalid Param: DDR3_TCQ ==> 100
669 
MIG: 20:03:07 :  Invalid Param: DDR3_IODELAY_GRP ==> "MIG_7SERIES_0_IODELAY_MIG"
670 
MIG: 20:03:07 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
671 
MIG: 20:03:07 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
672 
MIG: 20:03:07 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
673 
MIG: 20:03:07 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
674 
MIG: 20:03:07 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
675 
MIG: 20:03:07 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
676 
MIG: 20:03:07 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
677 
MIG: 20:03:07 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
678 
MIG: 20:03:07 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
679 
MIG: 20:03:07 :  Invalid Param: DDR3_tCK ==> 1875
680 
MIG: 20:03:07 : 4
681 
MIG: 20:03:07 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
682 
MIG: 20:03:07 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
683 
MIG: 20:03:07 :
684 
MIG: 20:03:07 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
685 
MIG: 20:03:07 :
686 
MIG: 20:03:07 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
687 
MIG: 20:03:07 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
688 
MIG: 20:03:07 : NOBUF
689 
MIG: 20:03:07 : NOBUF
690 
MIG: 20:03:07 :
691 
MIG: 20:03:07 : Same Interface
692 
MIG: 20:03:25 : Running synthesis.xit
693 
MIG: 20:03:25 : IGN:     mig_7series_0 <==>     mig_7series_0
694 
MIG: 20:03:25 : IGN:          <==>         533.333
695 
MIG: 20:03:25 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
696 
MIG: 20:03:25 : Running vlog_synth_rpr.xit
697 
MIG: 20:03:25 : IGN:     mig_7series_0 <==>     mig_7series_0
698 
MIG: 20:03:25 : IGN:          <==>         533.333
699 
MIG: 20:03:25 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
700 
MIG: 20:03:25 : Running implementation.xit
701 
MIG: 20:03:25 : IGN:     mig_7series_0 <==>     mig_7series_0
702 
MIG: 20:03:25 : IGN:          <==>         533.333
703 
MIG: 20:03:25 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
704 
MIG: 20:03:25 : Running vlog_synth_rpr.xit
705 
MIG: 20:03:25 : IGN:     mig_7series_0 <==>     mig_7series_0
706 
MIG: 20:03:25 : IGN:          <==>         533.333
707 
MIG: 20:03:25 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
708 
MIG: 20:03:27 : Running simulation.xit
709 
MIG: 20:03:27 : IGN:     mig_7series_0 <==>     mig_7series_0
710 
MIG: 20:03:27 : IGN:          <==>         533.333
711 
MIG: 20:03:27 : Added 67  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
712 
MIG: 20:03:27 : Running vlog_sim_rpr.xit
713 
MIG: 20:03:27 : IGN:     mig_7series_0 <==>     mig_7series_0
714 
MIG: 20:03:27 : IGN:          <==>         533.333
715 
MIG: 20:03:27 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
716 
MIG: 20:03:28 : Running vlog_sim_rpr.xit
717 
MIG: 20:03:28 : IGN:     mig_7series_0 <==>     mig_7series_0
718 
MIG: 20:03:28 : IGN:          <==>         533.333
719 
MIG: 20:03:28 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
720 
MIG: 20:04:18 : Running customizer.xit
721 
MIG: 20:04:18 : ################# RUNNING MIG INTERACTIVE ###################
722 
MIG: 20:04:18 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_5
723 
MIG: 20:04:18 : synp_flow:  -- synthesis_mode: Other
724 
MIG: 20:04:18 : outputDirectory: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_5/_tmp/
725 
MIG: 20:04:18 : vivado_mode: xpg_pa
726 
MIG: 20:04:18 : HDL Language: Verilog
727 
MIG: 20:04:18 : compInfo: false
728 
MIG: 20:04:18 : Vivado Options xc7a100t csg324 -3
729 
MIG: 20:04:18 : 1: xc7a100t 2: csg324 3: -3
730 
MIG: 20:04:18 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_5/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_5/xil_txt.out ...
731 
MIG: 20:08:03 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-23578-ws2/coregen/mig_7series_0_5/mig_a.prj
732 
MIG: 20:08:03 : Component_Name: mig_7series_0
733 
MIG: 20:08:03 : Moving mig_7series_0.veo ...
734 
MIG: 20:08:03 : Moving mig_7series_0 ...
735 
MIG: 20:08:03 : Moving mig_7series_0_xmdf.tcl ...
736 
MIG: 20:08:03 : Sending back 0
737 
MIG: 20:08:23 : Running synthesis.xit
738 
MIG: 20:08:23 : ################# RUNNING MIG BATCH ###################
739 
MIG: 20:08:23 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
740 
MIG: 20:08:23 : synp_flow:  -- synthesis_mode: Other
741 
MIG: 20:08:23 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
742 
MIG: 20:08:23 : vivado_mode: xpg_pa
743 
MIG: 20:08:23 : HDL Language: Verilog
744 
MIG: 20:08:23 : compInfo: false
745 
MIG: 20:08:23 : Vivado Options xc7a100t csg324 -3
746 
MIG: 20:08:23 : 1: xc7a100t 2: csg324 3: -3
747 
MIG: 20:08:23 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
748 
MIG: 20:08:38 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
749 
MIG: 20:08:38 : Component_Name: mig_7series_0
750 
MIG: 20:08:38 : Moving mig_7series_0_xmdf.tcl ...
751 
MIG: 20:08:38 : Moving mig_7series_0 ...
752 
MIG: 20:08:38 : Moving mig_7series_0.veo ...
753 
MIG: 20:08:39 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
754 
MIG: 20:08:39 : Running vlog_synth_rpr.xit
755 
MIG: 20:08:39 : IGN:     mig_7series_0 <==>     mig_7series_0
756 
MIG: 20:08:39 : IGN:          <==>         533.333
757 
MIG: 20:08:39 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
758 
MIG: 20:08:39 : Running implementation.xit
759 
MIG: 20:08:39 : IGN:     mig_7series_0 <==>     mig_7series_0
760 
MIG: 20:08:39 : IGN:          <==>         533.333
761 
MIG: 20:08:39 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
762 
MIG: 20:08:39 : Running vlog_synth_rpr.xit
763 
MIG: 20:08:39 : IGN:     mig_7series_0 <==>     mig_7series_0
764 
MIG: 20:08:39 : IGN:          <==>         533.333
765 
MIG: 20:08:39 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
766 
MIG: 20:08:40 : Running simulation.xit
767 
MIG: 20:08:40 : IGN:     mig_7series_0 <==>     mig_7series_0
768 
MIG: 20:08:40 : IGN:          <==>         533.333
769 
MIG: 20:08:40 : Added 50  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
770 
MIG: 20:08:40 : Running vlog_sim_rpr.xit
771 
MIG: 20:08:40 : IGN:     mig_7series_0 <==>     mig_7series_0
772 
MIG: 20:08:40 : IGN:          <==>         533.333
773 
MIG: 20:08:40 : Added 0  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
774 
MIG: 20:08:40 : Running vlog_sim_rpr.xit
775 
MIG: 20:08:40 : IGN:     mig_7series_0 <==>     mig_7series_0
776 
MIG: 20:08:40 : IGN:          <==>         533.333
777 
MIG: 20:08:40 : Added 0  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
778 
MIG: 21:36:51 : xml_input_file: mig_a.prj
779 
MIG: 21:36:51 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
780 
MIG: 21:36:51 : xml_input_file: mig_a.prj
781 
MIG: 21:36:51 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
782 
MIG: 21:36:51 : In updateAllModelParams
783 
MIG: 21:36:51 : ################# RUNNING MIG BATCH ###################
784 
MIG: 21:36:51 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
785 
MIG: 21:36:51 : synp_flow:  -- synthesis_mode: Other
786 
MIG: 21:36:51 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
787 
MIG: 21:36:51 : vivado_mode: xpg_pa
788 
MIG: 21:36:51 : HDL Language: Verilog
789 
MIG: 21:36:51 : compInfo: true
790 
MIG: 21:36:51 : Vivado Options xc7a100t csg324 -2
791 
MIG: 21:36:51 : 1: xc7a100t 2: csg324 3: -3
792 
MIG: 21:36:51 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
793 
MIG: 21:37:15 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
794 
MIG: 21:37:15 : Component_Name: mig_7series_0
795 
MIG: 21:37:23 : ################# RUNNING MIG BATCH ###################
796 
MIG: 21:37:23 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
797 
MIG: 21:37:23 : synp_flow:  -- synthesis_mode: Other
798 
MIG: 21:37:23 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
799 
MIG: 21:37:23 : vivado_mode: xpg_pa
800 
MIG: 21:37:23 : HDL Language: Verilog
801 
MIG: 21:37:23 : compInfo: false
802 
MIG: 21:37:23 : Vivado Options xc7a100t csg324 -2
803 
MIG: 21:37:23 : 1: xc7a100t 2: csg324 3: -3
804 
MIG: 21:37:23 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
805 
MIG: 21:37:35 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
806 
MIG: 21:37:35 : Component_Name: mig_7series_0
807 
MIG: 21:41:21 : Running customizer.xit
808 
MIG: 21:41:21 : ################# RUNNING MIG INTERACTIVE ###################
809 
MIG: 21:41:21 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /home/stefan/.Xil/Vivado-4721-ws2/coregen/mig_7series_0
810 
MIG: 21:41:21 : synp_flow:  -- synthesis_mode: Other
811 
MIG: 21:41:21 : outputDirectory: /home/stefan/.Xil/Vivado-4721-ws2/coregen/mig_7series_0/_tmp/
812 
MIG: 21:41:21 : vivado_mode: xpg_pa
813 
MIG: 21:41:21 : HDL Language: Verilog
814 
MIG: 21:41:21 : compInfo: false
815 
MIG: 21:41:21 : Vivado Options xc7a100t csg324 -2
816 
MIG: 21:41:21 : 1: xc7a100t 2: csg324 3: -3
817 
MIG: 21:41:21 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-4721-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-4721-ws2/coregen/mig_7series_0/xil_txt.out ...
818 
MIG: 21:45:16 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-4721-ws2/coregen/mig_7series_0/mig_a.prj
819 
MIG: 21:45:16 : Component_Name: mig_7series_0
820 
MIG: 21:45:16 : Moving mig_7series_0.veo ...
821 
MIG: 21:45:16 : Moving mig_7series_0 ...
822 
MIG: 21:45:16 : Moving mig_7series_0_xmdf.tcl ...
823 
MIG: 21:45:16 : Moving log.txt ...
824 
MIG: 21:45:16 : Sending back 0
825 
MIG: 21:45:31 : IGN:     mig_7series_0 <==>     mig_7series_0
826 
MIG: 21:45:31 : IGN:          <==>
827 
MIG: 21:45:33 : Running synthesis.xit
828 
MIG: 21:45:33 : IGN:     mig_7series_0 <==>     mig_7series_0
829 
MIG: 21:45:33 : IGN:          <==>
830 
MIG: 21:45:33 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
831 
MIG: 21:45:33 : Running vlog_synth_rpr.xit
832 
MIG: 21:45:33 : IGN:     mig_7series_0 <==>     mig_7series_0
833 
MIG: 21:45:33 : IGN:          <==>
834 
MIG: 21:45:33 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
835 
MIG: 21:45:33 : Running implementation.xit
836 
MIG: 21:45:33 : IGN:     mig_7series_0 <==>     mig_7series_0
837 
MIG: 21:45:33 : IGN:          <==>
838 
MIG: 21:45:33 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
839 
MIG: 21:45:33 : Running vlog_synth_rpr.xit
840 
MIG: 21:45:33 : IGN:     mig_7series_0 <==>     mig_7series_0
841 
MIG: 21:45:33 : IGN:          <==>
842 
MIG: 21:45:33 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
843 
MIG: 21:45:35 : Running simulation.xit
844 
MIG: 21:45:35 : IGN:     mig_7series_0 <==>     mig_7series_0
845 
MIG: 21:45:35 : IGN:          <==>
846 
MIG: 21:45:35 : Added 67  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
847 
MIG: 21:45:35 : Running vlog_sim_rpr.xit
848 
MIG: 21:45:35 : IGN:     mig_7series_0 <==>     mig_7series_0
849 
MIG: 21:45:35 : IGN:          <==>
850 
MIG: 21:45:35 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
851 
MIG: 21:45:35 : Running vlog_sim_rpr.xit
852 
MIG: 21:45:35 : IGN:     mig_7series_0 <==>     mig_7series_0
853 
MIG: 21:45:35 : IGN:          <==>
854 
MIG: 21:45:35 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
855 
MIG: 21:47:22 : IGN:     mig_7series_0 <==>     mig_7series_0
856 
MIG: 21:47:22 : IGN:          <==>
857 
MIG: 21:48:23 : ################# RUNNING MIG BATCH ###################
858 
MIG: 21:48:23 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
859 
MIG: 21:48:23 : synp_flow:  -- synthesis_mode: Other
860 
MIG: 21:48:23 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
861 
MIG: 21:48:23 : vivado_mode: xpg_pa
862 
MIG: 21:48:23 : HDL Language: Verilog
863 
MIG: 21:48:23 : compInfo: false
864 
MIG: 21:48:23 : Vivado Options xc7a100t csg324 -2
865 
MIG: 21:48:23 : 1: xc7a100t 2: csg324 3: -2
866 
MIG: 21:48:23 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
867 
MIG: 21:48:40 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
868 
MIG: 21:48:40 : Component_Name: mig_7series_0
869 
MIG: 21:48:40 : Moving mig_7series_0_xmdf.tcl ...
870 
MIG: 21:48:40 : Moving mig_7series_0 ...
871 
MIG: 21:48:40 : Moving mig_7series_0.veo ...
872 
MIG: 21:48:40 : Moving log.txt ...
873 
MIG: 21:48:42 : Running synthesis.xit
874 
MIG: 21:48:42 : IGN:     mig_7series_0 <==>     mig_7series_0
875 
MIG: 21:48:42 : IGN:          <==>         400
876 
MIG: 21:48:42 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
877 
MIG: 21:48:42 : Running vlog_synth_rpr.xit
878 
MIG: 21:48:42 : IGN:     mig_7series_0 <==>     mig_7series_0
879 
MIG: 21:48:42 : IGN:          <==>         400
880 
MIG: 21:48:42 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
881 
MIG: 21:48:42 : Running implementation.xit
882 
MIG: 21:48:42 : IGN:     mig_7series_0 <==>     mig_7series_0
883 
MIG: 21:48:42 : IGN:          <==>         400
884 
MIG: 21:48:42 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
885 
MIG: 21:48:42 : Running vlog_synth_rpr.xit
886 
MIG: 21:48:42 : IGN:     mig_7series_0 <==>     mig_7series_0
887 
MIG: 21:48:42 : IGN:          <==>         400
888 
MIG: 21:48:42 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
889 
MIG: 21:48:43 : Running simulation.xit
890 
MIG: 21:48:44 : IGN:     mig_7series_0 <==>     mig_7series_0
891 
MIG: 21:48:44 : IGN:          <==>         400
892 
MIG: 21:48:44 : Added 67  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
893 
MIG: 21:48:44 : Running vlog_sim_rpr.xit
894 
MIG: 21:48:44 : IGN:     mig_7series_0 <==>     mig_7series_0
895 
MIG: 21:48:44 : IGN:          <==>         400
896 
MIG: 21:48:44 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
897 
MIG: 21:48:44 : Running vlog_sim_rpr.xit
898 
MIG: 21:48:44 : IGN:     mig_7series_0 <==>     mig_7series_0
899 
MIG: 21:48:44 : IGN:          <==>         400
900 
MIG: 21:48:44 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
901 
MIG: 03:42:39 : xml_input_file: mig_a.prj
902 
MIG: 03:42:39 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
903 
MIG: 03:42:39 : xml_input_file: mig_a.prj
904 
MIG: 03:42:39 : abs: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
905 
MIG: 03:43:07 : Running customizer.xit
906 
MIG: 03:43:07 : ################# RUNNING MIG INTERACTIVE ###################
907 
MIG: 03:43:07 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /home/stefan/.Xil/Vivado-9962-ws2/coregen/mig_7series_0
908 
MIG: 03:43:07 : synp_flow:  -- synthesis_mode: Other
909 
MIG: 03:43:07 : outputDirectory: /home/stefan/.Xil/Vivado-9962-ws2/coregen/mig_7series_0/_tmp/
910 
MIG: 03:43:07 : vivado_mode: xpg_pa
911 
MIG: 03:43:07 : HDL Language: Verilog
912 
MIG: 03:43:07 : compInfo: false
913 
MIG: 03:43:07 : Vivado Options xc7a100t csg324 -2
914 
MIG: 03:43:07 : 1: xc7a100t 2: csg324 3: -2
915 
MIG: 03:43:07 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-9962-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-9962-ws2/coregen/mig_7series_0/xil_txt.out ...
916 
MIG: 03:45:17 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-9962-ws2/coregen/mig_7series_0/mig_a.prj
917 
MIG: 03:45:17 : Component_Name: mig_7series_0
918 
MIG: 03:45:17 : Moving mig_7series_0.veo ...
919 
MIG: 03:45:17 : Moving mig_7series_0 ...
920 
MIG: 03:45:17 : Moving mig_7series_0_xmdf.tcl ...
921 
MIG: 03:45:17 : Sending back 0
922 
MIG: 03:46:11 : Running synthesis.xit
923 
MIG: 03:46:11 : ################# RUNNING MIG BATCH ###################
924 
MIG: 03:46:11 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_a2/xilinx/Vivado/2013.3/data/ip/xilinx/mig_7series_v2_0... instDirPath: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0
925 
MIG: 03:46:11 : synp_flow:  -- synthesis_mode: Other
926 
MIG: 03:46:11 : outputDirectory: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/_tmp/
927 
MIG: 03:46:11 : vivado_mode: xpg_pa
928 
MIG: 03:46:11 : HDL Language: Verilog
929 
MIG: 03:46:11 : compInfo: false
930 
MIG: 03:46:11 : Vivado Options xc7a100t csg324 -2
931 
MIG: 03:46:11 : 1: xc7a100t 2: csg324 3: -2
932 
MIG: 03:46:11 : Running /drv_a2/xilinx/Vivado/2013.3/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_0/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
933 
MIG: 03:46:33 : XML_INPUT_FILE: /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_a.prj
934 
MIG: 03:46:33 : Component_Name: mig_7series_0
935 
MIG: 03:46:33 : Moving mig_7series_0_xmdf.tcl ...
936 
MIG: 03:46:33 : Moving mig_7series_0 ...
937 
MIG: 03:46:33 : Moving mig_7series_0.veo ...
938 
MIG: 03:46:33 : Added 51  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
939 
MIG: 03:46:33 : Running vlog_synth_rpr.xit
940 
MIG: 03:46:33 : IGN:     mig_7series_0 <==>     mig_7series_0
941 
MIG: 03:46:33 : IGN:          <==>         400
942 
MIG: 03:46:33 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
943 
MIG: 03:46:34 : Running implementation.xit
944 
MIG: 03:46:34 : IGN:     mig_7series_0 <==>     mig_7series_0
945 
MIG: 03:46:34 : IGN:          <==>         400
946 
MIG: 03:46:34 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/*.xdc ..
947 
MIG: 03:46:34 : Running vlog_synth_rpr.xit
948 
MIG: 03:46:34 : IGN:     mig_7series_0 <==>     mig_7series_0
949 
MIG: 03:46:34 : IGN:          <==>         400
950 
MIG: 03:46:34 : Added 1  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0.v ..
951 
MIG: 03:46:36 : Running simulation.xit
952 
MIG: 03:46:36 : IGN:     mig_7series_0 <==>     mig_7series_0
953 
MIG: 03:46:36 : IGN:          <==>         400
954 
MIG: 03:46:36 : Added 50  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.v /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/*/*.vhd /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/example_design/*/*/*.vhd ..
955 
MIG: 03:46:36 : Running vlog_sim_rpr.xit
956 
MIG: 03:46:36 : IGN:     mig_7series_0 <==>     mig_7series_0
957 
MIG: 03:46:36 : IGN:          <==>         400
958 
MIG: 03:46:36 : Added 0  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
959 
MIG: 03:46:36 : Running vlog_sim_rpr.xit
960 
MIG: 03:46:36 : IGN:     mig_7series_0 <==>     mig_7series_0
961 
MIG: 03:46:36 : IGN:          <==>         400
962 
MIG: 03:46:36 : Added 0  files from /drv_s2/usb-fpga/tests/ufm-2.13d-memtest/fpga/memtest.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_sim.v ..
963 
MIG: 19:52:10 : xml_input_file: mig_a.prj
964 
MIG: 19:52:10 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
965 
MIG: 19:52:10 : xml_input_file: mig_a.prj
966 
MIG: 19:52:10 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
967 
MIG: 19:52:10 : In updateAllModelParams
968 
MIG: 19:52:10 : ################# RUNNING MIG BATCH ###################
969 
MIG: 19:52:10 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.2/data/ip/xilinx/mig_7series_v2_1... instDirPath: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0
970 
MIG: 19:52:10 : synp_flow:  -- synthesis_mode: Other
971 
MIG: 19:52:10 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
972 
MIG: 19:52:10 : vivado_mode: xpg_pa
973 
MIG: 19:52:10 :  locked false
974 
MIG: 19:52:10 : HDL Language: Verilog
975 
MIG: 19:52:10 : compInfo: true
976 
MIG: 19:52:10 : Vivado Options xc7a100t csg324 -2
977 
MIG: 19:52:10 : 1: xc7a100t 2: csg324 3: -2
978 
MIG: 19:52:10 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig
979 
MIG: 19:52:10 : xilinx_path: /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE
980 
MIG: 19:52:10 : I am in catch area
981 
MIG: 19:52:10 : Running /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
982 
MIG: 19:52:26 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
983 
MIG: 19:52:26 : Component_Name: mig_7series_0
984 
MIG: 19:52:26 : Moving mig_7series_0_xmdf.tcl ...
985 
MIG: 19:52:26 : Moving mig_7series_0 ...
986 
MIG: 19:52:26 : Moving mig_7series_0.veo ...
987 
MIG: 19:52:26 : XGUI hdlLanguage: Verilog
988 
MIG: 19:52:26 : xgui vivado_mode: xpg_pa
989 
MIG: 19:52:26 : xgui hdlLanguage: Verilog -- hdlExt: v
990 
MIG: 19:52:26 : Reading /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
991 
MIG: 19:52:28 : 1
992 
MIG: 19:52:28 : Inside fn mem: DDR3
993 
MIG: 19:52:28 : QDRII+ Inside fn ui: 100000000
994 
MIG: 19:52:28 :
995 
MIG: 19:52:28 :
996 
MIG: 19:52:28 : 100000000
997 
MIG: 19:52:28 :
998 
MIG: 19:52:28 :  polarity_value: 1
999 
MIG: 19:52:28 :
1000 
MIG: 19:52:28 :
1001 
MIG: 19:52:28 :
1002 
MIG: 19:52:28 :  Valid Param: DDR3_BANK_WIDTH ==> 3
1003 
MIG: 19:52:28 :
1004 
MIG: 19:52:28 :  Valid Param: DDR3_CK_WIDTH ==> 1
1005 
MIG: 19:52:28 :  Invalid Param: DDR3_COL_WIDTH ==> 10
1006 
MIG: 19:52:28 :
1007 
MIG: 19:52:28 :  Valid Param: DDR3_CS_WIDTH ==> 1
1008 
MIG: 19:52:28 :
1009 
MIG: 19:52:28 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
1010 
MIG: 19:52:28 :
1011 
MIG: 19:52:28 :  Valid Param: DDR3_CKE_WIDTH ==> 1
1012 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
1013 
MIG: 19:52:28 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
1014 
MIG: 19:52:28 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
1015 
MIG: 19:52:28 : 2
1016 
MIG: 19:52:28 :  Valid Param: DDR3_DM_WIDTH ==> 2
1017 
MIG: 19:52:28 : 16
1018 
MIG: 19:52:28 :  Valid Param: DDR3_DQ_WIDTH ==> 16
1019 
MIG: 19:52:28 : 2
1020 
MIG: 19:52:28 :  Valid Param: DDR3_DQS_WIDTH ==> 2
1021 
MIG: 19:52:28 :
1022 
MIG: 19:52:28 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
1023 
MIG: 19:52:28 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
1024 
MIG: 19:52:28 :
1025 
MIG: 19:52:28 :  Valid Param: ECC ==> OFF
1026 
MIG: 19:52:28 : 16
1027 
MIG: 19:52:28 :  Valid Param: DDR3_DATA_WIDTH ==> 16
1028 
MIG: 19:52:28 :  Invalid Param: ECC_TEST ==> "OFF"
1029 
MIG: 19:52:28 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
1030 
MIG: 19:52:28 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
1031 
MIG: 19:52:28 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
1032 
MIG: 19:52:28 :  Invalid Param: DDR3_RANKS ==> 1
1033 
MIG: 19:52:28 :
1034 
MIG: 19:52:28 :  Valid Param: DDR3_ODT_WIDTH ==> 1
1035 
MIG: 19:52:28 :
1036 
MIG: 19:52:28 :  Valid Param: DDR3_ROW_WIDTH ==> 14
1037 
MIG: 19:52:28 : 28
1038 
MIG: 19:52:28 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
1039 
MIG: 19:52:28 : 0
1040 
MIG: 19:52:28 :  Valid Param: DDR3_USE_CS_PORT ==> 0
1041 
MIG: 19:52:28 :
1042 
MIG: 19:52:28 :  Valid Param: DDR3_USE_DM_PORT ==> 1
1043 
MIG: 19:52:28 :
1044 
MIG: 19:52:28 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
1045 
MIG: 19:52:28 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
1046 
MIG: 19:52:28 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
1047 
MIG: 19:52:28 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
1048 
MIG: 19:52:28 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
1049 
MIG: 19:52:28 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
1050 
MIG: 19:52:28 :  Invalid Param: DDR3_AL ==> "0"
1051 
MIG: 19:52:28 :  Invalid Param: DDR3_nAL ==> 0
1052 
MIG: 19:52:28 :  Invalid Param: DDR3_BURST_MODE ==> "8"
1053 
MIG: 19:52:28 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
1054 
MIG: 19:52:28 :  Invalid Param: DDR3_CL ==> 6
1055 
MIG: 19:52:28 :  Invalid Param: DDR3_CWL ==> 5
1056 
MIG: 19:52:28 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
1057 
MIG: 19:52:28 :  Invalid Param: DDR3_RTT_NOM ==> "40"
1058 
MIG: 19:52:28 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
1059 
MIG: 19:52:28 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
1060 
MIG: 19:52:28 :
1061 
MIG: 19:52:28 :  Valid Param: DDR3_REG_CTRL ==> OFF
1062 
MIG: 19:52:28 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
1063 
MIG: 19:52:28 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
1064 
MIG: 19:52:28 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 2500
1065 
MIG: 19:52:28 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 2
1066 
MIG: 19:52:28 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
1067 
MIG: 19:52:28 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
1068 
MIG: 19:52:28 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
1069 
MIG: 19:52:28 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
1070 
MIG: 19:52:28 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
1071 
MIG: 19:52:28 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
1072 
MIG: 19:52:28 :  Invalid Param: DDR3_tCKE ==> 5000
1073 
MIG: 19:52:28 :  Invalid Param: DDR3_tFAW ==> 40000
1074 
MIG: 19:52:28 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
1075 
MIG: 19:52:28 :  Invalid Param: DDR3_tRAS ==> 35000
1076 
MIG: 19:52:28 :  Invalid Param: DDR3_tRCD ==> 13750
1077 
MIG: 19:52:28 :  Invalid Param: DDR3_tREFI ==> 7800000
1078 
MIG: 19:52:28 :  Invalid Param: DDR3_tRFC ==> 160000
1079 
MIG: 19:52:28 :  Invalid Param: DDR3_tRP ==> 13750
1080 
MIG: 19:52:28 :  Invalid Param: DDR3_tRRD ==> 7500
1081 
MIG: 19:52:28 :  Invalid Param: DDR3_tRTP ==> 7500
1082 
MIG: 19:52:28 :  Invalid Param: DDR3_tWTR ==> 7500
1083 
MIG: 19:52:28 :  Invalid Param: DDR3_tZQI ==> 128_000_000
1084 
MIG: 19:52:28 :  Invalid Param: DDR3_tZQCS ==> 64
1085 
MIG: 19:52:28 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
1086 
MIG: 19:52:28 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
1087 
MIG: 19:52:28 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
1088 
MIG: 19:52:28 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
1089 
MIG: 19:52:28 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
1090 
MIG: 19:52:28 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
1091 
MIG: 19:52:28 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
1092 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
1093 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
1094 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
1095 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
1096 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
1097 
MIG: 19:52:28 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_CFF_3DF_2FF
1098 
MIG: 19:52:28 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
1099 
MIG: 19:52:28 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
1100 
MIG: 19:52:28 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
1101 
MIG: 19:52:28 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038
1102 
MIG: 19:52:28 :  Invalid Param: DDR3_BANK_MAP ==> 36'h033_02A_032
1103 
MIG: 19:52:28 :  Invalid Param: DDR3_CAS_MAP ==> 12'h020
1104 
MIG: 19:52:28 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
1105 
MIG: 19:52:28 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_02B
1106 
MIG: 19:52:28 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
1107 
MIG: 19:52:28 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
1108 
MIG: 19:52:28 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
1109 
MIG: 19:52:28 :  Invalid Param: DDR3_RAS_MAP ==> 12'h021
1110 
MIG: 19:52:28 :  Invalid Param: DDR3_WE_MAP ==> 12'h022
1111 
MIG: 19:52:28 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
1112 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h016_018_014_019_010_017_011_013
1113 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h003_002_005_004_001_006_000_007
1114 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
1115 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
1116 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
1117 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
1118 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
1119 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
1120 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
1121 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
1122 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
1123 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
1124 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
1125 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
1126 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
1127 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
1128 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
1129 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
1130 
MIG: 19:52:28 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_012
1131 
MIG: 19:52:28 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
1132 
MIG: 19:52:28 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
1133 
MIG: 19:52:28 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
1134 
MIG: 19:52:28 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
1135 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
1136 
MIG: 19:52:28 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
1137 
MIG: 19:52:28 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
1138 
MIG: 19:52:28 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
1139 
MIG: 19:52:28 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
1140 
MIG: 19:52:28 :  Invalid Param: DDR3_WRLVL ==> "ON"
1141 
MIG: 19:52:28 :  Invalid Param: DDR3_ORDERING ==> "NORM"
1142 
MIG: 19:52:28 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
1143 
MIG: 19:52:28 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
1144 
MIG: 19:52:28 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
1145 
MIG: 19:52:28 :  Invalid Param: DDR3_TCQ ==> 100
1146 
MIG: 19:52:28 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
1147 
MIG: 19:52:28 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
1148 
MIG: 19:52:28 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
1149 
MIG: 19:52:28 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
1150 
MIG: 19:52:28 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
1151 
MIG: 19:52:28 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
1152 
MIG: 19:52:28 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
1153 
MIG: 19:52:28 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
1154 
MIG: 19:52:28 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
1155 
MIG: 19:52:28 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
1156 
MIG: 19:52:28 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
1157 
MIG: 19:52:28 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
1158 
MIG: 19:52:28 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
1159 
MIG: 19:52:28 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
1160 
MIG: 19:52:28 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
1161 
MIG: 19:52:28 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
1162 
MIG: 19:52:28 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
1163 
MIG: 19:52:28 :  Invalid Param: DDR3_tCK ==> 2500
1164 
MIG: 19:52:28 : 4
1165 
MIG: 19:52:28 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
1166 
MIG: 19:52:28 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
1167 
MIG: 19:52:28 :
1168 
MIG: 19:52:28 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
1169 
MIG: 19:52:28 :
1170 
MIG: 19:52:28 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
1171 
MIG: 19:52:28 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
1172 
MIG: 19:52:28 : NOBUF
1173 
MIG: 19:52:28 : NOBUF
1174 
MIG: 19:52:28 :
1175 
MIG: 19:52:28 : Same Interface
1176 
MIG: 19:56:36 : Running synthesis.xit
1177 
MIG: 19:56:36 : IGN:     mig_7series_0 <==>     mig_7series_0
1178 
MIG: 19:56:36 : ERR:     2.0 <==>     2.1
1179 
MIG: 19:56:36 : ################# RUNNING MIG BATCH ###################
1180 
MIG: 19:56:36 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.2/data/ip/xilinx/mig_7series_v2_1... instDirPath: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0
1181 
MIG: 19:56:36 : synp_flow:  -- synthesis_mode: Other
1182 
MIG: 19:56:36 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1183 
MIG: 19:56:36 : vivado_mode: xpg_pa
1184 
MIG: 19:56:36 :  locked false
1185 
MIG: 19:56:36 : HDL Language: Verilog
1186 
MIG: 19:56:36 : compInfo: false
1187 
MIG: 19:56:36 : Vivado Options xc7a100t csg324 -2
1188 
MIG: 19:56:36 : 1: xc7a100t 2: csg324 3: -2
1189 
MIG: 19:56:36 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig
1190 
MIG: 19:56:36 : xilinx_path: /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE
1191 
MIG: 19:56:36 : I am in catch area
1192 
MIG: 19:56:36 : Running /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1193 
MIG: 19:56:52 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1194 
MIG: 19:56:52 : Component_Name: mig_7series_0
1195 
MIG: 19:56:52 : Moving mig_7series_0_xmdf.tcl ...
1196 
MIG: 19:56:52 : Moving mig_7series_0 ...
1197 
MIG: 19:56:52 : Moving mig_7series_0.veo ...
1198 
MIG: 19:56:53 : Running implementation.xit
1199 
MIG: 19:56:53 : IGN:     mig_7series_0 <==>     mig_7series_0
1200 
MIG: 19:56:53 : ERR:     2.0 <==>     2.1
1201 
MIG: 19:56:53 : ################# RUNNING MIG BATCH ###################
1202 
MIG: 19:56:53 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.2/data/ip/xilinx/mig_7series_v2_1... instDirPath: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0
1203 
MIG: 19:56:53 : synp_flow:  -- synthesis_mode: Other
1204 
MIG: 19:56:53 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1205 
MIG: 19:56:53 : vivado_mode: xpg_pa
1206 
MIG: 19:56:53 :  locked false
1207 
MIG: 19:56:53 : HDL Language: Verilog
1208 
MIG: 19:56:53 : compInfo: false
1209 
MIG: 19:56:53 : Vivado Options xc7a100t csg324 -2
1210 
MIG: 19:56:53 : 1: xc7a100t 2: csg324 3: -2
1211 
MIG: 19:56:53 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig
1212 
MIG: 19:56:53 : xilinx_path: /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE
1213 
MIG: 19:56:53 : I am in catch area
1214 
MIG: 19:56:53 : Running /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1215 
MIG: 19:57:10 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1216 
MIG: 19:57:10 : Component_Name: mig_7series_0
1217 
MIG: 19:57:10 : Moving mig_7series_0_xmdf.tcl ...
1218 
MIG: 19:57:10 : Moving mig_7series_0 ...
1219 
MIG: 19:57:10 : Moving mig_7series_0.veo ...
1220 
MIG: 19:57:11 : Running vlog_synth_rpr.xit
1221 
MIG: 19:57:11 : IGN:     mig_7series_0 <==>     mig_7series_0
1222 
MIG: 19:57:11 : ERR:     2.0 <==>     2.1
1223 
MIG: 19:57:11 : ################# RUNNING MIG BATCH ###################
1224 
MIG: 19:57:11 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.2/data/ip/xilinx/mig_7series_v2_1... instDirPath: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0
1225 
MIG: 19:57:11 : synp_flow:  -- synthesis_mode: Other
1226 
MIG: 19:57:11 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1227 
MIG: 19:57:11 : vivado_mode: xpg_pa
1228 
MIG: 19:57:11 :  locked false
1229 
MIG: 19:57:11 : HDL Language: Verilog
1230 
MIG: 19:57:11 : compInfo: false
1231 
MIG: 19:57:11 : Vivado Options xc7a100t csg324 -2
1232 
MIG: 19:57:11 : 1: xc7a100t 2: csg324 3: -2
1233 
MIG: 19:57:11 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig
1234 
MIG: 19:57:11 : xilinx_path: /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE
1235 
MIG: 19:57:11 : I am in catch area
1236 
MIG: 19:57:11 : Running /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1237 
MIG: 19:57:28 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1238 
MIG: 19:57:28 : Component_Name: mig_7series_0
1239 
MIG: 19:57:28 : Moving mig_7series_0_xmdf.tcl ...
1240 
MIG: 19:57:28 : Moving mig_7series_0 ...
1241 
MIG: 19:57:28 : Moving mig_7series_0.veo ...
1242 
MIG: 19:57:29 : Running simulation.xit
1243 
MIG: 19:57:29 : IGN:     mig_7series_0 <==>     mig_7series_0
1244 
MIG: 19:57:29 : ERR:     2.0 <==>     2.1
1245 
MIG: 19:57:29 : ################# RUNNING MIG BATCH ###################
1246 
MIG: 19:57:29 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.2/data/ip/xilinx/mig_7series_v2_1... instDirPath: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0
1247 
MIG: 19:57:29 : synp_flow:  -- synthesis_mode: Other
1248 
MIG: 19:57:29 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1249 
MIG: 19:57:29 : vivado_mode: xpg_pa
1250 
MIG: 19:57:29 :  locked false
1251 
MIG: 19:57:29 : HDL Language: Verilog
1252 
MIG: 19:57:29 : compInfo: false
1253 
MIG: 19:57:29 : Vivado Options xc7a100t csg324 -2
1254 
MIG: 19:57:29 : 1: xc7a100t 2: csg324 3: -2
1255 
MIG: 19:57:29 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig
1256 
MIG: 19:57:29 : xilinx_path: /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE
1257 
MIG: 19:57:29 : I am in catch area
1258 
MIG: 19:57:29 : Running /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1259 
MIG: 19:57:45 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1260 
MIG: 19:57:45 : Component_Name: mig_7series_0
1261 
MIG: 19:57:45 : Moving mig_7series_0_xmdf.tcl ...
1262 
MIG: 19:57:45 : Moving mig_7series_0 ...
1263 
MIG: 19:57:45 : Moving mig_7series_0.veo ...
1264 
MIG: 19:57:46 : Running vlog_sim_rpr.xit .. PRASAD DBG1
1265 
MIG: 19:57:46 : IGN:     mig_7series_0 <==>     mig_7series_0
1266 
MIG: 19:57:46 : ERR:     2.0 <==>     2.1
1267 
MIG: 19:57:46 : ################# RUNNING MIG BATCH ###################
1268 
MIG: 19:57:46 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.2/data/ip/xilinx/mig_7series_v2_1... instDirPath: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0
1269 
MIG: 19:57:46 : synp_flow:  -- synthesis_mode: Other
1270 
MIG: 19:57:46 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1271 
MIG: 19:57:46 : vivado_mode: xpg_pa
1272 
MIG: 19:57:46 :  locked false
1273 
MIG: 19:57:46 : HDL Language: Verilog
1274 
MIG: 19:57:46 : compInfo: false
1275 
MIG: 19:57:46 : Vivado Options xc7a100t csg324 -2
1276 
MIG: 19:57:46 : 1: xc7a100t 2: csg324 3: -2
1277 
MIG: 19:57:46 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig
1278 
MIG: 19:57:46 : xilinx_path: /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE
1279 
MIG: 19:57:46 : I am in catch area
1280 
MIG: 19:57:46 : Running /drv_s2/xilinx/Vivado/2014.2/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_1/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1281 
MIG: 19:58:00 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/usb-fpga-2.13/2.13d/memfifo/fpga/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1282 
MIG: 19:58:00 : Component_Name: mig_7series_0
1283 
MIG: 19:58:00 : Moving mig_7series_0_xmdf.tcl ...
1284 
MIG: 19:58:00 : Moving mig_7series_0 ...
1285 
MIG: 19:58:00 : Moving mig_7series_0.veo ...
1286 
MIG: 21:37:43 : xml_input_file: mig_a.prj
1287 
MIG: 21:37:43 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1288 
MIG: 21:37:43 : xml_input_file: mig_a.prj
1289 
MIG: 21:37:43 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1290 
MIG: 21:37:43 : In updateAllModelParams
1291 
MIG: 21:37:43 : ################# RUNNING MIG BATCH ###################
1292 
MIG: 21:37:43 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
1293 
MIG: 21:37:43 : synp_flow:  -- synthesis_mode: Other
1294 
MIG: 21:37:43 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1295 
MIG: 21:37:43 : vivado_mode: xpg_pa
1296 
MIG: 21:37:43 :  locked false
1297 
MIG: 21:37:43 : HDL Language: Verilog
1298 
MIG: 21:37:43 : compInfo: true
1299 
MIG: 21:37:43 : Vivado Options xc7a100t csg324 -2
1300 
MIG: 21:37:43 : 1: xc7a100t 2: csg324 3: -2
1301 
MIG: 21:37:43 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
1302 
MIG: 21:37:43 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
1303 
MIG: 21:37:43 : I am in catch area
1304 
MIG: 21:37:43 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1305 
MIG: 21:37:59 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1306 
MIG: 21:37:59 : Component_Name: mig_7series_0
1307 
MIG: 21:37:59 : Moving mig_7series_0_xmdf.tcl ...
1308 
MIG: 21:37:59 : Moving mig_7series_0 ...
1309 
MIG: 21:37:59 : Moving mig_7series_0.veo ...
1310 
MIG: 21:37:59 : XGUI hdlLanguage: Verilog
1311 
MIG: 21:37:59 : xgui vivado_mode: xpg_pa
1312 
MIG: 21:37:59 : xgui hdlLanguage: Verilog -- hdlExt: v
1313 
MIG: 21:37:59 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
1314 
MIG: 21:38:00 : 1
1315 
MIG: 21:38:00 : Inside fn mem: DDR3
1316 
MIG: 21:38:00 : QDRII+ Inside fn ui: 100000000
1317 
MIG: 21:38:00 : cntrl:  memtype: DDR3
1318 
MIG: 21:38:00 : 800
1319 
MIG: 21:38:00 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800
1320 
MIG: 21:38:00 :
1321 
MIG: 21:38:00 :
1322 
MIG: 21:38:00 : 100000000
1323 
MIG: 21:38:00 :
1324 
MIG: 21:38:00 :  polarity_value: 1
1325 
MIG: 21:38:00 :
1326 
MIG: 21:38:00 :
1327 
MIG: 21:38:00 : cntrl:  memtype: DDR3
1328 
MIG: 21:38:00 :
1329 
MIG: 21:38:00 :  Valid Param: DDR3_BANK_WIDTH ==> 3
1330 
MIG: 21:38:00 :
1331 
MIG: 21:38:00 :  Valid Param: DDR3_CK_WIDTH ==> 1
1332 
MIG: 21:38:00 :  Invalid Param: DDR3_COL_WIDTH ==> 10
1333 
MIG: 21:38:00 :
1334 
MIG: 21:38:00 :  Valid Param: DDR3_CS_WIDTH ==> 1
1335 
MIG: 21:38:00 :
1336 
MIG: 21:38:00 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
1337 
MIG: 21:38:00 :
1338 
MIG: 21:38:00 :  Valid Param: DDR3_CKE_WIDTH ==> 1
1339 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
1340 
MIG: 21:38:00 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
1341 
MIG: 21:38:00 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
1342 
MIG: 21:38:00 : 2
1343 
MIG: 21:38:00 :  Valid Param: DDR3_DM_WIDTH ==> 2
1344 
MIG: 21:38:00 : 16
1345 
MIG: 21:38:00 :  Valid Param: DDR3_DQ_WIDTH ==> 16
1346 
MIG: 21:38:00 : 2
1347 
MIG: 21:38:00 :  Valid Param: DDR3_DQS_WIDTH ==> 2
1348 
MIG: 21:38:00 :
1349 
MIG: 21:38:00 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
1350 
MIG: 21:38:00 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
1351 
MIG: 21:38:00 :
1352 
MIG: 21:38:00 :  Valid Param: ECC ==> OFF
1353 
MIG: 21:38:00 : 16
1354 
MIG: 21:38:00 :  Valid Param: DDR3_DATA_WIDTH ==> 16
1355 
MIG: 21:38:00 :  Invalid Param: ECC_TEST ==> "OFF"
1356 
MIG: 21:38:00 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
1357 
MIG: 21:38:00 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
1358 
MIG: 21:38:00 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
1359 
MIG: 21:38:00 :  Invalid Param: DDR3_RANKS ==> 1
1360 
MIG: 21:38:00 :
1361 
MIG: 21:38:00 :  Valid Param: DDR3_ODT_WIDTH ==> 1
1362 
MIG: 21:38:00 :
1363 
MIG: 21:38:00 :  Valid Param: DDR3_ROW_WIDTH ==> 14
1364 
MIG: 21:38:00 : 28
1365 
MIG: 21:38:00 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
1366 
MIG: 21:38:00 : 0
1367 
MIG: 21:38:00 :  Valid Param: DDR3_USE_CS_PORT ==> 0
1368 
MIG: 21:38:00 :
1369 
MIG: 21:38:00 :  Valid Param: DDR3_USE_DM_PORT ==> 1
1370 
MIG: 21:38:00 :
1371 
MIG: 21:38:00 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
1372 
MIG: 21:38:00 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
1373 
MIG: 21:38:00 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
1374 
MIG: 21:38:00 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
1375 
MIG: 21:38:00 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
1376 
MIG: 21:38:00 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
1377 
MIG: 21:38:00 :  Invalid Param: DDR3_AL ==> "0"
1378 
MIG: 21:38:00 :  Invalid Param: DDR3_nAL ==> 0
1379 
MIG: 21:38:00 :  Invalid Param: DDR3_BURST_MODE ==> "8"
1380 
MIG: 21:38:00 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
1381 
MIG: 21:38:00 :  Invalid Param: DDR3_CL ==> 6
1382 
MIG: 21:38:00 :  Invalid Param: DDR3_CWL ==> 5
1383 
MIG: 21:38:00 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
1384 
MIG: 21:38:00 :  Invalid Param: DDR3_RTT_NOM ==> "40"
1385 
MIG: 21:38:00 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
1386 
MIG: 21:38:00 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
1387 
MIG: 21:38:00 :
1388 
MIG: 21:38:00 :  Valid Param: DDR3_REG_CTRL ==> OFF
1389 
MIG: 21:38:00 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
1390 
MIG: 21:38:00 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
1391 
MIG: 21:38:00 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 2500
1392 
MIG: 21:38:00 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 2
1393 
MIG: 21:38:00 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
1394 
MIG: 21:38:00 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
1395 
MIG: 21:38:00 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
1396 
MIG: 21:38:00 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
1397 
MIG: 21:38:00 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
1398 
MIG: 21:38:00 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
1399 
MIG: 21:38:00 :  Invalid Param: DDR3_MMCM_VCO ==> 800
1400 
MIG: 21:38:00 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
1401 
MIG: 21:38:00 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
1402 
MIG: 21:38:00 :  Invalid Param: DDR3_tCKE ==> 5000
1403 
MIG: 21:38:00 :  Invalid Param: DDR3_tFAW ==> 40000
1404 
MIG: 21:38:00 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
1405 
MIG: 21:38:00 :  Invalid Param: DDR3_tRAS ==> 35000
1406 
MIG: 21:38:00 :  Invalid Param: DDR3_tRCD ==> 13750
1407 
MIG: 21:38:00 :  Invalid Param: DDR3_tREFI ==> 7800000
1408 
MIG: 21:38:00 :  Invalid Param: DDR3_tRFC ==> 160000
1409 
MIG: 21:38:00 :  Invalid Param: DDR3_tRP ==> 13750
1410 
MIG: 21:38:00 :  Invalid Param: DDR3_tRRD ==> 7500
1411 
MIG: 21:38:00 :  Invalid Param: DDR3_tRTP ==> 7500
1412 
MIG: 21:38:00 :  Invalid Param: DDR3_tWTR ==> 7500
1413 
MIG: 21:38:00 :  Invalid Param: DDR3_tZQI ==> 128_000_000
1414 
MIG: 21:38:00 :  Invalid Param: DDR3_tZQCS ==> 64
1415 
MIG: 21:38:00 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
1416 
MIG: 21:38:00 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
1417 
MIG: 21:38:00 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
1418 
MIG: 21:38:00 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
1419 
MIG: 21:38:00 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
1420 
MIG: 21:38:00 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
1421 
MIG: 21:38:00 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
1422 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
1423 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
1424 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
1425 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
1426 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
1427 
MIG: 21:38:00 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_CFF_3DF_2FF
1428 
MIG: 21:38:00 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
1429 
MIG: 21:38:00 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
1430 
MIG: 21:38:00 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
1431 
MIG: 21:38:00 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038
1432 
MIG: 21:38:00 :  Invalid Param: DDR3_BANK_MAP ==> 36'h033_02A_032
1433 
MIG: 21:38:00 :  Invalid Param: DDR3_CAS_MAP ==> 12'h020
1434 
MIG: 21:38:00 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
1435 
MIG: 21:38:00 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_02B
1436 
MIG: 21:38:00 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
1437 
MIG: 21:38:00 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
1438 
MIG: 21:38:00 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
1439 
MIG: 21:38:00 :  Invalid Param: DDR3_RAS_MAP ==> 12'h021
1440 
MIG: 21:38:00 :  Invalid Param: DDR3_WE_MAP ==> 12'h022
1441 
MIG: 21:38:00 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
1442 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h016_018_014_019_010_017_011_013
1443 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h003_002_005_004_001_006_000_007
1444 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
1445 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
1446 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
1447 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
1448 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
1449 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
1450 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
1451 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
1452 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
1453 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
1454 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
1455 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
1456 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
1457 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
1458 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
1459 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
1460 
MIG: 21:38:00 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_012
1461 
MIG: 21:38:00 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
1462 
MIG: 21:38:00 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
1463 
MIG: 21:38:00 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
1464 
MIG: 21:38:00 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
1465 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
1466 
MIG: 21:38:00 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
1467 
MIG: 21:38:00 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
1468 
MIG: 21:38:00 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
1469 
MIG: 21:38:00 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
1470 
MIG: 21:38:00 :  Invalid Param: DDR3_WRLVL ==> "ON"
1471 
MIG: 21:38:00 :  Invalid Param: DDR3_ORDERING ==> "NORM"
1472 
MIG: 21:38:00 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
1473 
MIG: 21:38:00 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
1474 
MIG: 21:38:00 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
1475 
MIG: 21:38:00 :  Invalid Param: DDR3_TCQ ==> 100
1476 
MIG: 21:38:00 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
1477 
MIG: 21:38:00 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
1478 
MIG: 21:38:00 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
1479 
MIG: 21:38:00 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
1480 
MIG: 21:38:00 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
1481 
MIG: 21:38:00 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
1482 
MIG: 21:38:00 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
1483 
MIG: 21:38:00 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
1484 
MIG: 21:38:00 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
1485 
MIG: 21:38:00 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
1486 
MIG: 21:38:00 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
1487 
MIG: 21:38:00 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
1488 
MIG: 21:38:00 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
1489 
MIG: 21:38:00 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
1490 
MIG: 21:38:00 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
1491 
MIG: 21:38:00 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
1492 
MIG: 21:38:00 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
1493 
MIG: 21:38:00 :  Invalid Param: DDR3_tCK ==> 2500
1494 
MIG: 21:38:00 : 4
1495 
MIG: 21:38:00 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
1496 
MIG: 21:38:00 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
1497 
MIG: 21:38:00 :
1498 
MIG: 21:38:00 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
1499 
MIG: 21:38:00 :
1500 
MIG: 21:38:00 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
1501 
MIG: 21:38:00 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
1502 
MIG: 21:38:00 : NOBUF
1503 
MIG: 21:38:00 : NOBUF
1504 
MIG: 21:38:00 :
1505 
MIG: 21:38:00 : Same Interface
1506 
MIG: 21:38:13 : Running synthesis.xit
1507 
MIG: 21:38:13 : IGN:     mig_7series_0 <==>     mig_7series_0
1508 
MIG: 21:38:13 : ERR:     2.0 <==>     2.3
1509 
MIG: 21:38:13 : ################# RUNNING MIG BATCH ###################
1510 
MIG: 21:38:13 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
1511 
MIG: 21:38:13 : synp_flow:  -- synthesis_mode: Other
1512 
MIG: 21:38:13 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1513 
MIG: 21:38:13 : vivado_mode: xpg_pa
1514 
MIG: 21:38:13 :  locked false
1515 
MIG: 21:38:13 : HDL Language: Verilog
1516 
MIG: 21:38:13 : compInfo: false
1517 
MIG: 21:38:13 : Vivado Options xc7a100t csg324 -2
1518 
MIG: 21:38:13 : 1: xc7a100t 2: csg324 3: -2
1519 
MIG: 21:38:13 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
1520 
MIG: 21:38:13 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
1521 
MIG: 21:38:13 : I am in catch area
1522 
MIG: 21:38:13 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1523 
MIG: 21:38:27 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1524 
MIG: 21:38:27 : Component_Name: mig_7series_0
1525 
MIG: 21:38:27 : Moving mig_7series_0_xmdf.tcl ...
1526 
MIG: 21:38:27 : Moving mig_7series_0 ...
1527 
MIG: 21:38:27 : Moving mig_7series_0.veo ...
1528 
MIG: 21:38:27 : Running vlog_synth_rpr.xit
1529 
MIG: 21:38:27 : IGN:     mig_7series_0 <==>     mig_7series_0
1530 
MIG: 21:38:27 : ERR:     2.0 <==>     2.3
1531 
MIG: 21:38:27 : ################# RUNNING MIG BATCH ###################
1532 
MIG: 21:38:27 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
1533 
MIG: 21:38:27 : synp_flow:  -- synthesis_mode: Other
1534 
MIG: 21:38:27 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1535 
MIG: 21:38:27 : vivado_mode: xpg_pa
1536 
MIG: 21:38:27 :  locked false
1537 
MIG: 21:38:27 : HDL Language: Verilog
1538 
MIG: 21:38:27 : compInfo: false
1539 
MIG: 21:38:27 : Vivado Options xc7a100t csg324 -2
1540 
MIG: 21:38:27 : 1: xc7a100t 2: csg324 3: -2
1541 
MIG: 21:38:27 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
1542 
MIG: 21:38:27 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
1543 
MIG: 21:38:27 : I am in catch area
1544 
MIG: 21:38:27 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1545 
MIG: 21:38:44 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1546 
MIG: 21:38:44 : Component_Name: mig_7series_0
1547 
MIG: 21:38:44 : Moving mig_7series_0_xmdf.tcl ...
1548 
MIG: 21:38:44 : Moving mig_7series_0 ...
1549 
MIG: 21:38:44 : Moving mig_7series_0.veo ...
1550 
MIG: 21:38:45 : Running simulation.xit
1551 
MIG: 21:38:45 : IGN:     mig_7series_0 <==>     mig_7series_0
1552 
MIG: 21:38:45 : ERR:     2.0 <==>     2.3
1553 
MIG: 21:38:45 : ################# RUNNING MIG BATCH ###################
1554 
MIG: 21:38:45 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
1555 
MIG: 21:38:45 : synp_flow:  -- synthesis_mode: Other
1556 
MIG: 21:38:45 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1557 
MIG: 21:38:45 : vivado_mode: xpg_pa
1558 
MIG: 21:38:45 :  locked false
1559 
MIG: 21:38:45 : HDL Language: Verilog
1560 
MIG: 21:38:45 : compInfo: false
1561 
MIG: 21:38:45 : Vivado Options xc7a100t csg324 -2
1562 
MIG: 21:38:45 : 1: xc7a100t 2: csg324 3: -2
1563 
MIG: 21:38:45 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
1564 
MIG: 21:38:45 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
1565 
MIG: 21:38:45 : I am in catch area
1566 
MIG: 21:38:45 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1567 
MIG: 21:38:59 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1568 
MIG: 21:38:59 : Component_Name: mig_7series_0
1569 
MIG: 21:38:59 : Moving mig_7series_0_xmdf.tcl ...
1570 
MIG: 21:38:59 : Moving mig_7series_0 ...
1571 
MIG: 21:38:59 : Moving mig_7series_0.veo ...
1572 
MIG: 21:39:00 : Running vlog_sim_rpr.xit .. PRASAD DBG1
1573 
MIG: 21:39:00 : IGN:     mig_7series_0 <==>     mig_7series_0
1574 
MIG: 21:39:00 : ERR:     2.0 <==>     2.3
1575 
MIG: 21:39:00 : ################# RUNNING MIG BATCH ###################
1576 
MIG: 21:39:00 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
1577 
MIG: 21:39:00 : synp_flow:  -- synthesis_mode: Other
1578 
MIG: 21:39:00 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1579 
MIG: 21:39:00 : vivado_mode: xpg_pa
1580 
MIG: 21:39:00 :  locked false
1581 
MIG: 21:39:00 : HDL Language: Verilog
1582 
MIG: 21:39:00 : compInfo: false
1583 
MIG: 21:39:00 : Vivado Options xc7a100t csg324 -2
1584 
MIG: 21:39:00 : 1: xc7a100t 2: csg324 3: -2
1585 
MIG: 21:39:00 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
1586 
MIG: 21:39:00 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
1587 
MIG: 21:39:00 : I am in catch area
1588 
MIG: 21:39:00 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1589 
MIG: 21:39:14 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1590 
MIG: 21:39:14 : Component_Name: mig_7series_0
1591 
MIG: 21:39:14 : Moving mig_7series_0_xmdf.tcl ...
1592 
MIG: 21:39:14 : Moving mig_7series_0 ...
1593 
MIG: 21:39:14 : Moving mig_7series_0.veo ...
1594 
MIG: 21:39:14 : Running implementation.xit
1595 
MIG: 21:39:14 : IGN:     mig_7series_0 <==>     mig_7series_0
1596 
MIG: 21:39:14 : ERR:     2.0 <==>     2.3
1597 
MIG: 21:39:14 : ################# RUNNING MIG BATCH ###################
1598 
MIG: 21:39:14 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
1599 
MIG: 21:39:14 : synp_flow:  -- synthesis_mode: Other
1600 
MIG: 21:39:14 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1601 
MIG: 21:39:14 : vivado_mode: xpg_pa
1602 
MIG: 21:39:14 :  locked false
1603 
MIG: 21:39:14 : HDL Language: Verilog
1604 
MIG: 21:39:14 : compInfo: false
1605 
MIG: 21:39:14 : Vivado Options xc7a100t csg324 -2
1606 
MIG: 21:39:14 : 1: xc7a100t 2: csg324 3: -2
1607 
MIG: 21:39:14 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
1608 
MIG: 21:39:14 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
1609 
MIG: 21:39:14 : I am in catch area
1610 
MIG: 21:39:14 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1611 
MIG: 21:39:28 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1612 
MIG: 21:39:28 : Component_Name: mig_7series_0
1613 
MIG: 21:39:28 : Moving mig_7series_0_xmdf.tcl ...
1614 
MIG: 21:39:28 : Moving mig_7series_0 ...
1615 
MIG: 21:39:28 : Moving mig_7series_0.veo ...
1616 
MIG: 21:39:58 : xml_input_file: mig_a.prj
1617 
MIG: 21:39:58 : Absolute path of xml_input_file: mig_a.prj
1618 
MIG: 21:39:58 : xml_input_file: mig_a.prj
1619 
MIG: 21:39:58 : Absolute path of xml_input_file: mig_a.prj
1620 
MIG: 21:39:58 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1621 
MIG: 21:39:58 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1622 
MIG: 21:39:58 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1623 
MIG: 21:39:58 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1624 
MIG: 21:39:58 : In updateAllModelParams
1625 
MIG: 21:39:58 : IGN:     mig_7series_0 <==>     mig_7series_0
1626 
MIG: 21:39:58 : ERR:     2.0 <==>     2.3
1627 
MIG: 21:39:58 : ################# RUNNING MIG BATCH ###################
1628 
MIG: 21:39:58 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
1629 
MIG: 21:39:58 : synp_flow:  -- synthesis_mode: Other
1630 
MIG: 21:39:58 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
1631 
MIG: 21:39:58 : vivado_mode: xpg_pa
1632 
MIG: 21:39:58 :  locked false
1633 
MIG: 21:39:58 : HDL Language: Verilog
1634 
MIG: 21:39:58 : compInfo: true
1635 
MIG: 21:39:58 : Vivado Options xc7a100t csg324 -2
1636 
MIG: 21:39:58 : 1: xc7a100t 2: csg324 3: -2
1637 
MIG: 21:39:58 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
1638 
MIG: 21:39:58 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
1639 
MIG: 21:39:58 : I am in catch area
1640 
MIG: 21:39:58 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
1641 
MIG: 21:40:12 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_a.prj
1642 
MIG: 21:40:12 : Component_Name: mig_7series_0
1643 
MIG: 21:40:12 : Moving mig_7series_0_xmdf.tcl ...
1644 
MIG: 21:40:12 : Moving mig_7series_0 ...
1645 
MIG: 21:40:12 : Moving mig_7series_0.veo ...
1646 
MIG: 21:40:12 : XGUI hdlLanguage: Verilog
1647 
MIG: 21:40:12 : xgui vivado_mode: xpg_pa
1648 
MIG: 21:40:12 : xgui hdlLanguage: Verilog -- hdlExt: v
1649 
MIG: 21:40:12 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
1650 
MIG: 21:40:13 :
1651 
MIG: 21:40:13 : Inside fn mem: DDR3
1652 
MIG: 21:40:13 : QDRII+ Inside fn ui: 100000000
1653 
MIG: 21:40:13 : cntrl:  memtype: DDR3
1654 
MIG: 21:40:13 :
1655 
MIG: 21:40:13 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800
1656 
MIG: 21:40:13 :
1657 
MIG: 21:40:13 :
1658 
MIG: 21:40:13 :
1659 
MIG: 21:40:13 :
1660 
MIG: 21:40:13 :  polarity_value: 1
1661 
MIG: 21:40:13 :
1662 
MIG: 21:40:13 :
1663 
MIG: 21:40:13 : cntrl:  memtype: DDR3
1664 
MIG: 21:40:13 :
1665 
MIG: 21:40:13 :  Valid Param: DDR3_BANK_WIDTH ==> 3
1666 
MIG: 21:40:13 :
1667 
MIG: 21:40:13 :  Valid Param: DDR3_CK_WIDTH ==> 1
1668 
MIG: 21:40:13 :  Invalid Param: DDR3_COL_WIDTH ==> 10
1669 
MIG: 21:40:13 :
1670 
MIG: 21:40:13 :  Valid Param: DDR3_CS_WIDTH ==> 1
1671 
MIG: 21:40:13 :
1672 
MIG: 21:40:13 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
1673 
MIG: 21:40:13 :
1674 
MIG: 21:40:13 :  Valid Param: DDR3_CKE_WIDTH ==> 1
1675 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
1676 
MIG: 21:40:13 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
1677 
MIG: 21:40:13 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
1678 
MIG: 21:40:13 :
1679 
MIG: 21:40:13 :  Valid Param: DDR3_DM_WIDTH ==> 2
1680 
MIG: 21:40:13 :
1681 
MIG: 21:40:13 :  Valid Param: DDR3_DQ_WIDTH ==> 16
1682 
MIG: 21:40:13 :
1683 
MIG: 21:40:13 :  Valid Param: DDR3_DQS_WIDTH ==> 2
1684 
MIG: 21:40:13 :
1685 
MIG: 21:40:13 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
1686 
MIG: 21:40:13 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
1687 
MIG: 21:40:13 :
1688 
MIG: 21:40:13 :  Valid Param: ECC ==> OFF
1689 
MIG: 21:40:13 :
1690 
MIG: 21:40:13 :  Valid Param: DDR3_DATA_WIDTH ==> 16
1691 
MIG: 21:40:13 :  Invalid Param: ECC_TEST ==> "OFF"
1692 
MIG: 21:40:13 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
1693 
MIG: 21:40:13 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
1694 
MIG: 21:40:13 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
1695 
MIG: 21:40:13 :  Invalid Param: DDR3_RANKS ==> 1
1696 
MIG: 21:40:13 :
1697 
MIG: 21:40:13 :  Valid Param: DDR3_ODT_WIDTH ==> 1
1698 
MIG: 21:40:13 :
1699 
MIG: 21:40:13 :  Valid Param: DDR3_ROW_WIDTH ==> 14
1700 
MIG: 21:40:13 :
1701 
MIG: 21:40:13 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
1702 
MIG: 21:40:13 :
1703 
MIG: 21:40:13 :  Valid Param: DDR3_USE_CS_PORT ==> 0
1704 
MIG: 21:40:13 :
1705 
MIG: 21:40:13 :  Valid Param: DDR3_USE_DM_PORT ==> 1
1706 
MIG: 21:40:13 :
1707 
MIG: 21:40:13 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
1708 
MIG: 21:40:13 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
1709 
MIG: 21:40:13 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
1710 
MIG: 21:40:13 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
1711 
MIG: 21:40:13 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
1712 
MIG: 21:40:13 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
1713 
MIG: 21:40:13 :  Invalid Param: DDR3_AL ==> "0"
1714 
MIG: 21:40:13 :  Invalid Param: DDR3_nAL ==> 0
1715 
MIG: 21:40:13 :  Invalid Param: DDR3_BURST_MODE ==> "8"
1716 
MIG: 21:40:13 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
1717 
MIG: 21:40:13 :  Invalid Param: DDR3_CL ==> 6
1718 
MIG: 21:40:13 :  Invalid Param: DDR3_CWL ==> 5
1719 
MIG: 21:40:13 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
1720 
MIG: 21:40:13 :  Invalid Param: DDR3_RTT_NOM ==> "40"
1721 
MIG: 21:40:13 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
1722 
MIG: 21:40:13 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
1723 
MIG: 21:40:13 :
1724 
MIG: 21:40:13 :  Valid Param: DDR3_REG_CTRL ==> OFF
1725 
MIG: 21:40:13 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
1726 
MIG: 21:40:13 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
1727 
MIG: 21:40:13 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 2500
1728 
MIG: 21:40:13 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 2
1729 
MIG: 21:40:13 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
1730 
MIG: 21:40:13 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
1731 
MIG: 21:40:13 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
1732 
MIG: 21:40:13 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
1733 
MIG: 21:40:13 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
1734 
MIG: 21:40:13 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
1735 
MIG: 21:40:13 :  Invalid Param: DDR3_MMCM_VCO ==> 800
1736 
MIG: 21:40:13 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
1737 
MIG: 21:40:13 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
1738 
MIG: 21:40:13 :  Invalid Param: DDR3_tCKE ==> 5000
1739 
MIG: 21:40:13 :  Invalid Param: DDR3_tFAW ==> 40000
1740 
MIG: 21:40:13 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
1741 
MIG: 21:40:13 :  Invalid Param: DDR3_tRAS ==> 35000
1742 
MIG: 21:40:13 :  Invalid Param: DDR3_tRCD ==> 13750
1743 
MIG: 21:40:13 :  Invalid Param: DDR3_tREFI ==> 7800000
1744 
MIG: 21:40:13 :  Invalid Param: DDR3_tRFC ==> 160000
1745 
MIG: 21:40:13 :  Invalid Param: DDR3_tRP ==> 13750
1746 
MIG: 21:40:13 :  Invalid Param: DDR3_tRRD ==> 7500
1747 
MIG: 21:40:13 :  Invalid Param: DDR3_tRTP ==> 7500
1748 
MIG: 21:40:13 :  Invalid Param: DDR3_tWTR ==> 7500
1749 
MIG: 21:40:13 :  Invalid Param: DDR3_tZQI ==> 128_000_000
1750 
MIG: 21:40:13 :  Invalid Param: DDR3_tZQCS ==> 64
1751 
MIG: 21:40:13 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
1752 
MIG: 21:40:13 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
1753 
MIG: 21:40:13 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
1754 
MIG: 21:40:13 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
1755 
MIG: 21:40:13 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
1756 
MIG: 21:40:13 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
1757 
MIG: 21:40:13 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
1758 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
1759 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
1760 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
1761 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
1762 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
1763 
MIG: 21:40:13 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_CFF_3DF_2FF
1764 
MIG: 21:40:13 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
1765 
MIG: 21:40:13 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
1766 
MIG: 21:40:13 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
1767 
MIG: 21:40:13 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038
1768 
MIG: 21:40:13 :  Invalid Param: DDR3_BANK_MAP ==> 36'h033_02A_032
1769 
MIG: 21:40:13 :  Invalid Param: DDR3_CAS_MAP ==> 12'h020
1770 
MIG: 21:40:13 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
1771 
MIG: 21:40:13 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_02B
1772 
MIG: 21:40:13 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
1773 
MIG: 21:40:13 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
1774 
MIG: 21:40:13 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
1775 
MIG: 21:40:13 :  Invalid Param: DDR3_RAS_MAP ==> 12'h021
1776 
MIG: 21:40:13 :  Invalid Param: DDR3_WE_MAP ==> 12'h022
1777 
MIG: 21:40:13 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
1778 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h016_018_014_019_010_017_011_013
1779 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h003_002_005_004_001_006_000_007
1780 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
1781 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
1782 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
1783 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
1784 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
1785 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
1786 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
1787 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
1788 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
1789 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
1790 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
1791 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
1792 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
1793 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
1794 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
1795 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
1796 
MIG: 21:40:13 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_012
1797 
MIG: 21:40:13 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
1798 
MIG: 21:40:13 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
1799 
MIG: 21:40:13 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
1800 
MIG: 21:40:13 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
1801 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
1802 
MIG: 21:40:13 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
1803 
MIG: 21:40:13 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
1804 
MIG: 21:40:13 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
1805 
MIG: 21:40:13 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
1806 
MIG: 21:40:13 :  Invalid Param: DDR3_WRLVL ==> "ON"
1807 
MIG: 21:40:13 :  Invalid Param: DDR3_ORDERING ==> "NORM"
1808 
MIG: 21:40:13 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
1809 
MIG: 21:40:13 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
1810 
MIG: 21:40:13 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
1811 
MIG: 21:40:13 :  Invalid Param: DDR3_TCQ ==> 100
1812 
MIG: 21:40:13 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
1813 
MIG: 21:40:13 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
1814 
MIG: 21:40:13 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
1815 
MIG: 21:40:13 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
1816 
MIG: 21:40:13 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
1817 
MIG: 21:40:13 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
1818 
MIG: 21:40:13 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
1819 
MIG: 21:40:13 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
1820 
MIG: 21:40:13 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
1821 
MIG: 21:40:13 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
1822 
MIG: 21:40:13 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
1823 
MIG: 21:40:13 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
1824 
MIG: 21:40:13 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
1825 
MIG: 21:40:13 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
1826 
MIG: 21:40:13 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
1827 
MIG: 21:40:13 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
1828 
MIG: 21:40:13 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
1829 
MIG: 21:40:13 :  Invalid Param: DDR3_tCK ==> 2500
1830 
MIG: 21:40:13 :
1831 
MIG: 21:40:13 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
1832 
MIG: 21:40:13 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
1833 
MIG: 21:40:13 :
1834 
MIG: 21:40:13 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
1835 
MIG: 21:40:13 :
1836 
MIG: 21:40:13 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
1837 
MIG: 21:40:13 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
1838 
MIG: 21:40:13 :
1839 
MIG: 21:40:13 :
1840 
MIG: 21:40:13 :
1841 
MIG: 21:40:13 : Same Interface
1842 
MIG: 21:40:18 : Running customizer.xit
1843 
MIG: 21:40:18 : ################# RUNNING MIG INTERACTIVE ###################
1844 
MIG: 21:40:18 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /home/stefan/.Xil/Vivado-16347-ws2/coregen/mig_7series_0
1845 
MIG: 21:40:18 : synp_flow:  -- synthesis_mode: Other
1846 
MIG: 21:40:18 : outputDirectory: /home/stefan/.Xil/Vivado-16347-ws2/coregen/mig_7series_0/_tmp/
1847 
MIG: 21:40:18 : vivado_mode: xpg_pa
1848 
MIG: 21:40:18 :  locked false
1849 
MIG: 21:40:18 : HDL Language: Verilog
1850 
MIG: 21:40:18 : compInfo: false
1851 
MIG: 21:40:18 : Vivado Options xc7a100t csg324 -2
1852 
MIG: 21:40:18 : 1: xc7a100t 2: csg324 3: -2
1853 
MIG: 21:40:18 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
1854 
MIG: 21:40:18 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
1855 
MIG: 21:40:18 : I am in catch area
1856 
MIG: 21:40:18 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /home/stefan/.Xil/Vivado-16347-ws2/coregen/mig_7series_0/xil_txt.in -cg_exc_out /home/stefan/.Xil/Vivado-16347-ws2/coregen/mig_7series_0/xil_txt.out ...
1857 
MIG: 21:41:47 : Prasad before: xmlPropertyPrj -- mig_a.prj
1858 
MIG: 21:41:47 : Prasad After: xmlPropertyPrj -- mig_b.prj
1859 
MIG: 21:41:47 : XML_INPUT_FILE: /home/stefan/.Xil/Vivado-16347-ws2/coregen/mig_7series_0/mig_b.prj
1860 
MIG: 21:41:47 : Component_Name: mig_7series_0
1861 
MIG: 21:41:47 : Moving mig_7series_0.veo ...
1862 
MIG: 21:41:47 : Moving mig_7series_0 ...
1863 
MIG: 21:41:47 : Moving mig_7series_0_xmdf.tcl ...
1864 
MIG: 21:41:47 : Sending back 0
1865 
MIG: 21:41:49 : xml_input_file: mig_b.prj
1866 
MIG: 21:41:49 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
1867 
MIG: 21:41:49 : xml_input_file: mig_b.prj
1868 
MIG: 21:41:49 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
1869 
MIG: 21:41:49 : In updateAllModelParams
1870 
MIG: 21:41:49 : IGN:     mig_7series_0 <==>     mig_7series_0
1871 
MIG: 21:41:49 : IGN:          <==>
1872 
MIG: 21:41:49 : XGUI hdlLanguage: Verilog
1873 
MIG: 21:41:49 : xgui vivado_mode: xpg_pa
1874 
MIG: 21:41:49 : xgui hdlLanguage: Verilog -- hdlExt: v
1875 
MIG: 21:41:49 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
1876 
MIG: 21:41:50 :
1877 
MIG: 21:41:50 : Inside fn mem: DDR3
1878 
MIG: 21:41:50 : QDRII+ Inside fn ui: 100000000
1879 
MIG: 21:41:50 : cntrl:  memtype: DDR3
1880 
MIG: 21:41:50 :
1881 
MIG: 21:41:50 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800
1882 
MIG: 21:41:50 :
1883 
MIG: 21:41:50 :
1884 
MIG: 21:41:50 :
1885 
MIG: 21:41:50 :
1886 
MIG: 21:41:50 :  polarity_value: 1
1887 
MIG: 21:41:50 :
1888 
MIG: 21:41:50 :
1889 
MIG: 21:41:50 : cntrl:  memtype: DDR3
1890 
MIG: 21:41:50 :
1891 
MIG: 21:41:50 :  Valid Param: DDR3_BANK_WIDTH ==> 3
1892 
MIG: 21:41:50 :
1893 
MIG: 21:41:50 :  Valid Param: DDR3_CK_WIDTH ==> 1
1894 
MIG: 21:41:50 :  Invalid Param: DDR3_COL_WIDTH ==> 10
1895 
MIG: 21:41:50 :
1896 
MIG: 21:41:50 :  Valid Param: DDR3_CS_WIDTH ==> 1
1897 
MIG: 21:41:50 :
1898 
MIG: 21:41:50 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
1899 
MIG: 21:41:50 :
1900 
MIG: 21:41:50 :  Valid Param: DDR3_CKE_WIDTH ==> 1
1901 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
1902 
MIG: 21:41:50 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
1903 
MIG: 21:41:50 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
1904 
MIG: 21:41:50 :
1905 
MIG: 21:41:50 :  Valid Param: DDR3_DM_WIDTH ==> 2
1906 
MIG: 21:41:50 :
1907 
MIG: 21:41:50 :  Valid Param: DDR3_DQ_WIDTH ==> 16
1908 
MIG: 21:41:50 :
1909 
MIG: 21:41:50 :  Valid Param: DDR3_DQS_WIDTH ==> 2
1910 
MIG: 21:41:50 :
1911 
MIG: 21:41:50 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
1912 
MIG: 21:41:50 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
1913 
MIG: 21:41:50 :
1914 
MIG: 21:41:50 :  Valid Param: ECC ==> OFF
1915 
MIG: 21:41:50 :
1916 
MIG: 21:41:50 :  Valid Param: DDR3_DATA_WIDTH ==> 16
1917 
MIG: 21:41:50 :  Invalid Param: ECC_TEST ==> "OFF"
1918 
MIG: 21:41:50 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
1919 
MIG: 21:41:50 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
1920 
MIG: 21:41:50 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
1921 
MIG: 21:41:50 :  Invalid Param: DDR3_RANKS ==> 1
1922 
MIG: 21:41:50 :
1923 
MIG: 21:41:50 :  Valid Param: DDR3_ODT_WIDTH ==> 1
1924 
MIG: 21:41:50 :
1925 
MIG: 21:41:50 :  Valid Param: DDR3_ROW_WIDTH ==> 14
1926 
MIG: 21:41:50 :
1927 
MIG: 21:41:50 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
1928 
MIG: 21:41:50 :
1929 
MIG: 21:41:50 :  Valid Param: DDR3_USE_CS_PORT ==> 0
1930 
MIG: 21:41:50 :
1931 
MIG: 21:41:50 :  Valid Param: DDR3_USE_DM_PORT ==> 1
1932 
MIG: 21:41:50 :
1933 
MIG: 21:41:50 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
1934 
MIG: 21:41:50 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
1935 
MIG: 21:41:50 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
1936 
MIG: 21:41:50 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
1937 
MIG: 21:41:50 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
1938 
MIG: 21:41:50 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
1939 
MIG: 21:41:50 :  Invalid Param: DDR3_AL ==> "0"
1940 
MIG: 21:41:50 :  Invalid Param: DDR3_nAL ==> 0
1941 
MIG: 21:41:50 :  Invalid Param: DDR3_BURST_MODE ==> "8"
1942 
MIG: 21:41:50 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
1943 
MIG: 21:41:50 :  Invalid Param: DDR3_CL ==> 6
1944 
MIG: 21:41:50 :  Invalid Param: DDR3_CWL ==> 5
1945 
MIG: 21:41:50 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
1946 
MIG: 21:41:50 :  Invalid Param: DDR3_RTT_NOM ==> "40"
1947 
MIG: 21:41:50 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
1948 
MIG: 21:41:50 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
1949 
MIG: 21:41:50 :
1950 
MIG: 21:41:50 :  Valid Param: DDR3_REG_CTRL ==> OFF
1951 
MIG: 21:41:50 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
1952 
MIG: 21:41:50 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
1953 
MIG: 21:41:50 :  Invalid Param: DDR3_CLKIN_PERIOD ==> -2147483647
1954 
MIG: 21:41:50 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 0
1955 
MIG: 21:41:50 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 0
1956 
MIG: 21:41:50 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
1957 
MIG: 21:41:50 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 0
1958 
MIG: 21:41:50 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 0
1959 
MIG: 21:41:50 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 0
1960 
MIG: 21:41:50 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 0
1961 
MIG: 21:41:50 :  Invalid Param: DDR3_MMCM_VCO ==> 800
1962 
MIG: 21:41:50 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
1963 
MIG: 21:41:50 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
1964 
MIG: 21:41:50 :  Invalid Param: DDR3_tCKE ==> 5000
1965 
MIG: 21:41:50 :  Invalid Param: DDR3_tFAW ==> 40000
1966 
MIG: 21:41:50 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
1967 
MIG: 21:41:50 :  Invalid Param: DDR3_tRAS ==> 35000
1968 
MIG: 21:41:50 :  Invalid Param: DDR3_tRCD ==> 13750
1969 
MIG: 21:41:50 :  Invalid Param: DDR3_tREFI ==> 7800000
1970 
MIG: 21:41:50 :  Invalid Param: DDR3_tRFC ==> 160000
1971 
MIG: 21:41:50 :  Invalid Param: DDR3_tRP ==> 13750
1972 
MIG: 21:41:50 :  Invalid Param: DDR3_tRRD ==> 7500
1973 
MIG: 21:41:50 :  Invalid Param: DDR3_tRTP ==> 7500
1974 
MIG: 21:41:50 :  Invalid Param: DDR3_tWTR ==> 7500
1975 
MIG: 21:41:50 :  Invalid Param: DDR3_tZQI ==> 128_000_000
1976 
MIG: 21:41:50 :  Invalid Param: DDR3_tZQCS ==> 64
1977 
MIG: 21:41:50 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
1978 
MIG: 21:41:50 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
1979 
MIG: 21:41:50 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
1980 
MIG: 21:41:50 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
1981 
MIG: 21:41:50 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
1982 
MIG: 21:41:50 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
1983 
MIG: 21:41:50 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
1984 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
1985 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
1986 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
1987 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
1988 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
1989 
MIG: 21:41:50 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_CFF_3DF_2FF
1990 
MIG: 21:41:50 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
1991 
MIG: 21:41:50 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
1992 
MIG: 21:41:50 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
1993 
MIG: 21:41:50 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038
1994 
MIG: 21:41:50 :  Invalid Param: DDR3_BANK_MAP ==> 36'h033_02A_032
1995 
MIG: 21:41:50 :  Invalid Param: DDR3_CAS_MAP ==> 12'h020
1996 
MIG: 21:41:50 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
1997 
MIG: 21:41:50 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_02B
1998 
MIG: 21:41:50 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
1999 
MIG: 21:41:50 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
2000 
MIG: 21:41:50 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
2001 
MIG: 21:41:50 :  Invalid Param: DDR3_RAS_MAP ==> 12'h021
2002 
MIG: 21:41:50 :  Invalid Param: DDR3_WE_MAP ==> 12'h022
2003 
MIG: 21:41:50 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
2004 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h016_018_014_019_010_017_011_013
2005 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h003_002_005_004_001_006_000_007
2006 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
2007 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
2008 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
2009 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
2010 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
2011 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
2012 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
2013 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
2014 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
2015 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
2016 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
2017 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
2018 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
2019 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
2020 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
2021 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
2022 
MIG: 21:41:50 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_012
2023 
MIG: 21:41:50 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
2024 
MIG: 21:41:50 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
2025 
MIG: 21:41:50 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
2026 
MIG: 21:41:50 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
2027 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
2028 
MIG: 21:41:50 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
2029 
MIG: 21:41:50 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
2030 
MIG: 21:41:50 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
2031 
MIG: 21:41:50 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
2032 
MIG: 21:41:50 :  Invalid Param: DDR3_WRLVL ==> "ON"
2033 
MIG: 21:41:50 :  Invalid Param: DDR3_ORDERING ==> "NORM"
2034 
MIG: 21:41:50 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
2035 
MIG: 21:41:50 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
2036 
MIG: 21:41:50 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
2037 
MIG: 21:41:50 :  Invalid Param: DDR3_TCQ ==> 100
2038 
MIG: 21:41:50 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
2039 
MIG: 21:41:50 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
2040 
MIG: 21:41:50 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
2041 
MIG: 21:41:50 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
2042 
MIG: 21:41:50 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
2043 
MIG: 21:41:50 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
2044 
MIG: 21:41:50 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
2045 
MIG: 21:41:50 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
2046 
MIG: 21:41:50 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
2047 
MIG: 21:41:50 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
2048 
MIG: 21:41:50 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
2049 
MIG: 21:41:50 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
2050 
MIG: 21:41:50 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
2051 
MIG: 21:41:50 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
2052 
MIG: 21:41:50 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
2053 
MIG: 21:41:50 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
2054 
MIG: 21:41:50 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
2055 
MIG: 21:41:50 :  Invalid Param: DDR3_tCK ==> 2500
2056 
MIG: 21:41:50 :
2057 
MIG: 21:41:50 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
2058 
MIG: 21:41:50 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
2059 
MIG: 21:41:50 :
2060 
MIG: 21:41:50 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
2061 
MIG: 21:41:50 :
2062 
MIG: 21:41:50 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
2063 
MIG: 21:41:50 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
2064 
MIG: 21:41:50 :
2065 
MIG: 21:41:50 :
2066 
MIG: 21:41:50 :
2067 
MIG: 21:41:50 : Same Interface
2068 
MIG: 21:41:53 : ################# RUNNING MIG BATCH ###################
2069 
MIG: 21:41:53 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
2070 
MIG: 21:41:53 : synp_flow:  -- synthesis_mode: Other
2071 
MIG: 21:41:53 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
2072 
MIG: 21:41:53 : vivado_mode: xpg_pa
2073 
MIG: 21:41:53 :  locked false
2074 
MIG: 21:41:53 : HDL Language: Verilog
2075 
MIG: 21:41:53 : compInfo: false
2076 
MIG: 21:41:53 : Vivado Options xc7a100t csg324 -2
2077 
MIG: 21:41:53 : 1: xc7a100t 2: csg324 3: -2
2078 
MIG: 21:41:53 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
2079 
MIG: 21:41:53 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
2080 
MIG: 21:41:53 : I am in catch area
2081 
MIG: 21:41:53 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
2082 
MIG: 21:42:08 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2083 
MIG: 21:42:08 : Component_Name: mig_7series_0
2084 
MIG: 21:42:08 : Moving mig_7series_0_xmdf.tcl ...
2085 
MIG: 21:42:08 : Moving mig_7series_0 ...
2086 
MIG: 21:42:08 : Moving mig_7series_0.veo ...
2087 
MIG: 21:42:14 : Running synthesis.xit
2088 
MIG: 21:42:14 : ################# RUNNING MIG BATCH ###################
2089 
MIG: 21:42:14 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
2090 
MIG: 21:42:14 : synp_flow:  -- synthesis_mode: Other
2091 
MIG: 21:42:14 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
2092 
MIG: 21:42:14 : vivado_mode: xpg_pa
2093 
MIG: 21:42:14 :  locked false
2094 
MIG: 21:42:14 : HDL Language: Verilog
2095 
MIG: 21:42:14 : compInfo: false
2096 
MIG: 21:42:14 : Vivado Options xc7a100t csg324 -2
2097 
MIG: 21:42:14 : 1: xc7a100t 2: csg324 3: -2
2098 
MIG: 21:42:14 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
2099 
MIG: 21:42:14 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
2100 
MIG: 21:42:14 : I am in catch area
2101 
MIG: 21:42:14 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
2102 
MIG: 21:42:28 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2103 
MIG: 21:42:28 : Component_Name: mig_7series_0
2104 
MIG: 21:42:28 : Moving mig_7series_0_xmdf.tcl ...
2105 
MIG: 21:42:28 : Moving mig_7series_0 ...
2106 
MIG: 21:42:28 : Moving mig_7series_0.veo ...
2107 
MIG: 21:42:29 : Running vlog_synth_rpr.xit
2108 
MIG: 21:42:29 : IGN:     mig_7series_0 <==>     mig_7series_0
2109 
MIG: 21:42:29 : IGN:          <==>         400
2110 
MIG: 21:42:29 : Running simulation.xit
2111 
MIG: 21:42:29 : ################# RUNNING MIG BATCH ###################
2112 
MIG: 21:42:29 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
2113 
MIG: 21:42:29 : synp_flow:  -- synthesis_mode: Other
2114 
MIG: 21:42:29 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
2115 
MIG: 21:42:29 : vivado_mode: xpg_pa
2116 
MIG: 21:42:29 :  locked false
2117 
MIG: 21:42:29 : HDL Language: Verilog
2118 
MIG: 21:42:29 : compInfo: false
2119 
MIG: 21:42:29 : Vivado Options xc7a100t csg324 -2
2120 
MIG: 21:42:29 : 1: xc7a100t 2: csg324 3: -2
2121 
MIG: 21:42:29 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
2122 
MIG: 21:42:29 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
2123 
MIG: 21:42:29 : I am in catch area
2124 
MIG: 21:42:29 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
2125 
MIG: 21:42:46 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2126 
MIG: 21:42:46 : Component_Name: mig_7series_0
2127 
MIG: 21:42:46 : Moving mig_7series_0_xmdf.tcl ...
2128 
MIG: 21:42:46 : Moving mig_7series_0 ...
2129 
MIG: 21:42:46 : Moving mig_7series_0.veo ...
2130 
MIG: 21:42:47 : Running vlog_sim_rpr.xit .. PRASAD DBG1
2131 
MIG: 21:42:47 : IGN:     mig_7series_0 <==>     mig_7series_0
2132 
MIG: 21:42:47 : IGN:          <==>         400
2133 
MIG: 21:42:47 : Running implementation.xit
2134 
MIG: 21:42:47 : IGN:     mig_7series_0 <==>     mig_7series_0
2135 
MIG: 21:42:47 : IGN:          <==>         400
2136 
MIG: 23:27:41 : xml_input_file: mig_b.prj
2137 
MIG: 23:27:41 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2138 
MIG: 23:27:41 : xml_input_file: mig_b.prj
2139 
MIG: 23:27:41 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2140 
MIG: 23:27:43 : xml_input_file: mig_b.prj
2141 
MIG: 23:27:43 : Absolute path of xml_input_file: mig_b.prj
2142 
MIG: 23:27:43 : xml_input_file: mig_b.prj
2143 
MIG: 23:27:43 : Absolute path of xml_input_file: mig_b.prj
2144 
MIG: 23:27:43 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2145 
MIG: 23:27:43 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2146 
MIG: 23:27:43 : xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2147 
MIG: 23:27:43 : Absolute path of xml_input_file: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2148 
MIG: 23:27:43 : In updateAllModelParams
2149 
MIG: 23:27:43 : IGN:     mig_7series_0 <==>     mig_7series_0
2150 
MIG: 23:27:43 : IGN:          <==>         400
2151 
MIG: 23:27:43 : XGUI hdlLanguage: Verilog
2152 
MIG: 23:27:43 : xgui vivado_mode: xpg_pa
2153 
MIG: 23:27:43 : xgui hdlLanguage: Verilog -- hdlExt: v
2154 
MIG: 23:27:43 : Reading /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_7series_0/user_design/rtl/mig_7series_0_mig.v ...
2155 
MIG: 23:27:44 :
2156 
MIG: 23:27:44 : Inside fn mem: DDR3
2157 
MIG: 23:27:44 : QDRII+ Inside fn ui: 100000000
2158 
MIG: 23:27:44 : cntrl:  memtype: DDR3
2159 
MIG: 23:27:44 :
2160 
MIG: 23:27:44 :  MMCM_VCO single ctrl param_name: MMCM_VCO --  possibleMaxVcoVal: 800
2161 
MIG: 23:27:44 :
2162 
MIG: 23:27:44 :
2163 
MIG: 23:27:44 :
2164 
MIG: 23:27:44 :
2165 
MIG: 23:27:44 :  polarity_value: 1
2166 
MIG: 23:27:44 :
2167 
MIG: 23:27:44 :
2168 
MIG: 23:27:44 : cntrl:  memtype: DDR3
2169 
MIG: 23:27:44 :
2170 
MIG: 23:27:44 :  Valid Param: DDR3_BANK_WIDTH ==> 3
2171 
MIG: 23:27:44 :
2172 
MIG: 23:27:44 :  Valid Param: DDR3_CK_WIDTH ==> 1
2173 
MIG: 23:27:44 :  Invalid Param: DDR3_COL_WIDTH ==> 10
2174 
MIG: 23:27:44 :
2175 
MIG: 23:27:44 :  Valid Param: DDR3_CS_WIDTH ==> 1
2176 
MIG: 23:27:44 :
2177 
MIG: 23:27:44 :  Valid Param: DDR3_nCS_PER_RANK ==> 1
2178 
MIG: 23:27:44 :
2179 
MIG: 23:27:44 :  Valid Param: DDR3_CKE_WIDTH ==> 1
2180 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA_BUF_ADDR_WIDTH ==> 5
2181 
MIG: 23:27:44 :  Invalid Param: DDR3_DQ_CNT_WIDTH ==> 4
2182 
MIG: 23:27:44 :  Invalid Param: DDR3_DQ_PER_DM ==> 8
2183 
MIG: 23:27:44 :
2184 
MIG: 23:27:44 :  Valid Param: DDR3_DM_WIDTH ==> 2
2185 
MIG: 23:27:44 :
2186 
MIG: 23:27:44 :  Valid Param: DDR3_DQ_WIDTH ==> 16
2187 
MIG: 23:27:44 :
2188 
MIG: 23:27:44 :  Valid Param: DDR3_DQS_WIDTH ==> 2
2189 
MIG: 23:27:44 :
2190 
MIG: 23:27:44 :  Valid Param: DDR3_DQS_CNT_WIDTH ==> 1
2191 
MIG: 23:27:44 :  Invalid Param: DDR3_DRAM_WIDTH ==> 8
2192 
MIG: 23:27:44 :
2193 
MIG: 23:27:44 :  Valid Param: ECC ==> OFF
2194 
MIG: 23:27:44 :
2195 
MIG: 23:27:44 :  Valid Param: DDR3_DATA_WIDTH ==> 16
2196 
MIG: 23:27:44 :  Invalid Param: ECC_TEST ==> "OFF"
2197 
MIG: 23:27:44 :  Invalid Param: DDR3_PAYLOAD_WIDTH ==> (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH
2198 
MIG: 23:27:44 :  Invalid Param: DDR3_MEM_ADDR_ORDER ==> "BANK_ROW_COLUMN"
2199 
MIG: 23:27:44 :  Invalid Param: DDR3_nBANK_MACHS ==> 4
2200 
MIG: 23:27:44 :  Invalid Param: DDR3_RANKS ==> 1
2201 
MIG: 23:27:44 :
2202 
MIG: 23:27:44 :  Valid Param: DDR3_ODT_WIDTH ==> 1
2203 
MIG: 23:27:44 :
2204 
MIG: 23:27:44 :  Valid Param: DDR3_ROW_WIDTH ==> 14
2205 
MIG: 23:27:44 :
2206 
MIG: 23:27:44 :  Valid Param: DDR3_ADDR_WIDTH ==> 28
2207 
MIG: 23:27:44 :
2208 
MIG: 23:27:44 :  Valid Param: DDR3_USE_CS_PORT ==> 0
2209 
MIG: 23:27:44 :
2210 
MIG: 23:27:44 :  Valid Param: DDR3_USE_DM_PORT ==> 1
2211 
MIG: 23:27:44 :
2212 
MIG: 23:27:44 :  Valid Param: DDR3_USE_ODT_PORT ==> 1
2213 
MIG: 23:27:44 :  Invalid Param: DDR3_IS_CLK_SHARED ==> "FALSE"
2214 
MIG: 23:27:44 :  Invalid Param: DDR3_PHY_CONTROL_MASTER_BANK ==> 0
2215 
MIG: 23:27:44 :  Invalid Param: DDR3_MEM_DENSITY ==> "2Gb"
2216 
MIG: 23:27:44 :  Invalid Param: DDR3_MEM_SPEEDGRADE ==> "125"
2217 
MIG: 23:27:44 :  Invalid Param: DDR3_MEM_DEVICE_WIDTH ==> 16
2218 
MIG: 23:27:44 :  Invalid Param: DDR3_AL ==> "0"
2219 
MIG: 23:27:44 :  Invalid Param: DDR3_nAL ==> 0
2220 
MIG: 23:27:44 :  Invalid Param: DDR3_BURST_MODE ==> "8"
2221 
MIG: 23:27:44 :  Invalid Param: DDR3_BURST_TYPE ==> "SEQ"
2222 
MIG: 23:27:44 :  Invalid Param: DDR3_CL ==> 6
2223 
MIG: 23:27:44 :  Invalid Param: DDR3_CWL ==> 5
2224 
MIG: 23:27:44 :  Invalid Param: DDR3_OUTPUT_DRV ==> "HIGH"
2225 
MIG: 23:27:44 :  Invalid Param: DDR3_RTT_NOM ==> "40"
2226 
MIG: 23:27:44 :  Invalid Param: DDR3_RTT_WR ==> "OFF"
2227 
MIG: 23:27:44 :  Invalid Param: DDR3_ADDR_CMD_MODE ==> "1T"
2228 
MIG: 23:27:44 :
2229 
MIG: 23:27:44 :  Valid Param: DDR3_REG_CTRL ==> OFF
2230 
MIG: 23:27:44 :  Invalid Param: DDR3_CA_MIRROR ==> "OFF"
2231 
MIG: 23:27:44 :  Invalid Param: DDR3_VDD_OP_VOLT ==> "150"
2232 
MIG: 23:27:44 :  Invalid Param: DDR3_CLKIN_PERIOD ==> 2500
2233 
MIG: 23:27:44 :  Invalid Param: DDR3_CLKFBOUT_MULT ==> 2
2234 
MIG: 23:27:44 :  Invalid Param: DDR3_DIVCLK_DIVIDE ==> 1
2235 
MIG: 23:27:44 :  Invalid Param: DDR3_CLKOUT0_PHASE ==> 337.5
2236 
MIG: 23:27:44 :  Invalid Param: DDR3_CLKOUT0_DIVIDE ==> 2
2237 
MIG: 23:27:44 :  Invalid Param: DDR3_CLKOUT1_DIVIDE ==> 2
2238 
MIG: 23:27:44 :  Invalid Param: DDR3_CLKOUT2_DIVIDE ==> 32
2239 
MIG: 23:27:44 :  Invalid Param: DDR3_CLKOUT3_DIVIDE ==> 8
2240 
MIG: 23:27:44 :  Invalid Param: DDR3_MMCM_VCO ==> 800
2241 
MIG: 23:27:44 :  Invalid Param: DDR3_MMCM_MULT_F ==> 8
2242 
MIG: 23:27:44 :  Invalid Param: DDR3_MMCM_DIVCLK_DIVIDE ==> 1
2243 
MIG: 23:27:44 :  Invalid Param: DDR3_tCKE ==> 5000
2244 
MIG: 23:27:44 :  Invalid Param: DDR3_tFAW ==> 40000
2245 
MIG: 23:27:44 :  Invalid Param: DDR3_tPRDI ==> 1_000_000
2246 
MIG: 23:27:44 :  Invalid Param: DDR3_tRAS ==> 35000
2247 
MIG: 23:27:44 :  Invalid Param: DDR3_tRCD ==> 13750
2248 
MIG: 23:27:44 :  Invalid Param: DDR3_tREFI ==> 7800000
2249 
MIG: 23:27:44 :  Invalid Param: DDR3_tRFC ==> 160000
2250 
MIG: 23:27:44 :  Invalid Param: DDR3_tRP ==> 13750
2251 
MIG: 23:27:44 :  Invalid Param: DDR3_tRRD ==> 7500
2252 
MIG: 23:27:44 :  Invalid Param: DDR3_tRTP ==> 7500
2253 
MIG: 23:27:44 :  Invalid Param: DDR3_tWTR ==> 7500
2254 
MIG: 23:27:44 :  Invalid Param: DDR3_tZQI ==> 128_000_000
2255 
MIG: 23:27:44 :  Invalid Param: DDR3_tZQCS ==> 64
2256 
MIG: 23:27:44 :  Invalid Param: DDR3_SIM_BYPASS_INIT_CAL ==> "OFF"
2257 
MIG: 23:27:44 :  Invalid Param: DDR3_SIMULATION ==> "FALSE"
2258 
MIG: 23:27:44 :  Invalid Param: DDR3_BYTE_LANES_B0 ==> 4'b1111
2259 
MIG: 23:27:44 :  Invalid Param: DDR3_BYTE_LANES_B1 ==> 4'b0000
2260 
MIG: 23:27:44 :  Invalid Param: DDR3_BYTE_LANES_B2 ==> 4'b0000
2261 
MIG: 23:27:44 :  Invalid Param: DDR3_BYTE_LANES_B3 ==> 4'b0000
2262 
MIG: 23:27:44 :  Invalid Param: DDR3_BYTE_LANES_B4 ==> 4'b0000
2263 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA_CTL_B0 ==> 4'b0011
2264 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA_CTL_B1 ==> 4'b0000
2265 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA_CTL_B2 ==> 4'b0000
2266 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA_CTL_B3 ==> 4'b0000
2267 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA_CTL_B4 ==> 4'b0000
2268 
MIG: 23:27:44 :  Invalid Param: DDR3_PHY_0_BITLANES ==> 48'hFFF_CFF_3DF_2FF
2269 
MIG: 23:27:44 :  Invalid Param: DDR3_PHY_1_BITLANES ==> 48'h000_000_000_000
2270 
MIG: 23:27:44 :  Invalid Param: DDR3_PHY_2_BITLANES ==> 48'h000_000_000_000
2271 
MIG: 23:27:44 :  Invalid Param: DDR3_CK_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_02
2272 
MIG: 23:27:44 :  Invalid Param: DDR3_ADDR_MAP ==> 192'h000_000_037_025_03A_024_035_03B_039_027_031_026_023_034_036_038
2273 
MIG: 23:27:44 :  Invalid Param: DDR3_BANK_MAP ==> 36'h033_02A_032
2274 
MIG: 23:27:44 :  Invalid Param: DDR3_CAS_MAP ==> 12'h020
2275 
MIG: 23:27:44 :  Invalid Param: DDR3_CKE_ODT_BYTE_MAP ==> 8'h00
2276 
MIG: 23:27:44 :  Invalid Param: DDR3_CKE_MAP ==> 96'h000_000_000_000_000_000_000_02B
2277 
MIG: 23:27:44 :  Invalid Param: DDR3_ODT_MAP ==> 96'h000_000_000_000_000_000_000_030
2278 
MIG: 23:27:44 :  Invalid Param: DDR3_CS_MAP ==> 120'h000_000_000_000_000_000_000_000_000_000
2279 
MIG: 23:27:44 :  Invalid Param: DDR3_PARITY_MAP ==> 12'h000
2280 
MIG: 23:27:44 :  Invalid Param: DDR3_RAS_MAP ==> 12'h021
2281 
MIG: 23:27:44 :  Invalid Param: DDR3_WE_MAP ==> 12'h022
2282 
MIG: 23:27:44 :  Invalid Param: DDR3_DQS_BYTE_MAP ==> 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_01
2283 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA0_MAP ==> 96'h016_018_014_019_010_017_011_013
2284 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA1_MAP ==> 96'h003_002_005_004_001_006_000_007
2285 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA2_MAP ==> 96'h000_000_000_000_000_000_000_000
2286 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA3_MAP ==> 96'h000_000_000_000_000_000_000_000
2287 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA4_MAP ==> 96'h000_000_000_000_000_000_000_000
2288 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA5_MAP ==> 96'h000_000_000_000_000_000_000_000
2289 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA6_MAP ==> 96'h000_000_000_000_000_000_000_000
2290 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA7_MAP ==> 96'h000_000_000_000_000_000_000_000
2291 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA8_MAP ==> 96'h000_000_000_000_000_000_000_000
2292 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA9_MAP ==> 96'h000_000_000_000_000_000_000_000
2293 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA10_MAP ==> 96'h000_000_000_000_000_000_000_000
2294 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA11_MAP ==> 96'h000_000_000_000_000_000_000_000
2295 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA12_MAP ==> 96'h000_000_000_000_000_000_000_000
2296 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA13_MAP ==> 96'h000_000_000_000_000_000_000_000
2297 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA14_MAP ==> 96'h000_000_000_000_000_000_000_000
2298 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA15_MAP ==> 96'h000_000_000_000_000_000_000_000
2299 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA16_MAP ==> 96'h000_000_000_000_000_000_000_000
2300 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA17_MAP ==> 96'h000_000_000_000_000_000_000_000
2301 
MIG: 23:27:44 :  Invalid Param: DDR3_MASK0_MAP ==> 108'h000_000_000_000_000_000_000_009_012
2302 
MIG: 23:27:44 :  Invalid Param: DDR3_MASK1_MAP ==> 108'h000_000_000_000_000_000_000_000_000
2303 
MIG: 23:27:44 :  Invalid Param: DDR3_SLOT_0_CONFIG ==> 8'b0000_0001
2304 
MIG: 23:27:44 :  Invalid Param: DDR3_SLOT_1_CONFIG ==> 8'b0000_0000
2305 
MIG: 23:27:44 :  Invalid Param: DDR3_IBUF_LPWR_MODE ==> "OFF"
2306 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA_IO_IDLE_PWRDWN ==> "ON"
2307 
MIG: 23:27:44 :  Invalid Param: DDR3_BANK_TYPE ==> "HR_IO"
2308 
MIG: 23:27:44 :  Invalid Param: DDR3_DATA_IO_PRIM_TYPE ==> "HR_LP"
2309 
MIG: 23:27:44 :  Invalid Param: DDR3_CKE_ODT_AUX ==> "FALSE"
2310 
MIG: 23:27:44 :  Invalid Param: DDR3_USER_REFRESH ==> "OFF"
2311 
MIG: 23:27:44 :  Invalid Param: DDR3_WRLVL ==> "ON"
2312 
MIG: 23:27:44 :  Invalid Param: DDR3_ORDERING ==> "NORM"
2313 
MIG: 23:27:44 :  Invalid Param: DDR3_CALIB_ROW_ADD ==> 16'h0000
2314 
MIG: 23:27:44 :  Invalid Param: DDR3_CALIB_COL_ADD ==> 12'h000
2315 
MIG: 23:27:44 :  Invalid Param: DDR3_CALIB_BA_ADD ==> 3'h0
2316 
MIG: 23:27:44 :  Invalid Param: DDR3_TCQ ==> 100
2317 
MIG: 23:27:44 :  Invalid Param: DDR3_IDELAY_ADJ ==> "OFF"
2318 
MIG: 23:27:44 :  Invalid Param: DDR3_FINE_PER_BIT ==> "OFF"
2319 
MIG: 23:27:44 :  Invalid Param: DDR3_CENTER_COMP_MODE ==> "OFF"
2320 
MIG: 23:27:44 :  Invalid Param: DDR3_PI_VAL_ADJ ==> "OFF"
2321 
MIG: 23:27:44 :  Invalid Param: DDR3_IODELAY_GRP0 ==> "MIG_7SERIES_0_IODELAY_MIG0"
2322 
MIG: 23:27:44 :  Invalid Param: DDR3_IODELAY_GRP1 ==> "MIG_7SERIES_0_IODELAY_MIG1"
2323 
MIG: 23:27:44 :  Invalid Param: DDR3_SYSCLK_TYPE ==> "NO_BUFFER"
2324 
MIG: 23:27:44 :  Invalid Param: DDR3_REFCLK_TYPE ==> "NO_BUFFER"
2325 
MIG: 23:27:44 :  Invalid Param: DDR3_SYS_RST_PORT ==> "FALSE"
2326 
MIG: 23:27:44 :  Invalid Param: DDR3_FPGA_SPEED_GRADE ==> 2
2327 
MIG: 23:27:44 :  Invalid Param: DDR3_CMD_PIPE_PLUS1 ==> "ON"
2328 
MIG: 23:27:44 :  Invalid Param: DDR3_DRAM_TYPE ==> "DDR3"
2329 
MIG: 23:27:44 :  Invalid Param: DDR3_CAL_WIDTH ==> "HALF"
2330 
MIG: 23:27:44 :  Invalid Param: DDR3_STARVE_LIMIT ==> 2
2331 
MIG: 23:27:44 :  Invalid Param: DDR3_REF_CLK_MMCM_IODELAY_CTRL ==> "FALSE"
2332 
MIG: 23:27:44 :  Invalid Param: DDR3_REFCLK_FREQ ==> 200.0
2333 
MIG: 23:27:44 :  Invalid Param: DDR3_DIFF_TERM_REFCLK ==> "TRUE"
2334 
MIG: 23:27:44 :  Invalid Param: DDR3_tCK ==> 2500
2335 
MIG: 23:27:44 :
2336 
MIG: 23:27:44 :  Valid Param: DDR3_nCK_PER_CLK ==> 4
2337 
MIG: 23:27:44 :  Invalid Param: DDR3_DIFF_TERM_SYSCLK ==> "TRUE"
2338 
MIG: 23:27:44 :
2339 
MIG: 23:27:44 :  Valid Param: DDR3_DEBUG_PORT ==> OFF
2340 
MIG: 23:27:44 :
2341 
MIG: 23:27:44 :  Invalid Param: DDR3_TEMP_MON_CONTROL ==> "INTERNAL"
2342 
MIG: 23:27:44 :  Invalid Param: DDR3_RST_ACT_LOW ==> 1
2343 
MIG: 23:27:44 :
2344 
MIG: 23:27:44 :
2345 
MIG: 23:27:44 :
2346 
MIG: 23:27:44 : Same Interface
2347 
MIG: 01:33:14 : Running synthesis.xit
2348 
MIG: 01:33:14 : ################# RUNNING MIG BATCH ###################
2349 
MIG: 01:33:14 : Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
2350 
MIG: 01:33:14 : synp_flow:  -- synthesis_mode: Other
2351 
MIG: 01:33:14 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
2352 
MIG: 01:33:14 : vivado_mode: xpg_pa
2353 
MIG: 01:33:14 :  locked false
2354 
MIG: 01:33:14 : HDL Language: Verilog
2355 
MIG: 01:33:14 : compInfo: false
2356 
MIG: 01:33:14 : Vivado Options xc7a100t csg324 -2
2357 
MIG: 01:33:14 : 1: xc7a100t 2: csg324 3: -2
2358 
MIG: 01:33:14 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig
2359 
MIG: 01:33:14 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
2360 
MIG: 01:33:14 : I am in catch area
2361 
MIG: 01:33:14 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_3/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_txt.out ...
2362 
MIG: 01:33:30 : XML_INPUT_FILE: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
2363 
MIG: 01:33:30 : Component_Name: mig_7series_0
2364 
MIG: 01:33:30 : Moving mig_7series_0_xmdf.tcl ...
2365 
MIG: 01:33:30 : Moving mig_7series_0 ...
2366 
MIG: 01:33:30 : Moving mig_7series_0.veo ...
2367 
MIG: 01:33:30 : Running vlog_synth_rpr.xit
2368 
MIG: 01:33:30 : IGN:     mig_7series_0 <==>     mig_7series_0
2369 
MIG: 01:33:30 : IGN:          <==>         400
2370 
MIG: 01:33:31 : Running implementation.xit
2371 
MIG: 01:33:31 : IGN:     mig_7series_0 <==>     mig_7series_0
2372 
MIG: 01:33:31 : IGN:          <==>         400

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