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https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
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ZTEX |
MIG: 21:37:37 : ################# RUNNING MIG BATCH ###################
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MIG: 21:37:37 : MIG::Writing IN file for 'mig_7series_0'...compDirPath: /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_2... instDirPath: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0
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MIG: 21:37:37 : synp_flow: -- synthesis_mode: Other
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MIG: 21:37:37 : outputDirectory: /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
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MIG: 21:37:37 : vivado_mode: xpg_pa
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MIG: 21:37:37 : HDL Language: Verilog
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MIG: 21:37:37 : compInfo: false
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MIG: 21:37:37 : Vivado Options xc7a100t csg324 -2
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MIG: 21:37:37 : 1: xc7a100t 2: csg324 3: -2
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MIG: 21:37:37 : relative mig path: coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_2/bin/lin/mig
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MIG: 21:37:37 : xilinx_path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE
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MIG: 21:37:37 : Without MYMIG
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MIG: 21:37:37 : mig_exec path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_2/bin/lin/mig
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MIG: 21:37:37 : mig_exec path: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_2/bin/lin/mig
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MIG: 21:37:37 : mig_bin: /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_2/bin/lin/mig
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MIG: 21:37:37 : /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_2/bin/lin/mig -- /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_upgrade.out -- /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_upgrade.in
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MIG: 21:37:37 : Running /drv_s2/xilinx/Vivado/2014.4/ids_lite/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_7series_v2_2/bin/lin/mig -cg_exc_inp /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_upgrade.in -cg_exc_out /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.13/memfifo.srcs/sources_1/ip/mig_7series_0/xil_upgrade.out ...
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