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ZTEX |
2014.4:
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* Version 2.3
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* Updated maximum frequencies and controller rates as per specifications listed in 7 Series and Zync DC and Switching Characteristics Datasheets
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* DDR3 write calibration changes
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2014.3:
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* Version 2.2
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* DDR3 SDRAM, DDR2 SDRAM, RLDRAM II, LPDDR2 SDRAM, QDRIIPLUS SRAM max supported frequencies updated. See (Xilinx Answer 61853) for details."
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* Resolved (Xilinx Answer 61744) "MIG 7 Series DDR3 - ECC Multiple errors are seen in hardware when targeting Vivado 2014.2. Errors were not seen in previous versions."
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* Resolved (Xilinx Answer 61521) "MIG 7 Series - Cannot generate data width greater than 8-bits for CPG325 packages"
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* Resolved (Xilinx Answer 60480) "MIG 7 Series - Receiving ERROR [Drc 23-20] when CLOCK_DEDICATED_ROUTE set to BACKBONE but backbone resources are not used"
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* Resolved (Xilinx Answer 60051) "MIG 7 Series DDR3 - VCS simulations fail with unresolved modules"
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2014.2:
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* Version 2.1
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* DDR3 clocking and read path calibration updates. Refer to Answer Record 60470 for details
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* Addition of Artix-7Q(xq7a50t-cs325,xq7a50t-fg484) and XAZynq (xa7z030-fbg484) devices
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2014.1:
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* Version 2.0 (Rev. 3)
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* Extended IES and VCS support to Multi-Controller and Multi-Interface designs
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2013.4:
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* Version 2.0 (Rev. 2)
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* Added OOC support
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* Added support for IES and VCS Simulators
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2013.3:
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* Version 2.0 (Rev. 1)
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* Added support for ILA 3.0 and VIO 3.0
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* Resolved controller hang issues on read-modify-write commands (See Xilinx Answer 54710)
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* Resolved Clock Driver Enable settings for RC1 on RDIMM interfaces (See Xilinx Answer 57279)
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* Updated Chipscope debug signals for OCLKDELAY calibration (See Xilinx Answer 54918)
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* Resolved timing failures with larger SSI devices (See Xilinx Answer 56385)
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* Added AXI addressing support over 32 bits for DDR2 and DDR3
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* Corrected Chip Select width for single rank RDIMM devices (See Xilinx Answer 57436)
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2013.2:
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* Version 2.0
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* 2013.2 software support
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* Added support for ILA 2.0 and VIO 2.0
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2013.1:
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* Version 1.9.a
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* 2013.1 software support
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* Questa SIM 10.1b Support
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* Synplify Pro supported version G-2012.09-SP1
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* Support of LPDDR2 SDRAM Verilog designs
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* System Reset Pin Polarity selection
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* Additional clocks selection for AXI interface designs
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(c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
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This file contains confidential and proprietary information
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of Xilinx, Inc. and is protected under U.S. and
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international copyright and other intellectual property
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laws.
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DISCLAIMER
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This disclaimer is not a license and does not grant any
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rights to the materials distributed herewith. Except as
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otherwise provided in a valid license issued to you by
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Xilinx, and to the maximum extent permitted by applicable
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law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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(2) Xilinx shall not be liable (whether in contract or tort,
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including negligence, or under any other theory of
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liability) for any loss or damage of any kind or nature
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related to, arising under or in connection with these
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materials, including for any direct, or any indirect,
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special, incidental, or consequential loss or damage
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(including loss of data, profits, goodwill, or any type of
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loss or damage suffered as a result of any action brought
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by a third party) even if such damage or loss was
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reasonably foreseeable or Xilinx had been advised of the
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possibility of the same.
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CRITICAL APPLICATIONS
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Xilinx products are not designed or intended to be fail-
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safe, or for use in any application requiring fail-safe
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performance, such as life-support or safety devices or
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systems, Class III medical devices, nuclear facilities,
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applications related to the deployment of airbags, or any
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other applications that could lead to death, personal
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injury, or severe property or environmental damage
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(individually and collectively, "Critical
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Applications"). Customer assumes the sole risk and
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liability of any use of Xilinx products in Critical
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Applications, subject only to applicable laws and
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regulations governing limitations on product liability.
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THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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PART OF THIS FILE AT ALL TIMES.
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