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//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version: %version

//  \   \         Application: MIG

//  /   /         Filename: ddr_calib_top.v

// /___/   /\     Date Last Modified: $Date: 2011/06/02 08:35:06 $

// \   \  /  \    Date Created: Aug 03 2009

//  \___\/\___\

//

//Device: 7 Series

//Design Name: DDR3 SDRAM

//Purpose:

//Purpose:

//   Top-level for memory physical layer (PHY) interface

//   NOTES:

//     1. Need to support multiple copies of CS outputs

//     2. DFI_DRAM_CKE_DISABLE not supported

//

//Reference:

//Revision History:

//*****************************************************************************

/******************************************************************************

**$Id: ddr_calib_top.v,v 1.1 2011/06/02 08:35:06 mishra Exp $

**$Date: 2011/06/02 08:35:06 $

**$Author: mishra $

**$Revision: 1.1 $

**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_calib_top.v,v $

******************************************************************************/

`timescale 1ps/1ps

module mig_7series_v2_3_ddr_calib_top #

  (

   parameter TCQ             = 100,

   parameter nCK_PER_CLK     = 2,       // # of memory clocks per CLK

   parameter tCK             = 2500,    // DDR3 SDRAM clock period

   parameter DDR3_VDD_OP_VOLT = "135",     // Voltage mode used for DDR3

   parameter CLK_PERIOD      = 3333,    // Internal clock period (in ps)

   parameter N_CTL_LANES     = 3,       // # of control byte lanes in the PHY

   parameter DRAM_TYPE       = "DDR3",  // Memory I/F type: "DDR3", "DDR2"

   parameter PRBS_WIDTH      = 8,      // The PRBS sequence is 2^PRBS_WIDTH

   parameter HIGHEST_LANE    = 4,

   parameter HIGHEST_BANK    = 3,

   parameter BANK_TYPE       = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"

   // five fields, one per possible I/O bank, 4 bits in each field, 

   // 1 per lane data=1/ctl=0

   parameter DATA_CTL_B0     = 4'hc,

   parameter DATA_CTL_B1     = 4'hf,

   parameter DATA_CTL_B2     = 4'hf,

   parameter DATA_CTL_B3     = 4'hf,

   parameter DATA_CTL_B4     = 4'hf,

   // defines the byte lanes in I/O banks being used in the interface

   // 1- Used, 0- Unused

   parameter BYTE_LANES_B0   = 4'b1111,

   parameter BYTE_LANES_B1   = 4'b0000,

   parameter BYTE_LANES_B2   = 4'b0000,

   parameter BYTE_LANES_B3   = 4'b0000,

   parameter BYTE_LANES_B4   = 4'b0000,

   parameter DQS_BYTE_MAP

     = 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,

   parameter CTL_BYTE_LANE   = 8'hE4,    // Control byte lane map

   parameter CTL_BANK        = 3'b000,  // Bank used for control byte lanes   

   // Slot Conifg parameters

   parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,

   // DRAM bus widths

   parameter BANK_WIDTH      = 2,       // # of bank bits

   parameter CA_MIRROR       = "OFF",   // C/A mirror opt for DDR3 dual rank

   parameter COL_WIDTH       = 10,      // column address width

   parameter nCS_PER_RANK    = 1,       // # of unique CS outputs per rank

   parameter DQ_WIDTH        = 64,      // # of DQ (data)

   parameter DQS_CNT_WIDTH   = 3,       // = ceil(log2(DQS_WIDTH))

   parameter DQS_WIDTH       = 8,       // # of DQS (strobe)

   parameter DRAM_WIDTH      = 8,       // # of DQ per DQS

   parameter ROW_WIDTH       = 14,      // DRAM address bus width

   parameter RANKS           = 1,       // # of memory ranks in the interface

   parameter CS_WIDTH        = 1,       // # of CS# signals in the interface

   parameter CKE_WIDTH       = 1,       // # of cke outputs

   parameter DDR2_DQSN_ENABLE = "YES",  // Enable differential DQS for DDR2

   parameter PER_BIT_DESKEW  = "ON",

   // calibration Address. The address given below will be used for calibration

   // read and write operations. 

   parameter NUM_DQSFOUND_CAL = 1020,      // # of iteration of DQSFOUND calib 

   parameter CALIB_ROW_ADD   = 16'h0000,// Calibration row address

   parameter CALIB_COL_ADD   = 12'h000, // Calibration column address

   parameter CALIB_BA_ADD    = 3'h0,    // Calibration bank address 

   // DRAM mode settings

   parameter AL              = "0",     // Additive Latency option

   parameter TEST_AL         = "0",     // Additive Latency for internal use

   parameter ADDR_CMD_MODE   = "1T",    // ADDR/CTRL timing: "2T", "1T"

   parameter BURST_MODE      = "8",     // Burst length

   parameter BURST_TYPE      = "SEQ",   // Burst type

   parameter nCL             = 5,       // Read CAS latency (in clk cyc)

   parameter nCWL            = 5,       // Write CAS latency (in clk cyc)

   parameter tRFC            = 110000,  // Refresh-to-command delay

   parameter tREFI           = 7800000, // pS Refresh-to-Refresh delay

   parameter OUTPUT_DRV      = "HIGH",  // DRAM reduced output drive option

   parameter REG_CTRL        = "ON",    // "ON" for registered DIMM

   parameter RTT_NOM         = "60",    // ODT Nominal termination value

   parameter RTT_WR          = "60",    // ODT Write termination value

   parameter USE_ODT_PORT    = 0,       // 0 - No ODT output from FPGA

                                        // 1 - ODT output from FPGA

   parameter WRLVL           = "OFF",   // Enable write leveling

   parameter PRE_REV3ES       = "OFF",       // Delay O/Ps using Phaser_Out fine dly

   parameter POC_USE_METASTABLE_SAMP = "FALSE",

    // Simulation /debug options

   parameter SIM_INIT_OPTION = "NONE",  // Performs all initialization steps

   parameter SIM_CAL_OPTION  = "NONE",  // Performs all calibration steps

   parameter CKE_ODT_AUX     = "FALSE",

   parameter IDELAY_ADJ      = "ON",

   parameter FINE_PER_BIT    = "ON",

   parameter CENTER_COMP_MODE = "ON",

   parameter PI_VAL_ADJ       = "ON",

   parameter TAPSPERKCLK      = 56,

   parameter DEBUG_PORT       = "OFF"    // Enable debug port

   )

  (

   input                              clk,         // Internal (logic) clock

   input                              rst,         // Reset sync'ed to CLK

   // Slot present inputs

   input [7:0]                        slot_0_present,

   input [7:0]                        slot_1_present,

   // Hard PHY signals

   // From PHY Ctrl Block

   input                              phy_ctl_ready,

   input                              phy_ctl_full,

   input                              phy_cmd_full,

   input                              phy_data_full,

   // To PHY Ctrl Block

   output                             write_calib,

   output                             read_calib,

   output                             calib_ctl_wren,

   output                             calib_cmd_wren,

   output [1:0]                       calib_seq,

   output [3:0]                       calib_aux_out,

   output [nCK_PER_CLK -1:0]          calib_cke,

   output [1:0]                        calib_odt,

   output [2:0]                       calib_cmd,

   output                             calib_wrdata_en,

   output [1:0]                       calib_rank_cnt,

   output [1:0]                       calib_cas_slot,

   output [5:0]                       calib_data_offset_0,

   output [5:0]                       calib_data_offset_1,

   output [5:0]                       calib_data_offset_2,

   output [nCK_PER_CLK*ROW_WIDTH-1:0] phy_address,

   output [nCK_PER_CLK*BANK_WIDTH-1:0]phy_bank,

   output [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] phy_cs_n,

   output [nCK_PER_CLK-1:0]           phy_ras_n,

   output [nCK_PER_CLK-1:0]           phy_cas_n,

   output [nCK_PER_CLK-1:0]           phy_we_n,

   output                             phy_reset_n,

   // To hard PHY wrapper

 output reg [5:0] calib_sel/* synthesis syn_maxfan = 10 */,

 output reg       calib_in_common/* synthesis syn_maxfan = 10 */,

 output reg [HIGHEST_BANK-1:0] calib_zero_inputs/* synthesis syn_maxfan = 10 */,

   output reg [HIGHEST_BANK-1:0]      calib_zero_ctrl,

   output                             phy_if_empty_def,

   output reg                         phy_if_reset,

//   output reg                         ck_addr_ctl_delay_done,

   // From DQS Phaser_In

   input                              pi_phaselocked,

   input                              pi_phase_locked_all,

   input                              pi_found_dqs,

   input                              pi_dqs_found_all,

   input [HIGHEST_LANE-1:0]           pi_dqs_found_lanes,

   input [5:0]                        pi_counter_read_val,

   // To DQS Phaser_In

   output [HIGHEST_BANK-1:0]          pi_rst_stg1_cal,

   output                             pi_en_stg2_f,

   output                             pi_stg2_f_incdec,

   output                             pi_stg2_load,

   output [5:0]                       pi_stg2_reg_l,

   // To DQ IDELAY

   output                             idelay_ce,

   output                             idelay_inc,

   output                             idelay_ld,

   // To DQS Phaser_Out

 output [2:0]       po_sel_stg2stg3 /* synthesis syn_maxfan = 3 */,

 output [2:0]       po_stg2_c_incdec /* synthesis syn_maxfan = 3 */,

 output [2:0]       po_en_stg2_c /* synthesis syn_maxfan = 3 */,

 output [2:0]       po_stg2_f_incdec /* synthesis syn_maxfan = 3 */,

 output [2:0]       po_en_stg2_f /* synthesis syn_maxfan = 3 */,

   output                             po_counter_load_en,

   input [8:0]                        po_counter_read_val,

   // To command Phaser_Out

   input                              phy_if_empty,

   input [4:0]                        idelaye2_init_val,

   input [5:0]                        oclkdelay_init_val,

   input                              tg_err,

   output                             rst_tg_mc,

   // Write data to OUT_FIFO

   output [2*nCK_PER_CLK*DQ_WIDTH-1:0]phy_wrdata,

   // To CNTVALUEIN input of DQ IDELAYs for perbit de-skew

   output [5*RANKS*DQ_WIDTH-1:0]      dlyval_dq,

   // IN_FIFO read enable during write leveling, write calibration,

   // and read leveling

   // Read data from hard PHY fans out to mc and calib logic

   input[2*nCK_PER_CLK*DQ_WIDTH-1:0]  phy_rddata,

   // To MC

   output [6*RANKS-1:0]               calib_rd_data_offset_0,

   output [6*RANKS-1:0]               calib_rd_data_offset_1,

   output [6*RANKS-1:0]               calib_rd_data_offset_2,

   output                             phy_rddata_valid,

   output                             calib_writes,

   (* max_fanout = 50 *) output reg   init_calib_complete/* synthesis syn_maxfan = 10 */,

   output                             init_wrcal_complete,

   output                             pi_phase_locked_err,

   output                             pi_dqsfound_err,

   output                             wrcal_err,

   input                              pd_out,

  // input                              mmcm_ps_clk,  //phase shift clock

  // input                              oclkdelay_fb_clk,  //Write DQS feedback clk 

   //phase shift clock control

   output                             psen,

   output                             psincdec,

   input                              psdone,

   input                              poc_sample_pd,

   // Debug Port

   output                             dbg_pi_phaselock_start,

   output                             dbg_pi_dqsfound_start,

   output                             dbg_pi_dqsfound_done,

   output                             dbg_wrcal_start,

   output                             dbg_wrcal_done,

   output                             dbg_wrlvl_start,

   output                             dbg_wrlvl_done,

   output                             dbg_wrlvl_err,

   output [6*DQS_WIDTH-1:0]           dbg_wrlvl_fine_tap_cnt,

   output [3*DQS_WIDTH-1:0]           dbg_wrlvl_coarse_tap_cnt,

   output [255:0]                     dbg_phy_wrlvl,

   output [5:0]                       dbg_tap_cnt_during_wrlvl,

   output                             dbg_wl_edge_detect_valid,

   output [DQS_WIDTH-1:0]             dbg_rd_data_edge_detect,

   // Write Calibration Logic

   output [6*DQS_WIDTH-1:0]           dbg_final_po_fine_tap_cnt,

   output [3*DQS_WIDTH-1:0]           dbg_final_po_coarse_tap_cnt,

   output [99:0]                      dbg_phy_wrcal,

   // Read leveling logic

   output [1:0]                       dbg_rdlvl_start,

   output [1:0]                       dbg_rdlvl_done,

   output [1:0]                       dbg_rdlvl_err,

   output [6*DQS_WIDTH*RANKS-1:0]     dbg_cpt_first_edge_cnt,

   output [6*DQS_WIDTH*RANKS-1:0]     dbg_cpt_second_edge_cnt,

   output [6*DQS_WIDTH*RANKS-1:0]     dbg_cpt_tap_cnt,

   output [5*DQS_WIDTH*RANKS-1:0]     dbg_dq_idelay_tap_cnt,

   // Delay control

   input  [11:0]                      device_temp,

   input                              tempmon_sample_en,

   input                              dbg_sel_pi_incdec,

   input                              dbg_sel_po_incdec,

   input [DQS_CNT_WIDTH:0]            dbg_byte_sel,

   input                              dbg_pi_f_inc,

   input                              dbg_pi_f_dec,

   input                              dbg_po_f_inc,

   input                              dbg_po_f_stg23_sel,

   input                              dbg_po_f_dec,

   input                              dbg_idel_up_all,

   input                              dbg_idel_down_all,

   input                              dbg_idel_up_cpt,

   input                              dbg_idel_down_cpt,

   input [DQS_CNT_WIDTH-1:0]          dbg_sel_idel_cpt,

   input                              dbg_sel_all_idel_cpt,

   output [255:0]                     dbg_phy_rdlvl, // Read leveling calibration

   output [255:0]                     dbg_calib_top,   // General PHY debug

   output                             dbg_oclkdelay_calib_start,

   output                             dbg_oclkdelay_calib_done,

   output [255:0]                     dbg_phy_oclkdelay_cal,

   output [DRAM_WIDTH*16 -1:0]        dbg_oclkdelay_rd_data,

   output [255:0]                     dbg_phy_init,

   output [255:0]                     dbg_prbs_rdlvl,

   output [255:0]                     dbg_dqs_found_cal,

   output [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r,

   output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,

   output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,

   output reg [DQS_CNT_WIDTH:0]   byte_sel_cnt,

   output [DRAM_WIDTH-1:0]        fine_delay_incdec_pb,  //fine_delay decreament per bit

   output                         fine_delay_sel

   );

   function integer clogb2 (input integer size);

    begin

      size = size - 1;

      for (clogb2=1; size>1; clogb2=clogb2+1)

        size = size >> 1;

    end

   endfunction

// Advance ODELAY of DQ by extra 0.25*tCK (quarter clock cycle) to center

// align DQ and DQS on writes. Round (up or down) value to nearest integer

// localparam integer SHIFT_TBY4_TAP

//             = (CLK_PERIOD + (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*2)-1) /

//             (nCK_PER_CLK*(1000000/(REFCLK_FREQ*64))*4);

// Calculate number of slots in the system

  localparam nSLOTS  = 1 + (|SLOT_1_CONFIG ? 1 : 0);

  localparam OCAL_EN = ((SIM_CAL_OPTION == "FAST_CAL") || (tCK > 2500)) ? "OFF" : "ON";

  // Different CTL_LANES value for DDR2. In DDR2 during DQS found all 

  // the add,ctl & data phaser out fine delays will be adjusted. 

  // In DDR3 only the add/ctrl lane delays will be adjusted 

  localparam DQS_FOUND_N_CTL_LANES = (DRAM_TYPE == "DDR3") ? N_CTL_LANES : 1;

  localparam DQSFOUND_CAL    = (BANK_TYPE == "HR_IO" || BANK_TYPE == "HRL_IO" || (BANK_TYPE == "HPL_IO" && tCK > 2500)) ? "LEFT" : "RIGHT"; // IO Bank used for Memory I/F: "LEFT", "RIGHT"

  localparam FIXED_VICTIM  = (SIM_CAL_OPTION == "NONE") ? "FALSE" : "TRUE";

  localparam VCCO_PAT_EN   = 1;  // Enable VCCO pattern during calibration

  localparam VCCAUX_PAT_EN = 1;  // Enable VCCAUX pattern during calibration

  localparam ISI_PAT_EN    = 1;  // Enable VCCO pattern during calibration

  //Per-bit deskew for higher freqency (>800Mhz)

  //localparam FINE_DELAY = (tCK < 1250) ? "ON" : "OFF";

  //BYPASS

  localparam BYPASS_COMPLEX_RDLVL = (tCK > 2500) ? "TRUE": "FALSE"; //"TRUE";

  localparam BYPASS_COMPLEX_OCAL = "TRUE";

  //localparam BYPASS_COMPLEX_OCAL = ((DRAM_TYPE == "DDR2") || (nCK_PER_CLK == 2) || (OCAL_EN == "OFF")) ? "TRUE" : "FALSE";

  // 8*tREFI in ps is divided by the fabric clock period in ps

  // 270 fabric clock cycles is subtracted to account for PRECHARGE, WR, RD times

  localparam REFRESH_TIMER = (SIM_CAL_OPTION == "NONE") ? (8*tREFI/(tCK*nCK_PER_CLK)) - 270 : 10795;

  localparam REFRESH_TIMER_WIDTH = clogb2(REFRESH_TIMER);

  wire [2*8*nCK_PER_CLK-1:0]          prbs_seed;

  //wire [2*8*nCK_PER_CLK-1:0]          prbs_out;

  wire [8*DQ_WIDTH-1:0]               prbs_out;

  wire [7:0]                          prbs_rise0;

  wire [7:0]                          prbs_fall0;

  wire [7:0]                          prbs_rise1;

  wire [7:0]                          prbs_fall1;

  wire [7:0]                          prbs_rise2;

  wire [7:0]                          prbs_fall2;

  wire [7:0]                          prbs_rise3;

  wire [7:0]                          prbs_fall3;

  //wire [2*8*nCK_PER_CLK-1:0]          prbs_o;

  wire [2*nCK_PER_CLK*DQ_WIDTH-1:0]   prbs_o;

  wire                                dqsfound_retry;

  wire                                dqsfound_retry_done;

  wire                                phy_rddata_en;

  wire                                prech_done;

  wire                                rdlvl_stg1_done;

  reg                                 rdlvl_stg1_done_r1;

  wire                                pi_dqs_found_done;

  wire                                rdlvl_stg1_err;

  wire                                pi_dqs_found_err;

  wire                                wrcal_pat_resume;

  wire                                wrcal_resume_w;

  wire                                rdlvl_prech_req;

  wire                                rdlvl_last_byte_done;

  wire                                rdlvl_stg1_start;

  wire                                rdlvl_stg1_rank_done;

  wire                                rdlvl_assrt_common;

  wire                                pi_dqs_found_start;

  wire                                pi_dqs_found_rank_done;

  wire                                wl_sm_start;

  wire                                wrcal_start;

  wire                                wrcal_rd_wait;

  wire                                wrcal_prech_req;

  wire                                wrcal_pat_err;

  wire                                wrcal_done;

  wire                                wrlvl_done;

  wire                                wrlvl_err;

  wire                                wrlvl_start;

  wire                                ck_addr_cmd_delay_done;

  wire                                po_ck_addr_cmd_delay_done;

  wire                                pi_calib_done;

  wire                                detect_pi_found_dqs;

  wire [5:0]                          rd_data_offset_0;

  wire [5:0]                          rd_data_offset_1;

  wire [5:0]                          rd_data_offset_2;

  wire [6*RANKS-1:0]                  rd_data_offset_ranks_0;

  wire [6*RANKS-1:0]                  rd_data_offset_ranks_1;

  wire [6*RANKS-1:0]                  rd_data_offset_ranks_2;

  wire [6*RANKS-1:0]                  rd_data_offset_ranks_mc_0;

  wire [6*RANKS-1:0]                  rd_data_offset_ranks_mc_1;

  wire [6*RANKS-1:0]                  rd_data_offset_ranks_mc_2;

  wire                                cmd_po_stg2_f_incdec;

  wire                                cmd_po_stg2_incdec_ddr2_c;

  wire                                cmd_po_en_stg2_f;

  wire                                cmd_po_en_stg2_ddr2_c;

  wire                                cmd_po_stg2_c_incdec;

  wire                                cmd_po_en_stg2_c;

  wire                                po_stg2_ddr2_incdec;

  wire                                po_en_stg2_ddr2;

  wire                                dqs_po_stg2_f_incdec;

  wire                                dqs_po_en_stg2_f;

  wire                                dqs_wl_po_stg2_c_incdec;

  wire                                wrcal_po_stg2_c_incdec;

  wire                                dqs_wl_po_en_stg2_c;

  wire                                wrcal_po_en_stg2_c;

  wire [N_CTL_LANES-1:0]              ctl_lane_cnt;

  reg [N_CTL_LANES-1:0]               ctl_lane_sel;

  wire [DQS_CNT_WIDTH:0]              po_stg2_wrcal_cnt;

  wire [DQS_CNT_WIDTH:0]              po_stg2_wl_cnt;

  wire [DQS_CNT_WIDTH:0]              po_stg2_ddr2_cnt;

  wire [8:0]                          dqs_wl_po_stg2_reg_l;

  wire                                dqs_wl_po_stg2_load;

  wire [8:0]                          dqs_po_stg2_reg_l;

  wire                                dqs_po_stg2_load;

  wire                                dqs_po_dec_done;

  wire                                pi_fine_dly_dec_done;

  wire                                rdlvl_pi_stg2_f_incdec;

  wire                                rdlvl_pi_stg2_f_en;

  wire [DQS_CNT_WIDTH:0]              pi_stg2_rdlvl_cnt;

  //reg [DQS_CNT_WIDTH:0]               byte_sel_cnt;

  wire [3*DQS_WIDTH-1:0]              wl_po_coarse_cnt;

  wire [6*DQS_WIDTH-1:0]              wl_po_fine_cnt;

  wire                                phase_locked_err;

  wire                                phy_ctl_rdy_dly;

  wire                                idelay_ce_int;

  wire                                idelay_inc_int;

  reg                                 idelay_ce_r1;

  reg                                 idelay_ce_r2;

  reg                                 idelay_inc_r1;

 reg        idelay_inc_r2 /* synthesis syn_maxfan = 30 */;

  reg                                 po_dly_req_r;

  wire                                wrcal_read_req;

  wire                                wrcal_act_req;

  wire                                temp_wrcal_done;

  wire                                tg_timer_done;

  wire                                no_rst_tg_mc;

  wire                                calib_complete;

  reg                                 reset_if_r1;

  reg                                 reset_if_r2;

  reg                                 reset_if_r3;

  reg                                 reset_if_r4;

  reg                                 reset_if_r5;

  reg                                 reset_if_r6;

  reg                                 reset_if_r7;

  reg                                 reset_if_r8;

  reg                                 reset_if_r9;

  reg                                 reset_if;

  wire                                phy_if_reset_w;

  wire                                pi_phaselock_start;

  reg                                 dbg_pi_f_inc_r;

  reg                                 dbg_pi_f_en_r;

  reg                                 dbg_sel_pi_incdec_r;

  reg                                 dbg_po_f_inc_r;

  reg                                 dbg_po_f_stg23_sel_r;

  reg                                 dbg_po_f_en_r;

  reg                                 dbg_sel_po_incdec_r;

  reg                                 tempmon_pi_f_inc_r;

  reg                                 tempmon_pi_f_en_r;

  reg                                 tempmon_sel_pi_incdec_r;

  reg                                 ck_addr_cmd_delay_done_r1;

  reg                                 ck_addr_cmd_delay_done_r2;

  reg                                 ck_addr_cmd_delay_done_r3;

  reg                                 ck_addr_cmd_delay_done_r4;

  reg                                 ck_addr_cmd_delay_done_r5;

  reg                                 ck_addr_cmd_delay_done_r6;

//  wire                                oclk_init_delay_start;

  wire                                oclk_prech_req;

  wire                                oclk_calib_resume;

//  wire                                oclk_init_delay_done;

  wire [DQS_CNT_WIDTH:0]              oclkdelay_calib_cnt;

  wire [DQS_CNT_WIDTH:0]              complex_oclkdelay_calib_cnt;

  wire                                oclkdelay_calib_start;

  wire                                oclkdelay_calib_done;

  wire                                complex_oclk_prech_req;

  wire                                complex_oclk_calib_resume;

  wire                                complex_oclkdelay_calib_start;

  wire                                complex_oclkdelay_calib_done;

  wire                                complex_ocal_num_samples_inc;

  wire                                complex_ocal_num_samples_done_r;

  wire [2:0]                          complex_ocal_rd_victim_sel;

  wire                                complex_ocal_ref_req;

  wire                                complex_ocal_ref_done;

  wire [6*DQS_WIDTH-1:0]              oclkdelay_left_edge_val;

  wire [6*DQS_WIDTH-1:0]              oclkdelay_right_edge_val;

  wire                                wrlvl_final;

  wire                                complex_wrlvl_final;

  reg                                 wrlvl_final_mux;

  wire                                wrlvl_final_if_rst;

  wire                                wrlvl_byte_redo;

  wire                                wrlvl_byte_done;

  wire                                early1_data;

  wire                                early2_data;

  //wire                                po_stg3_incdec;

  //wire                                po_en_stg3;

  wire                                po_stg23_sel;

  wire                                po_stg23_incdec;

  wire                                po_en_stg23;

  wire                                complex_po_stg23_sel;

  wire                                complex_po_stg23_incdec;

  wire                                complex_po_en_stg23;

  wire                                mpr_rdlvl_done;

  wire                                mpr_rdlvl_start;

  wire                                mpr_last_byte_done;

  wire                                mpr_rnk_done;

  wire                                mpr_end_if_reset;

  wire                                mpr_rdlvl_err;

  wire                                rdlvl_err;

  wire                                prbs_rdlvl_start;

  wire                                prbs_rdlvl_done;

  reg                                 prbs_rdlvl_done_r1;

  wire                                prbs_last_byte_done;

  wire                                prbs_rdlvl_prech_req;

  wire                                prbs_pi_stg2_f_incdec;

  wire                                prbs_pi_stg2_f_en;

  wire                                complex_sample_cnt_inc;

  wire                                complex_sample_cnt_inc_ocal;

  wire [DQS_CNT_WIDTH:0]              pi_stg2_prbs_rdlvl_cnt;

  wire                                prbs_gen_clk_en;

  wire                                prbs_gen_oclk_clk_en;

  wire                                rd_data_offset_cal_done;

  wire                                fine_adjust_done;

  wire [N_CTL_LANES-1:0]              fine_adjust_lane_cnt;

  wire                                ck_po_stg2_f_indec;

  wire                                ck_po_stg2_f_en;

  wire                                dqs_found_prech_req;

  wire                                tempmon_pi_f_inc;

  wire                                tempmon_pi_f_dec;

  wire                                tempmon_sel_pi_incdec;

  wire                                wrcal_sanity_chk;

  wire                                wrcal_sanity_chk_done;

  wire                                wrlvl_done_w;

  wire                                wrlvl_rank_done;

  wire                                done_dqs_tap_inc;

  wire [2:0]                          rd_victim_sel;

  wire [2:0]                          victim_sel;

  wire [DQS_CNT_WIDTH:0]              victim_byte_cnt;

  wire                                complex_wr_done;

  wire                                complex_victim_inc;

  wire                                reset_rd_addr;

  wire                                read_pause;

  wire                                complex_ocal_reset_rd_addr;

  wire                                oclkdelay_center_calib_start;

  wire                                poc_error;

  wire                                prbs_ignore_first_byte;

  wire                                prbs_ignore_last_bytes;

  //stg3 tap values 

 // wire [6*DQS_WIDTH-1:0]              oclkdelay_center_val;

   //byte selection

 // wire [DQS_CNT_WIDTH:0]              oclkdelay_center_cnt;

   //INC/DEC for stg3 taps

 // wire                                ocal_ctr_po_stg23_sel;

 // wire                                ocal_ctr_po_stg23_incdec;

 // wire                                ocal_ctr_po_en_stg23;

  //Write resume for DQS toggling 

  wire                                oclk_center_write_resume;

  wire                                oclkdelay_center_calib_done;

  //Write request to toggle DQS for limit module

  wire                                lim2init_write_request;

  wire                                lim_done;

  // Bypass complex ocal

  wire                                complex_oclkdelay_calib_start_w;

  wire                                complex_oclkdelay_calib_done_w;

  wire [2:0]                          complex_ocal_rd_victim_sel_w;

  wire                                complex_wrlvl_final_w;

  wire [255:0]                        dbg_ocd_lim;

   //with MMCM phase detect logic

  //wire                                mmcm_edge_detect_rdy;    // ready for MMCM detect

  //wire                                ktap_at_rightedge;       // stg3 tap at right edge

  //wire                                ktap_at_leftedge;        // stg3 tap at left edge

  //wire                                mmcm_tap_at_center;     // indicate stg3 tap at center

  //wire                                mmcm_ps_clkphase_ok;    // ps clkphase is OK 

  //wire                                mmcm_edge_detect_done;  // mmcm edge detect is done

  //wire                                mmcm_lbclk_edges_aligned; // mmcm edge detect is done

  //wire                                reset_mmcm;             //mmcm detect logic reset per byte

 // wire [255:0]                        dbg_phy_oclkdelay_center_cal;

  //*****************************************************************************

  // Assertions to check correctness of parameter values

  //*****************************************************************************

  // synthesis translate_off

  initial

  begin

    if (RANKS == 0) begin

      $display ("Error: Invalid RANKS parameter. Must be 1 or greater");

      $finish;