Subversion Repositories usb_fpga_2_14

/***********************************************************

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//

//

//  Owner:        Gary Martin

//  Revision:     $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $

//                $Author: gary $

//                $DateTime: 2010/05/11 18:05:17 $

//                $Change: 490882 $

//  Description:

//    This verilog file is a parameterizable wrapper instantiating

//    up to 5 memory banks of 4-lane phy primitives. There

//    There are always 2 control banks leaving 18 lanes for data.

//

//  History:

//  Date        Engineer    Description

//  04/01/2010  G. Martin   Initial Checkin.

//

////////////////////////////////////////////////////////////

***********************************************************/

`timescale 1ps/1ps

module mig_7series_v2_3_ddr_mc_phy

 #(

// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0

      parameter        BYTE_LANES_B0                 = 4'b1111,

      parameter        BYTE_LANES_B1                 = 4'b0000,

      parameter        BYTE_LANES_B2                 = 4'b0000,

      parameter        BYTE_LANES_B3                 = 4'b0000,

      parameter        BYTE_LANES_B4                 = 4'b0000,

      parameter        DATA_CTL_B0                   = 4'hc,

      parameter        DATA_CTL_B1                   = 4'hf,

      parameter        DATA_CTL_B2                   = 4'hf,

      parameter        DATA_CTL_B3                   = 4'hf,

      parameter        DATA_CTL_B4                   = 4'hf,

      parameter        RCLK_SELECT_BANK              = 0,

      parameter        RCLK_SELECT_LANE              = "B",

      parameter        RCLK_SELECT_EDGE              = 4'b1111,

      parameter        GENERATE_DDR_CK_MAP           = "0B",

      parameter        BYTELANES_DDR_CK              = 72'h00_0000_0000_0000_0002,

      parameter        USE_PRE_POST_FIFO             = "TRUE",

      parameter        SYNTHESIS                     = "FALSE",

      parameter        PO_CTL_COARSE_BYPASS          = "FALSE",

      parameter        PI_SEL_CLK_OFFSET             = 6,

      parameter        PHYCTL_CMD_FIFO               = "FALSE",

      parameter        PHY_CLK_RATIO                 = 4,          // phy to controller divide ratio

// common to all i/o banks

      parameter        PHY_FOUR_WINDOW_CLOCKS        = 63,

      parameter        PHY_EVENTS_DELAY              = 18,

      parameter        PHY_COUNT_EN                  = "TRUE",

      parameter        PHY_SYNC_MODE                 = "TRUE",

      parameter        PHY_DISABLE_SEQ_MATCH         = "FALSE",

      parameter        MASTER_PHY_CTL                = 0,

// common to instance 0

      parameter        PHY_0_BITLANES                = 48'hdffd_fffe_dfff,

      parameter        PHY_0_BITLANES_OUTONLY        = 48'h0000_0000_0000,

      parameter        PHY_0_LANE_REMAP              = 16'h3210,

      parameter        PHY_0_GENERATE_IDELAYCTRL     = "FALSE",

      parameter        PHY_0_IODELAY_GRP             = "IODELAY_MIG",

      parameter        FPGA_SPEED_GRADE              = 1,

      parameter        BANK_TYPE                     = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"

      parameter        NUM_DDR_CK                    = 1,

      parameter        PHY_0_DATA_CTL                = DATA_CTL_B0,

      parameter        PHY_0_CMD_OFFSET              = 0,

      parameter        PHY_0_RD_CMD_OFFSET_0         = 0,

      parameter        PHY_0_RD_CMD_OFFSET_1         = 0,

      parameter        PHY_0_RD_CMD_OFFSET_2         = 0,

      parameter        PHY_0_RD_CMD_OFFSET_3         = 0,

      parameter        PHY_0_RD_DURATION_0           = 0,

      parameter        PHY_0_RD_DURATION_1           = 0,

      parameter        PHY_0_RD_DURATION_2           = 0,

      parameter        PHY_0_RD_DURATION_3           = 0,

      parameter        PHY_0_WR_CMD_OFFSET_0         = 0,

      parameter        PHY_0_WR_CMD_OFFSET_1         = 0,

      parameter        PHY_0_WR_CMD_OFFSET_2         = 0,

      parameter        PHY_0_WR_CMD_OFFSET_3         = 0,

      parameter        PHY_0_WR_DURATION_0           = 0,

      parameter        PHY_0_WR_DURATION_1           = 0,

      parameter        PHY_0_WR_DURATION_2           = 0,

      parameter        PHY_0_WR_DURATION_3           = 0,

      parameter        PHY_0_AO_WRLVL_EN             = 0,

      parameter        PHY_0_AO_TOGGLE               = 4'b0101, // odd bits are toggle (CKE)

      parameter        PHY_0_OF_ALMOST_FULL_VALUE    = 1,

      parameter        PHY_0_IF_ALMOST_EMPTY_VALUE   = 1,

// per lane parameters

      parameter        PHY_0_A_PI_FREQ_REF_DIV       = "NONE",

      parameter        PHY_0_A_PI_CLKOUT_DIV         = 2,

      parameter        PHY_0_A_PO_CLKOUT_DIV         = 2,

      parameter        PHY_0_A_BURST_MODE            = "TRUE",

      parameter        PHY_0_A_PI_OUTPUT_CLK_SRC     = "DELAYED_REF",

      parameter        PHY_0_A_PO_OUTPUT_CLK_SRC     = "DELAYED_REF",

      parameter        PHY_0_A_PO_OCLK_DELAY         = 25,

      parameter        PHY_0_B_PO_OCLK_DELAY         = PHY_0_A_PO_OCLK_DELAY,

      parameter        PHY_0_C_PO_OCLK_DELAY         = PHY_0_A_PO_OCLK_DELAY,

      parameter        PHY_0_D_PO_OCLK_DELAY         = PHY_0_A_PO_OCLK_DELAY,

      parameter        PHY_0_A_PO_OCLKDELAY_INV      = "FALSE",

      parameter        PHY_0_A_OF_ARRAY_MODE         = "ARRAY_MODE_8_X_4",

      parameter        PHY_0_B_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_0_C_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_0_D_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_0_A_IF_ARRAY_MODE         = "ARRAY_MODE_8_X_4",

      parameter        PHY_0_B_IF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_0_C_IF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_0_D_IF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_0_A_OSERDES_DATA_RATE     = "UNDECLARED",

      parameter        PHY_0_A_OSERDES_DATA_WIDTH    = "UNDECLARED",

      parameter        PHY_0_B_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_0_B_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_0_C_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_0_C_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_0_D_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_0_D_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_0_A_IDELAYE2_IDELAY_TYPE  = "VARIABLE",

      parameter        PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,

      parameter        PHY_0_B_IDELAYE2_IDELAY_TYPE  = PHY_0_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_0_C_IDELAYE2_IDELAY_TYPE  = PHY_0_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_0_D_IDELAYE2_IDELAY_TYPE  = PHY_0_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,

// common to instance 1

      parameter        PHY_1_BITLANES                = PHY_0_BITLANES,

      parameter        PHY_1_BITLANES_OUTONLY        = 48'h0000_0000_0000,

      parameter        PHY_1_LANE_REMAP              = 16'h3210,

      parameter        PHY_1_GENERATE_IDELAYCTRL     =  "FALSE",

      parameter        PHY_1_IODELAY_GRP             = PHY_0_IODELAY_GRP,

      parameter        PHY_1_DATA_CTL                = DATA_CTL_B1,

      parameter        PHY_1_CMD_OFFSET              = PHY_0_CMD_OFFSET,

      parameter        PHY_1_RD_CMD_OFFSET_0         = PHY_0_RD_CMD_OFFSET_0,

      parameter        PHY_1_RD_CMD_OFFSET_1         = PHY_0_RD_CMD_OFFSET_1,

      parameter        PHY_1_RD_CMD_OFFSET_2         = PHY_0_RD_CMD_OFFSET_2,

      parameter        PHY_1_RD_CMD_OFFSET_3         = PHY_0_RD_CMD_OFFSET_3,

      parameter        PHY_1_RD_DURATION_0           = PHY_0_RD_DURATION_0,

      parameter        PHY_1_RD_DURATION_1           = PHY_0_RD_DURATION_1,

      parameter        PHY_1_RD_DURATION_2           = PHY_0_RD_DURATION_2,

      parameter        PHY_1_RD_DURATION_3           = PHY_0_RD_DURATION_3,

      parameter        PHY_1_WR_CMD_OFFSET_0         = PHY_0_WR_CMD_OFFSET_0,

      parameter        PHY_1_WR_CMD_OFFSET_1         = PHY_0_WR_CMD_OFFSET_1,

      parameter        PHY_1_WR_CMD_OFFSET_2         = PHY_0_WR_CMD_OFFSET_2,

      parameter        PHY_1_WR_CMD_OFFSET_3         = PHY_0_WR_CMD_OFFSET_3,

      parameter        PHY_1_WR_DURATION_0           = PHY_0_WR_DURATION_0,

      parameter        PHY_1_WR_DURATION_1           = PHY_0_WR_DURATION_1,

      parameter        PHY_1_WR_DURATION_2           = PHY_0_WR_DURATION_2,

      parameter        PHY_1_WR_DURATION_3           = PHY_0_WR_DURATION_3,

      parameter        PHY_1_AO_WRLVL_EN             = PHY_0_AO_WRLVL_EN,

      parameter        PHY_1_AO_TOGGLE               = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)

      parameter        PHY_1_OF_ALMOST_FULL_VALUE    = 1,

      parameter        PHY_1_IF_ALMOST_EMPTY_VALUE   = 1,

// per lane parameters

      parameter        PHY_1_A_PI_FREQ_REF_DIV       = PHY_0_A_PI_FREQ_REF_DIV,

      parameter        PHY_1_A_PI_CLKOUT_DIV         = PHY_0_A_PI_CLKOUT_DIV,

      parameter        PHY_1_A_PO_CLKOUT_DIV         = PHY_0_A_PO_CLKOUT_DIV,

      parameter        PHY_1_A_BURST_MODE            = PHY_0_A_BURST_MODE,

      parameter        PHY_1_A_PI_OUTPUT_CLK_SRC     = PHY_0_A_PI_OUTPUT_CLK_SRC,

      parameter        PHY_1_A_PO_OUTPUT_CLK_SRC     = PHY_0_A_PO_OUTPUT_CLK_SRC ,

      parameter        PHY_1_A_PO_OCLK_DELAY         = PHY_0_A_PO_OCLK_DELAY,

      parameter        PHY_1_B_PO_OCLK_DELAY         = PHY_1_A_PO_OCLK_DELAY,

      parameter        PHY_1_C_PO_OCLK_DELAY         = PHY_1_A_PO_OCLK_DELAY,

      parameter        PHY_1_D_PO_OCLK_DELAY         = PHY_1_A_PO_OCLK_DELAY,

      parameter        PHY_1_A_PO_OCLKDELAY_INV      = PHY_0_A_PO_OCLKDELAY_INV,

      parameter        PHY_1_A_IDELAYE2_IDELAY_TYPE  = PHY_0_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_1_B_IDELAYE2_IDELAY_TYPE  = PHY_1_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_1_C_IDELAYE2_IDELAY_TYPE  = PHY_1_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_1_D_IDELAYE2_IDELAY_TYPE  = PHY_1_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_1_A_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_1_B_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_1_C_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_1_D_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_1_A_IF_ARRAY_MODE         = PHY_0_A_IF_ARRAY_MODE,

      parameter        PHY_1_B_IF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_1_C_IF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_1_D_IF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_1_A_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_1_A_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_1_B_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_1_B_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_1_C_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_1_C_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_1_D_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_1_D_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

// common to instance 2

      parameter        PHY_2_BITLANES                = PHY_0_BITLANES,

      parameter        PHY_2_BITLANES_OUTONLY        = 48'h0000_0000_0000,

      parameter        PHY_2_LANE_REMAP              = 16'h3210,

      parameter        PHY_2_GENERATE_IDELAYCTRL     =  "FALSE",

      parameter        PHY_2_IODELAY_GRP             = PHY_0_IODELAY_GRP,

      parameter        PHY_2_DATA_CTL                = DATA_CTL_B2,

      parameter        PHY_2_CMD_OFFSET              = PHY_0_CMD_OFFSET,

      parameter        PHY_2_RD_CMD_OFFSET_0         = PHY_0_RD_CMD_OFFSET_0,

      parameter        PHY_2_RD_CMD_OFFSET_1         = PHY_0_RD_CMD_OFFSET_1,

      parameter        PHY_2_RD_CMD_OFFSET_2         = PHY_0_RD_CMD_OFFSET_2,

      parameter        PHY_2_RD_CMD_OFFSET_3         = PHY_0_RD_CMD_OFFSET_3,

      parameter        PHY_2_RD_DURATION_0           = PHY_0_RD_DURATION_0,

      parameter        PHY_2_RD_DURATION_1           = PHY_0_RD_DURATION_1,

      parameter        PHY_2_RD_DURATION_2           = PHY_0_RD_DURATION_2,

      parameter        PHY_2_RD_DURATION_3           = PHY_0_RD_DURATION_3,

      parameter        PHY_2_WR_CMD_OFFSET_0         = PHY_0_WR_CMD_OFFSET_0,

      parameter        PHY_2_WR_CMD_OFFSET_1         = PHY_0_WR_CMD_OFFSET_1,

      parameter        PHY_2_WR_CMD_OFFSET_2         = PHY_0_WR_CMD_OFFSET_2,

      parameter        PHY_2_WR_CMD_OFFSET_3         = PHY_0_WR_CMD_OFFSET_3,

      parameter        PHY_2_WR_DURATION_0           = PHY_0_WR_DURATION_0,

      parameter        PHY_2_WR_DURATION_1           = PHY_0_WR_DURATION_1,

      parameter        PHY_2_WR_DURATION_2           = PHY_0_WR_DURATION_2,

      parameter        PHY_2_WR_DURATION_3           = PHY_0_WR_DURATION_3,

      parameter        PHY_2_AO_WRLVL_EN             = PHY_0_AO_WRLVL_EN,

      parameter        PHY_2_AO_TOGGLE               = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)

      parameter        PHY_2_OF_ALMOST_FULL_VALUE    = 1,

      parameter        PHY_2_IF_ALMOST_EMPTY_VALUE   = 1,

// per lane parameters

      parameter        PHY_2_A_PI_FREQ_REF_DIV       = PHY_0_A_PI_FREQ_REF_DIV,

      parameter        PHY_2_A_PI_CLKOUT_DIV         = PHY_0_A_PI_CLKOUT_DIV ,

      parameter        PHY_2_A_PO_CLKOUT_DIV         = PHY_0_A_PO_CLKOUT_DIV,

      parameter        PHY_2_A_BURST_MODE            = PHY_0_A_BURST_MODE ,

      parameter        PHY_2_A_PI_OUTPUT_CLK_SRC     = PHY_0_A_PI_OUTPUT_CLK_SRC,

      parameter        PHY_2_A_PO_OUTPUT_CLK_SRC     = PHY_0_A_PO_OUTPUT_CLK_SRC,

      parameter        PHY_2_A_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_2_B_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_2_C_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_2_D_OF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_2_A_IF_ARRAY_MODE         = PHY_0_A_IF_ARRAY_MODE,

      parameter        PHY_2_B_IF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_2_C_IF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_2_D_IF_ARRAY_MODE         = PHY_0_A_OF_ARRAY_MODE,

      parameter        PHY_2_A_PO_OCLK_DELAY         = PHY_0_A_PO_OCLK_DELAY,

      parameter        PHY_2_B_PO_OCLK_DELAY         = PHY_2_A_PO_OCLK_DELAY,

      parameter        PHY_2_C_PO_OCLK_DELAY         = PHY_2_A_PO_OCLK_DELAY,

      parameter        PHY_2_D_PO_OCLK_DELAY         = PHY_2_A_PO_OCLK_DELAY,

      parameter        PHY_2_A_PO_OCLKDELAY_INV      = PHY_0_A_PO_OCLKDELAY_INV,

      parameter        PHY_2_A_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_2_A_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_2_B_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_2_B_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_2_C_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_2_C_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_2_D_OSERDES_DATA_RATE     = PHY_0_A_OSERDES_DATA_RATE,

      parameter        PHY_2_D_OSERDES_DATA_WIDTH    = PHY_0_A_OSERDES_DATA_WIDTH,

      parameter        PHY_2_A_IDELAYE2_IDELAY_TYPE  = PHY_0_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_2_B_IDELAYE2_IDELAY_TYPE  = PHY_2_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_2_C_IDELAYE2_IDELAY_TYPE  = PHY_2_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_2_D_IDELAYE2_IDELAY_TYPE  = PHY_2_A_IDELAYE2_IDELAY_TYPE,

      parameter        PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,

      parameter        PHY_0_IS_LAST_BANK   = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ?  "FALSE" : "TRUE",

      parameter        PHY_1_IS_LAST_BANK   = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ?  "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),

      parameter        PHY_2_IS_LAST_BANK   = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ?  "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),

      parameter        TCK = 2500,

// local computational use, do not pass down

      parameter        N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])

      +  (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3])  + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])

      ,  // must not delete comma for syntax

      parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 :  (BYTE_LANES_B1 != 0  ? 2 : 1)))),

      parameter HIGHEST_LANE_B0  =   ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0)  ,

      parameter HIGHEST_LANE_B1  = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,

      parameter HIGHEST_LANE_B2  = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,

      parameter HIGHEST_LANE_B3  = 0,

      parameter HIGHEST_LANE_B4  = 0,

      parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8)  : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),

      parameter LP_DDR_CK_WIDTH = 2,

      parameter GENERATE_SIGNAL_SPLIT = "FALSE"

      ,parameter CKE_ODT_AUX = "FALSE"

 )

 (

      input            rst,

      input            ddr_rst_in_n ,

      input            phy_clk,

      input            freq_refclk,

      input            mem_refclk,

      input            mem_refclk_div4,

      input            pll_lock,

      input            sync_pulse,

      input            auxout_clk,

      input            idelayctrl_refclk,

      input [HIGHEST_LANE*80-1:0]    phy_dout,

      input            phy_cmd_wr_en,

      input            phy_data_wr_en,

      input            phy_rd_en,

      input [31:0]     phy_ctl_wd,

      input [3:0]      aux_in_1,

      input [3:0]      aux_in_2,

      input [5:0]      data_offset_1,

      input [5:0]      data_offset_2,

      input            phy_ctl_wr,

      input            if_rst,

      input            if_empty_def,

      input            cke_in,

      input            idelay_ce,

      input            idelay_ld,

      input            idelay_inc,

      input            phyGo,

      input            input_sink,

      output           if_a_empty,

      output           if_empty /* synthesis syn_maxfan = 3 */,

      output           if_empty_or,

      output           if_empty_and,

      output           of_ctl_a_full,

      output           of_data_a_full,

      output           of_ctl_full,

      output           of_data_full,

      output           pre_data_a_full,

      output [HIGHEST_LANE*80-1:0]   phy_din,

      output           phy_ctl_a_full,

      output wire [3:0]      phy_ctl_full,

      output [HIGHEST_LANE*12-1:0] mem_dq_out,

      output [HIGHEST_LANE*12-1:0] mem_dq_ts,

      input  [HIGHEST_LANE*10-1:0] mem_dq_in,

      output [HIGHEST_LANE-1:0]    mem_dqs_out,

      output [HIGHEST_LANE-1:0]    mem_dqs_ts,

      input  [HIGHEST_LANE-1:0]    mem_dqs_in,

(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt ,  4 per phy controller

      output           phy_ctl_ready,          // to fabric

      output reg       rst_out,                // to memory

      output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0]  ddr_clk,

//      output           rclk,

      output           mcGo,

      output           ref_dll_lock,

// calibration signals

      input            phy_write_calib,

      input            phy_read_calib,

      input  [5:0]     calib_sel,

      input  [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank

      input  [HIGHEST_BANK-1:0]calib_zero_ctrl,  // one  bit per bank, zero's only control lane calibration inputs

      input  [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane

      input            calib_in_common,

      input  [2:0]     po_fine_enable,

      input  [2:0]     po_coarse_enable,

      input  [2:0]     po_fine_inc,

      input  [2:0]     po_coarse_inc,

      input            po_counter_load_en,

      input  [2:0]     po_sel_fine_oclk_delay,

      input  [8:0]     po_counter_load_val,

      input            po_counter_read_en,

      output reg       po_coarse_overflow,

      output reg       po_fine_overflow,

      output reg [8:0] po_counter_read_val,

      input [HIGHEST_BANK-1:0] pi_rst_dqs_find,

      input            pi_fine_enable,

      input            pi_fine_inc,

      input            pi_counter_load_en,

      input            pi_counter_read_en,

      input  [5:0]     pi_counter_load_val,

      output reg       pi_fine_overflow,

      output reg [5:0] pi_counter_read_val,

      output reg       pi_phase_locked,

      output           pi_phase_locked_all,

      output reg       pi_dqs_found,

      output           pi_dqs_found_all,

      output           pi_dqs_found_any,

      output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,

      output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,

      output reg       pi_dqs_out_of_range,

      input [29:0]     fine_delay,

      input            fine_delay_sel

 );

wire  [7:0]     calib_zero_inputs_int ;

wire  [HIGHEST_BANK*4-1:0]     calib_zero_lanes_int ;

//Added the temporary variable for concadination operation

wire  [2:0]     calib_sel_byte0 ;

wire  [2:0]     calib_sel_byte1 ;

wire  [2:0]     calib_sel_byte2 ;

wire  [4:0]     po_coarse_overflow_w;

wire  [4:0]     po_fine_overflow_w;

wire  [8:0]     po_counter_read_val_w[4:0];

wire  [4:0]     pi_fine_overflow_w;

wire  [5:0]     pi_counter_read_val_w[4:0];

wire  [4:0]     pi_dqs_found_w;

wire  [4:0]     pi_dqs_found_all_w;

wire  [4:0]     pi_dqs_found_any_w;

wire  [4:0]     pi_dqs_out_of_range_w;

wire  [4:0]     pi_phase_locked_w;

wire  [4:0]     pi_phase_locked_all_w;

wire  [4:0]     rclk_w;

wire  [HIGHEST_BANK-1:0]     phy_ctl_ready_w;

wire  [(LP_DDR_CK_WIDTH*24)-1:0]     ddr_clk_w [HIGHEST_BANK-1:0];

wire  [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;

wire [3:0]    if_q0;

wire [3:0]    if_q1;

wire [3:0]    if_q2;

wire [3:0]    if_q3;

wire [3:0]    if_q4;

wire [7:0]    if_q5;

wire [7:0]    if_q6;

wire [3:0]    if_q7;

wire [3:0]    if_q8;

wire [3:0]    if_q9;

wire [31:0]   _phy_ctl_wd;

wire [3:0]    aux_in_[4:1];

wire [3:0]    rst_out_w;

wire           freq_refclk_split;

wire           mem_refclk_split;

wire           mem_refclk_div4_split;

wire           sync_pulse_split;

wire           phy_clk_split0;

wire           phy_ctl_clk_split0;

wire  [31:0]   phy_ctl_wd_split0;

wire           phy_ctl_wr_split0;

wire           phy_ctl_clk_split1;

wire           phy_clk_split1;

wire  [31:0]   phy_ctl_wd_split1;

wire           phy_ctl_wr_split1;

wire  [5:0]    phy_data_offset_1_split1;

wire           phy_ctl_clk_split2;

wire           phy_clk_split2;

wire  [31:0]   phy_ctl_wd_split2;

wire           phy_ctl_wr_split2;

wire  [5:0]    phy_data_offset_2_split2;

wire  [HIGHEST_LANE*80-1:0] phy_dout_split0;

wire           phy_cmd_wr_en_split0;

wire           phy_data_wr_en_split0;

wire           phy_rd_en_split0;

wire  [HIGHEST_LANE*80-1:0] phy_dout_split1;

wire           phy_cmd_wr_en_split1;

wire           phy_data_wr_en_split1;

wire           phy_rd_en_split1;

wire  [HIGHEST_LANE*80-1:0] phy_dout_split2;

wire           phy_cmd_wr_en_split2;

wire           phy_data_wr_en_split2;

wire           phy_rd_en_split2;

wire          phy_ctl_mstr_empty;

wire  [HIGHEST_BANK-1:0] phy_ctl_empty;

wire          _phy_ctl_a_full_f;

wire          _phy_ctl_a_empty_f;

wire          _phy_ctl_full_f;

wire          _phy_ctl_empty_f;

wire  [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;

wire  [HIGHEST_BANK-1:0] _phy_ctl_full_p;

wire  [HIGHEST_BANK-1:0]  of_ctl_a_full_v;

wire  [HIGHEST_BANK-1:0]  of_ctl_full_v;

wire  [HIGHEST_BANK-1:0]  of_data_a_full_v;

wire  [HIGHEST_BANK-1:0]  of_data_full_v;

wire  [HIGHEST_BANK-1:0]  pre_data_a_full_v;

wire  [HIGHEST_BANK-1:0]  if_empty_v;

wire  [HIGHEST_BANK-1:0]  byte_rd_en_v;

wire  [HIGHEST_BANK*2-1:0]  byte_rd_en_oth_banks;

wire  [HIGHEST_BANK-1:0]  if_empty_or_v;

wire  [HIGHEST_BANK-1:0]  if_empty_and_v;

wire  [HIGHEST_BANK-1:0]  if_a_empty_v;

localparam IF_ARRAY_MODE         = "ARRAY_MODE_4_X_4";

localparam IF_SYNCHRONOUS_MODE   = "FALSE";

localparam IF_SLOW_WR_CLK        = "FALSE";

localparam IF_SLOW_RD_CLK        = "FALSE";

localparam PHY_MULTI_REGION      = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";

localparam RCLK_NEG_EDGE         = 3'b000;

localparam RCLK_POS_EDGE         = 3'b111;

localparam LP_PHY_0_BYTELANES_DDR_CK     =  BYTELANES_DDR_CK & 24'hFF_FFFF;

localparam LP_PHY_1_BYTELANES_DDR_CK     = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;

localparam LP_PHY_2_BYTELANES_DDR_CK     = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;

// hi, lo positions for data offset field, MIG doesn't allow defines

localparam PC_DATA_OFFSET_RANGE_HI    = 22;

localparam PC_DATA_OFFSET_RANGE_LO    = 17;

/* Phaser_In Output source coding table

    "PHASE_REF"         :  4'b0000;

    "DELAYED_MEM_REF"   :  4'b0101;

    "DELAYED_PHASE_REF" :  4'b0011;

    "DELAYED_REF"       :  4'b0001;

    "FREQ_REF"          :  4'b1000;

    "MEM_REF"           :  4'b0010;

*/

localparam  RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";

localparam  DDR_TCK = TCK;

localparam  real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);

localparam  real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;

localparam  PO_S3_TAPS      = 64 ;  // Number of taps per clock cycle in OCLK_DELAYED delay line

localparam  PI_S2_TAPS      = 128 ; // Number of taps per clock cycle in stage 2 delay line

localparam  PO_S2_TAPS      = 128 ; // Number of taps per clock cycle in sta

/*

Intrinsic delay of Phaser In Stage 1

@3300ps - 1.939ns - 58.8%

@2500ps - 1.657ns - 66.3%

@1875ps - 1.263ns - 67.4%

@1500ps - 1.021ns - 68.1%

@1250ps - 0.868ns - 69.4%

@1072ps - 0.752ns - 70.1%

@938ps  - 0.667ns - 71.1%

*/

// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0

// Fraction of a full DDR_TCK period

localparam  real PI_STG1_INTRINSIC_DELAY  =  (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :

                     ((DDR_TCK < 1005) ? 0.667 :

                      (DDR_TCK < 1160) ? 0.752 :

                      (DDR_TCK < 1375) ? 0.868 :

                      (DDR_TCK < 1685) ? 1.021 :

                      (DDR_TCK < 2185) ? 1.263 :

                      (DDR_TCK < 2900) ? 1.657 :

                      (DDR_TCK < 3100) ? 1.771 : 1.939)*1000;

/*

Intrinsic delay of Phaser In Stage 2

@3300ps - 0.912ns - 27.6% - single tap - 13ps

@3000ps - 0.848ns - 28.3% - single tap - 11ps

@2500ps - 1.264ns - 50.6% - single tap - 19ps

@1875ps - 1.000ns - 53.3% - single tap - 15ps

@1500ps - 0.848ns - 56.5% - single tap - 11ps

@1250ps - 0.736ns - 58.9% - single tap - 9ps

@1072ps - 0.664ns - 61.9% - single tap - 8ps

@938ps  - 0.608ns - 64.8% - single tap - 7ps

*/

// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)

localparam  real PI_STG2_INTRINSIC_DELAY  = (0.4218*FREQ_REF_PERIOD + 200) + 16.75;  // 12ps fudge factor

/*

Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1

@3300ps - 1.294ns - 39.2%

@2500ps - 1.294ns - 51.8%

@1875ps - 1.030ns - 54.9%

@1500ps - 0.878ns - 58.5%

@1250ps - 0.766ns - 61.3%

@1072ps - 0.694ns - 64.7%

@938ps  - 0.638ns - 68.0%

Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0

@3300ps - 2.084ns - 63.2% - single tap - 20ps

@2500ps - 2.084ns - 81.9% - single tap - 19ps

@1875ps - 1.676ns - 89.4% - single tap - 15ps

@1500ps - 1.444ns - 96.3% - single tap - 11ps

@1250ps - 1.276ns - 102.1% - single tap - 9ps

@1072ps - 1.164ns - 108.6% - single tap - 8ps

@938ps  - 1.076ns - 114.7% - single tap - 7ps

*/

// Fraction of a full DDR_TCK period

localparam  real  PO_STG1_INTRINSIC_DELAY  = 0;

localparam  real  PO_STG2_FINE_INTRINSIC_DELAY    = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor

localparam  real  PO_STG2_COARSE_INTRINSIC_DELAY  = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor

localparam  real  PO_STG2_INTRINSIC_DELAY  = PO_STG2_FINE_INTRINSIC_DELAY +

                                            (PO_CTL_COARSE_BYPASS  == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);