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//*****************************************************************************
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// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version: %version
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// \ \ Application: MIG
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// / / Filename: ddr_phy_v2_3_phy_ocd_edge.v
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// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
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// \ \ / \ Date Created: Aug 03 2009
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// \___\/\___\
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//
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//Device: 7 Series
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//Design Name: DDR3 SDRAM
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//Purpose: Detects and stores edges as the test pattern is scanned via
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// manipulating the phaser out stage 3 taps.
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//
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// Scanning always proceeds from the left to the right. For more
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// on the scanning algorithm, see the _po_cntlr block.
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//
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// Four scan results are reported. The edges at fuzz2zero,
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// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge
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// has a 6 bit stg3 tap value and a valid bit. The valid bits
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// are reset before the scan starts.
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//
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// Once reset_scan is set low, this block waits for the first
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// samp_done while scanning_right. This marks the left end
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// of the scan, and initializes prev_samp_r with samp_result and
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// sets the prev_samp_r valid bit to one.
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//
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// At each subesquent samp_done, the previous samp is compared
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// to the current samp_result. The case statement details how
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// edges are identified.
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//
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// Original design assumed fuzz between valid regions. Design
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// has been updated to tolerate transitions from zero to oneeight
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// and vice-versa without fuzz in between.
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//
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//Reference:
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//Revision History:
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//*****************************************************************************
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`timescale 1ps/1ps
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module mig_7series_v2_3_ddr_phy_ocd_edge #
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(parameter TCQ = 100)
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(/*AUTOARG*/
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// Outputs
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scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero,
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oneeighty2fuzz, fuzz2oneeighty,
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// Inputs
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clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right,
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samp_result, stg3
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);
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localparam [1:0] NULL = 2'b11,
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FUZZ = 2'b00,
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ONEEIGHTY = 2'b10,
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ZERO = 2'b01;
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input clk;
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input samp_done;
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input phy_rddata_en_2;
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wire samp_valid = samp_done && phy_rddata_en_2;
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input reset_scan;
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input scanning_right;
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reg prev_samp_valid_ns, prev_samp_valid_r;
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always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns;
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always @(*) begin
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prev_samp_valid_ns = prev_samp_valid_r;
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if (reset_scan) prev_samp_valid_ns = 1'b0;
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else if (samp_valid) prev_samp_valid_ns = 1'b1;
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end
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input [1:0] samp_result;
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reg [1:0] prev_samp_ns, prev_samp_r;
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always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns;
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always @(*)
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if (samp_valid) prev_samp_ns = samp_result;
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else prev_samp_ns = prev_samp_r;
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reg scan_right_ns, scan_right_r;
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always @(posedge clk) scan_right_r <= #TCQ scan_right_ns;
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output scan_right;
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assign scan_right = scan_right_r;
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input [5:0] stg3;
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reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r;
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always @(posedge clk) z2f_r <= #TCQ z2f_ns;
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always @(posedge clk) f2z_r <= #TCQ f2z_ns;
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always @(posedge clk) o2f_r <= #TCQ o2f_ns;
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always @(posedge clk) f2o_r <= #TCQ f2o_ns;
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output z2f, f2z, o2f, f2o;
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assign z2f = z2f_r;
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assign f2z = f2z_r;
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assign o2f = o2f_r;
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assign f2o = f2o_r;
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reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r,
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oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r;
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always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns;
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always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns;
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always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns;
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always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns;
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output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
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assign zero2fuzz = zero2fuzz_r;
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assign fuzz2zero = fuzz2zero_r;
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assign oneeighty2fuzz = oneeighty2fuzz_r;
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assign fuzz2oneeighty = fuzz2oneeighty_r;
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always @(*) begin
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z2f_ns = z2f_r;
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f2z_ns = f2z_r;
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o2f_ns = o2f_r;
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f2o_ns = f2o_r;
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zero2fuzz_ns = zero2fuzz_r;
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fuzz2zero_ns = fuzz2zero_r;
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oneeighty2fuzz_ns = oneeighty2fuzz_r;
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fuzz2oneeighty_ns = fuzz2oneeighty_r;
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scan_right_ns = 1'b0;
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if (reset_scan) begin
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z2f_ns = 1'b0;
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f2z_ns = 1'b0;
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o2f_ns = 1'b0;
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f2o_ns = 1'b0;
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end
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else if (samp_valid && prev_samp_valid_r)
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case (prev_samp_r)
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FUZZ :
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if (scanning_right) begin
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if (samp_result == ZERO) begin
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fuzz2zero_ns = stg3;
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f2z_ns = 1'b1;
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end
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if (samp_result == ONEEIGHTY) begin
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fuzz2oneeighty_ns = stg3;
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f2o_ns = 1'b1;
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end
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end
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ZERO : begin
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if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right;
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if (scanning_right) begin
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if (samp_result == FUZZ) begin
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zero2fuzz_ns = stg3 - 6'b1;
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z2f_ns = 1'b1;
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end
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if (samp_result == ONEEIGHTY) begin
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zero2fuzz_ns = stg3 - 6'b1;
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z2f_ns = 1'b1;
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fuzz2oneeighty_ns = stg3;
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f2o_ns = 1'b1;
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end
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end
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end
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ONEEIGHTY :
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if (scanning_right) begin
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if (samp_result == FUZZ) begin
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oneeighty2fuzz_ns = stg3 - 6'b1;
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o2f_ns = 1'b1;
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end
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if (samp_result == ZERO)
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if (f2o_r) begin
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oneeighty2fuzz_ns = stg3 - 6'b1;
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o2f_ns = 1'b1;
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end else begin
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fuzz2zero_ns = stg3;
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f2z_ns = 1'b1;
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end
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end // if (scanning_right)
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// NULL : // Should never happen
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endcase
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end
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endmodule // mig_7series_v2_3_ddr_phy_ocd_edge
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