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[/] [usb_fpga_2_14/] [trunk/] [examples/] [memfifo/] [fpga-2.14/] [memfifo.srcs/] [sources_1/] [ip/] [mig_7series_0/] [mig_7series_0/] [user_design/] [rtl/] [phy/] [mig_7series_v2_3_ddr_phy_rdlvl.v] - Blame information for rev 2

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//*****************************************************************************
2 
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
3 
//
4 
// This file contains confidential and proprietary information
5 
// of Xilinx, Inc. and is protected under U.S. and
6 
// international copyright and other intellectual property
7 
// laws.
8 
//
9 
// DISCLAIMER
10 
// This disclaimer is not a license and does not grant any
11 
// rights to the materials distributed herewith. Except as
12 
// otherwise provided in a valid license issued to you by
13 
// Xilinx, and to the maximum extent permitted by applicable
14 
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
15 
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
16 
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
17 
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
18 
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
19 
// (2) Xilinx shall not be liable (whether in contract or tort,
20 
// including negligence, or under any other theory of
21 
// liability) for any loss or damage of any kind or nature
22 
// related to, arising under or in connection with these
23 
// materials, including for any direct, or any indirect,
24 
// special, incidental, or consequential loss or damage
25 
// (including loss of data, profits, goodwill, or any type of
26 
// loss or damage suffered as a result of any action brought
27 
// by a third party) even if such damage or loss was
28 
// reasonably foreseeable or Xilinx had been advised of the
29 
// possibility of the same.
30 
//
31 
// CRITICAL APPLICATIONS
32 
// Xilinx products are not designed or intended to be fail-
33 
// safe, or for use in any application requiring fail-safe
34 
// performance, such as life-support or safety devices or
35 
// systems, Class III medical devices, nuclear facilities,
36 
// applications related to the deployment of airbags, or any
37 
// other applications that could lead to death, personal
38 
// injury, or severe property or environmental damage
39 
// (individually and collectively, "Critical
40 
// Applications"). Customer assumes the sole risk and
41 
// liability of any use of Xilinx products in Critical
42 
// Applications, subject only to applicable laws and
43 
// regulations governing limitations on product liability.
44 
//
45 
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
46 
// PART OF THIS FILE AT ALL TIMES.
47 
//
48 
//*****************************************************************************
49 
//   ____  ____
50 
//  /   /\/   /
51 
// /___/  \  /    Vendor: Xilinx
52 
// \   \   \/     Version:
53 
//  \   \         Application: MIG
54 
//  /   /         Filename: ddr_phy_rdlvl.v
55 
// /___/   /\     Date Last Modified: $Date: 2011/06/24 14:49:00 $
56 
// \   \  /  \    Date Created:
57 
//  \___\/\___\
58 
//
59 
//Device: 7 Series
60 
//Design Name: DDR3 SDRAM
61 
//Purpose:
62 
//  Read leveling Stage1 calibration logic
63 
//  NOTES:
64 
//    1. Window detection with PRBS pattern.
65 
//Reference:
66 
//Revision History:
67 
//*****************************************************************************
68 
 
69 
/******************************************************************************
70 
**$Id: ddr_phy_rdlvl.v,v 1.2 2011/06/24 14:49:00 mgeorge Exp $
71 
**$Date: 2011/06/24 14:49:00 $
72 
**$Author: mgeorge $
73 
**$Revision: 1.2 $
74 
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_rdlvl.v,v $
75 
******************************************************************************/
76 
 
77 
`timescale 1ps/1ps
78 
 
79 
(* use_dsp48 = "no" *)
80 
 
81 
module mig_7series_v2_3_ddr_phy_rdlvl #
82 
  (
83 
   parameter TCQ             = 100,    // clk->out delay (sim only)
84 
   parameter nCK_PER_CLK     = 2,      // # of memory clocks per CLK
85 
   parameter CLK_PERIOD      = 3333,   // Internal clock period (in ps)
86 
   parameter DQ_WIDTH        = 64,     // # of DQ (data)
87 
   parameter DQS_CNT_WIDTH   = 3,      // = ceil(log2(DQS_WIDTH))
88 
   parameter DQS_WIDTH       = 8,      // # of DQS (strobe)
89 
   parameter DRAM_WIDTH      = 8,      // # of DQ per DQS
90 
   parameter RANKS           = 1,      // # of DRAM ranks
91 
   parameter PER_BIT_DESKEW  = "ON",   // Enable per-bit DQ deskew
92 
   parameter SIM_CAL_OPTION  = "NONE", // Skip various calibration steps
93 
   parameter DEBUG_PORT      = "OFF",  // Enable debug port
94 
   parameter DRAM_TYPE       = "DDR3",  // Memory I/F type: "DDR3", "DDR2"
95 
   parameter OCAL_EN         = "ON",
96 
   parameter IDELAY_ADJ   = "ON"
97 
   )
98 
  (
99 
   input                        clk,
100 
   input                        rst,
101 
   // Calibration status, control signals
102 
   input                        mpr_rdlvl_start,
103 
   output                       mpr_rdlvl_done,
104 
   output reg                   mpr_last_byte_done,
105 
   output                       mpr_rnk_done,
106 
   input                        rdlvl_stg1_start,
107 
   output reg                   rdlvl_stg1_done /* synthesis syn_maxfan = 30 */,
108 
   output                       rdlvl_stg1_rnk_done,
109 
   output reg                   rdlvl_stg1_err,
110 
   output                       mpr_rdlvl_err,
111 
   output                       rdlvl_err,
112 
   output reg                   rdlvl_prech_req,
113 
   output reg                   rdlvl_last_byte_done,
114 
   output reg                   rdlvl_assrt_common,
115 
   input                        prech_done,
116 
   input                        phy_if_empty,
117 
   input [4:0]                  idelaye2_init_val,
118 
   // Captured data in fabric clock domain
119 
   input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
120 
   // Decrement initial Phaser_IN Fine tap delay
121 
   input                        dqs_po_dec_done,
122 
   input [5:0]                  pi_counter_read_val,
123 
   // Stage 1 calibration outputs
124 
   output reg                   pi_fine_dly_dec_done,
125 
   output reg                   pi_en_stg2_f,
126 
   output reg                   pi_stg2_f_incdec,
127 
   output reg                   pi_stg2_load,
128 
   output reg [5:0]             pi_stg2_reg_l,
129 
   output [DQS_CNT_WIDTH:0]     pi_stg2_rdlvl_cnt,
130 
   // To DQ IDELAY required to find left edge of
131 
   // valid window
132 
   output                       idelay_ce,
133 
   output                       idelay_inc,
134 
   input                        idelay_ld,
135 
   input [DQS_CNT_WIDTH:0]      wrcal_cnt,
136 
   // Only output if Per-bit de-skew enabled
137 
   output reg [5*RANKS*DQ_WIDTH-1:0] dlyval_dq,
138 
   // Debug Port
139 
   output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
140 
   output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
141 
   output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
142 
   output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
143 
 
144 
   input                        dbg_idel_up_all,
145 
   input                        dbg_idel_down_all,
146 
   input                        dbg_idel_up_cpt,
147 
   input                        dbg_idel_down_cpt,
148 
   input [DQS_CNT_WIDTH-1:0]    dbg_sel_idel_cpt,
149 
   input                        dbg_sel_all_idel_cpt,
150 
   output [255:0]               dbg_phy_rdlvl
151 
   );
152 
 
153 
  // minimum time (in IDELAY taps) for which capture data must be stable for
154 
  // algorithm to consider a valid data eye to be found. The read leveling
155 
  // logic will ignore any window found smaller than this value. Limitations
156 
  // on how small this number can be is determined by: (1) the algorithmic
157 
  // limitation of how many taps wide the data eye can be (3 taps), and (2)
158 
  // how wide regions of "instability" that occur around the edges of the
159 
  // read valid window can be (i.e. need to be able to filter out "false"
160 
  // windows that occur for a short # of taps around the edges of the true
161 
  // data window, although with multi-sampling during read leveling, this is
162 
  // not as much a concern) - the larger the value, the more protection
163 
  // against "false" windows
164 
  localparam MIN_EYE_SIZE = 16;
165 
 
166 
  // Length of calibration sequence (in # of words)
167 
  localparam CAL_PAT_LEN = 8;
168 
  // Read data shift register length
169 
  localparam RD_SHIFT_LEN = CAL_PAT_LEN / (2*nCK_PER_CLK);
170 
 
171 
  // # of cycles required to perform read data shift register compare
172 
  // This is defined as from the cycle the new data is loaded until
173 
  // signal found_edge_r is valid
174 
  localparam RD_SHIFT_COMP_DELAY = 5;
175 
 
176 
  // worst-case # of cycles to wait to ensure that both the SR and
177 
  // PREV_SR shift registers have valid data, and that the comparison
178 
  // of the two shift register values is valid. The "+1" at the end of
179 
  // this equation is a fudge factor, I freely admit that
180 
  localparam SR_VALID_DELAY = (2 * RD_SHIFT_LEN) + RD_SHIFT_COMP_DELAY + 1;
181 
 
182 
  // # of clock cycles to wait after changing tap value or read data MUX
183 
  // to allow: (1) tap chain to settle, (2) for delayed input to propagate
184 
  // thru ISERDES, (3) for the read data comparison logic to have time to
185 
  // output the comparison of two consecutive samples of the settled read data
186 
  // The minimum delay is 16 cycles, which should be good enough to handle all
187 
  // three of the above conditions for the simulation-only case with a short
188 
  // training pattern. For H/W (or for simulation with longer training
189 
  // pattern), it will take longer to store and compare two consecutive
190 
  // samples, and the value of this parameter will reflect that
191 
  localparam PIPE_WAIT_CNT = (SR_VALID_DELAY < 8) ? 16 : (SR_VALID_DELAY + 8);
192 
 
193 
  // # of read data samples to examine when detecting whether an edge has
194 
  // occured during stage 1 calibration. Width of local param must be
195 
  // changed as appropriate. Note that there are two counters used, each
196 
  // counter can be changed independently of the other - they are used in
197 
  // cascade to create a larger counter
198 
  localparam [11:0] DETECT_EDGE_SAMPLE_CNT0 = 12'h001; //12'hFFF;
199 
  localparam [11:0] DETECT_EDGE_SAMPLE_CNT1 = 12'h001;   // 12'h1FF Must be > 0
200 
 
201 
  localparam [5:0] CAL1_IDLE                 = 6'h00;
202 
  localparam [5:0] CAL1_NEW_DQS_WAIT         = 6'h01;
203 
  localparam [5:0] CAL1_STORE_FIRST_WAIT     = 6'h02;
204 
  localparam [5:0] CAL1_PAT_DETECT           = 6'h03;
205 
  localparam [5:0] CAL1_DQ_IDEL_TAP_INC      = 6'h04;
206 
  localparam [5:0] CAL1_DQ_IDEL_TAP_INC_WAIT = 6'h05;
207 
  localparam [5:0] CAL1_DQ_IDEL_TAP_DEC      = 6'h06;
208 
  localparam [5:0] CAL1_DQ_IDEL_TAP_DEC_WAIT = 6'h07;
209 
  localparam [5:0] CAL1_DETECT_EDGE          = 6'h08;
210 
  localparam [5:0] CAL1_IDEL_INC_CPT         = 6'h09;
211 
  localparam [5:0] CAL1_IDEL_INC_CPT_WAIT    = 6'h0A;
212 
  localparam [5:0] CAL1_CALC_IDEL            = 6'h0B;
213 
  localparam [5:0] CAL1_IDEL_DEC_CPT         = 6'h0C;
214 
  localparam [5:0] CAL1_IDEL_DEC_CPT_WAIT    = 6'h0D;
215 
  localparam [5:0] CAL1_NEXT_DQS             = 6'h0E;
216 
  localparam [5:0] CAL1_DONE                 = 6'h0F;
217 
  localparam [5:0] CAL1_PB_STORE_FIRST_WAIT  = 6'h10;
218 
  localparam [5:0] CAL1_PB_DETECT_EDGE       = 6'h11;
219 
  localparam [5:0] CAL1_PB_INC_CPT           = 6'h12;
220 
  localparam [5:0] CAL1_PB_INC_CPT_WAIT      = 6'h13;
221 
  localparam [5:0] CAL1_PB_DEC_CPT_LEFT      = 6'h14;
222 
  localparam [5:0] CAL1_PB_DEC_CPT_LEFT_WAIT = 6'h15;
223 
  localparam [5:0] CAL1_PB_DETECT_EDGE_DQ    = 6'h16;
224 
  localparam [5:0] CAL1_PB_INC_DQ            = 6'h17;
225 
  localparam [5:0] CAL1_PB_INC_DQ_WAIT       = 6'h18;
226 
  localparam [5:0] CAL1_PB_DEC_CPT           = 6'h19;
227 
  localparam [5:0] CAL1_PB_DEC_CPT_WAIT      = 6'h1A;
228 
  localparam [5:0] CAL1_REGL_LOAD            = 6'h1B;
229 
  localparam [5:0] CAL1_RDLVL_ERR            = 6'h1C;
230 
  localparam [5:0] CAL1_MPR_NEW_DQS_WAIT     = 6'h1D;
231 
  localparam [5:0] CAL1_VALID_WAIT           = 6'h1E;
232 
  localparam [5:0] CAL1_MPR_PAT_DETECT       = 6'h1F;
233 
  localparam [5:0] CAL1_NEW_DQS_PREWAIT      = 6'h20;
234 
 
235 
  integer    a;
236 
  integer    b;
237 
  integer    d;
238 
  integer    e;
239 
  integer    f;
240 
  integer    h;
241 
  integer    g;
242 
  integer    i;
243 
  integer    j;
244 
  integer    k;
245 
  integer    l;
246 
  integer    m;
247 
  integer    n;
248 
  integer    r;
249 
  integer    p;
250 
  integer    q;
251 
  integer    s;
252 
  integer    t;
253 
  integer    u;
254 
  integer    w;
255 
  integer    ce_i;
256 
  integer    ce_rnk_i;
257 
  integer    aa;
258 
  integer    bb;
259 
  integer    cc;
260 
  integer    dd;
261 
  genvar     x;
262 
  genvar     z;
263 
 
264 
  reg [DQS_CNT_WIDTH:0]   cal1_cnt_cpt_r;
265 
  wire [DQS_CNT_WIDTH+2:0]cal1_cnt_cpt_timing;
266 
  reg [DQS_CNT_WIDTH:0]   cal1_cnt_cpt_timing_r;
267 
  reg                     cal1_dq_idel_ce;
268 
  reg                     cal1_dq_idel_inc;
269 
  reg                     cal1_dlyce_cpt_r;
270 
  reg                     cal1_dlyinc_cpt_r;
271 
  reg                     cal1_dlyce_dq_r;
272 
  reg                     cal1_dlyinc_dq_r;
273 
  reg                     cal1_wait_cnt_en_r;
274 
  reg [4:0]               cal1_wait_cnt_r;
275 
  reg                     cal1_wait_r;
276 
  reg [DQ_WIDTH-1:0]      dlyce_dq_r;
277 
  reg                     dlyinc_dq_r;
278 
  reg [4:0]               dlyval_dq_reg_r [0:RANKS-1][0:DQ_WIDTH-1];
279 
  reg                     cal1_prech_req_r;
280 
  reg [5:0]               cal1_state_r;
281 
  reg [5:0]               cal1_state_r1;
282 
  reg [5:0]               cnt_idel_dec_cpt_r;
283 
  reg [3:0]               cnt_shift_r;
284 
  reg                     detect_edge_done_r;
285 
  reg [5:0]               right_edge_taps_r;
286 
  reg [5:0]               first_edge_taps_r;
287 
  reg                     found_edge_r;
288 
  reg                     found_first_edge_r;
289 
  reg                     found_second_edge_r;
290 
  reg                     found_stable_eye_r;
291 
  reg                     found_stable_eye_last_r;
292 
  reg                     found_edge_all_r;
293 
  reg [5:0]               tap_cnt_cpt_r;
294 
  reg                     tap_limit_cpt_r;
295 
  reg [4:0]               idel_tap_cnt_dq_pb_r;
296 
  reg                     idel_tap_limit_dq_pb_r;
297 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall0_r;
298 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall1_r;
299 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise0_r;
300 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise1_r;
301 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall2_r;
302 
  reg [DRAM_WIDTH-1:0]    mux_rd_fall3_r;
303 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise2_r;
304 
  reg [DRAM_WIDTH-1:0]    mux_rd_rise3_r;
305 
  reg                     mux_rd_valid_r;
306 
  reg                     new_cnt_cpt_r;
307 
  reg [RD_SHIFT_LEN-1:0]  old_sr_fall0_r [DRAM_WIDTH-1:0];
308 
  reg [RD_SHIFT_LEN-1:0]  old_sr_fall1_r [DRAM_WIDTH-1:0];
309 
  reg [RD_SHIFT_LEN-1:0]  old_sr_rise0_r [DRAM_WIDTH-1:0];
310 
  reg [RD_SHIFT_LEN-1:0]  old_sr_rise1_r [DRAM_WIDTH-1:0];
311 
  reg [RD_SHIFT_LEN-1:0]  old_sr_fall2_r [DRAM_WIDTH-1:0];
312 
  reg [RD_SHIFT_LEN-1:0]  old_sr_fall3_r [DRAM_WIDTH-1:0];
313 
  reg [RD_SHIFT_LEN-1:0]  old_sr_rise2_r [DRAM_WIDTH-1:0];
314 
  reg [RD_SHIFT_LEN-1:0]  old_sr_rise3_r [DRAM_WIDTH-1:0];
315 
  reg [DRAM_WIDTH-1:0]    old_sr_match_fall0_r;
316 
  reg [DRAM_WIDTH-1:0]    old_sr_match_fall1_r;
317 
  reg [DRAM_WIDTH-1:0]    old_sr_match_rise0_r;
318 
  reg [DRAM_WIDTH-1:0]    old_sr_match_rise1_r;
319 
  reg [DRAM_WIDTH-1:0]    old_sr_match_fall2_r;
320 
  reg [DRAM_WIDTH-1:0]    old_sr_match_fall3_r;
321 
  reg [DRAM_WIDTH-1:0]    old_sr_match_rise2_r;
322 
  reg [DRAM_WIDTH-1:0]    old_sr_match_rise3_r;
323 
  reg [4:0]               pb_cnt_eye_size_r [DRAM_WIDTH-1:0];
324 
  reg [DRAM_WIDTH-1:0]    pb_detect_edge_done_r;
325 
  reg [DRAM_WIDTH-1:0]    pb_found_edge_last_r;
326 
  reg [DRAM_WIDTH-1:0]    pb_found_edge_r;
327 
  reg [DRAM_WIDTH-1:0]    pb_found_first_edge_r;
328 
  reg [DRAM_WIDTH-1:0]    pb_found_stable_eye_r;
329 
  reg [DRAM_WIDTH-1:0]    pb_last_tap_jitter_r;
330 
  reg                     pi_en_stg2_f_timing;
331 
  reg                     pi_stg2_f_incdec_timing;
332 
  reg                     pi_stg2_load_timing;
333 
  reg [5:0]                pi_stg2_reg_l_timing;
334 
  reg [DRAM_WIDTH-1:0]    prev_sr_diff_r;
335 
  reg [RD_SHIFT_LEN-1:0]  prev_sr_fall0_r [DRAM_WIDTH-1:0];
336 
  reg [RD_SHIFT_LEN-1:0]  prev_sr_fall1_r [DRAM_WIDTH-1:0];
337 
  reg [RD_SHIFT_LEN-1:0]  prev_sr_rise0_r [DRAM_WIDTH-1:0];
338 
  reg [RD_SHIFT_LEN-1:0]  prev_sr_rise1_r [DRAM_WIDTH-1:0];
339 
  reg [RD_SHIFT_LEN-1:0]  prev_sr_fall2_r [DRAM_WIDTH-1:0];
340 
  reg [RD_SHIFT_LEN-1:0]  prev_sr_fall3_r [DRAM_WIDTH-1:0];
341 
  reg [RD_SHIFT_LEN-1:0]  prev_sr_rise2_r [DRAM_WIDTH-1:0];
342 
  reg [RD_SHIFT_LEN-1:0]  prev_sr_rise3_r [DRAM_WIDTH-1:0];
343 
  reg [DRAM_WIDTH-1:0]    prev_sr_match_cyc2_r;
344 
  reg [DRAM_WIDTH-1:0]    prev_sr_match_fall0_r;
345 
  reg [DRAM_WIDTH-1:0]    prev_sr_match_fall1_r;
346 
  reg [DRAM_WIDTH-1:0]    prev_sr_match_rise0_r;
347 
  reg [DRAM_WIDTH-1:0]    prev_sr_match_rise1_r;
348 
  reg [DRAM_WIDTH-1:0]    prev_sr_match_fall2_r;
349 
  reg [DRAM_WIDTH-1:0]    prev_sr_match_fall3_r;
350 
  reg [DRAM_WIDTH-1:0]    prev_sr_match_rise2_r;
351 
  reg [DRAM_WIDTH-1:0]    prev_sr_match_rise3_r;
352 
  wire [DQ_WIDTH-1:0]     rd_data_rise0;
353 
  wire [DQ_WIDTH-1:0]     rd_data_fall0;
354 
  wire [DQ_WIDTH-1:0]     rd_data_rise1;
355 
  wire [DQ_WIDTH-1:0]     rd_data_fall1;
356 
  wire [DQ_WIDTH-1:0]     rd_data_rise2;
357 
  wire [DQ_WIDTH-1:0]     rd_data_fall2;
358 
  wire [DQ_WIDTH-1:0]     rd_data_rise3;
359 
  wire [DQ_WIDTH-1:0]     rd_data_fall3;
360 
  reg                     samp_cnt_done_r;
361 
  reg                     samp_edge_cnt0_en_r;
362 
  reg [11:0]              samp_edge_cnt0_r;
363 
  reg                     samp_edge_cnt1_en_r;
364 
  reg [11:0]              samp_edge_cnt1_r;
365 
  reg [DQS_CNT_WIDTH:0]   rd_mux_sel_r;
366 
  reg [5:0]               second_edge_taps_r;
367 
  reg [RD_SHIFT_LEN-1:0]  sr_fall0_r [DRAM_WIDTH-1:0];
368 
  reg [RD_SHIFT_LEN-1:0]  sr_fall1_r [DRAM_WIDTH-1:0];
369 
  reg [RD_SHIFT_LEN-1:0]  sr_rise0_r [DRAM_WIDTH-1:0];
370 
  reg [RD_SHIFT_LEN-1:0]  sr_rise1_r [DRAM_WIDTH-1:0];
371 
  reg [RD_SHIFT_LEN-1:0]  sr_fall2_r [DRAM_WIDTH-1:0];
372 
  reg [RD_SHIFT_LEN-1:0]  sr_fall3_r [DRAM_WIDTH-1:0];
373 
  reg [RD_SHIFT_LEN-1:0]  sr_rise2_r [DRAM_WIDTH-1:0];
374 
  reg [RD_SHIFT_LEN-1:0]  sr_rise3_r [DRAM_WIDTH-1:0];
375 
  reg                     store_sr_r;
376 
  reg                     store_sr_req_pulsed_r;
377 
  reg                     store_sr_req_r;
378 
  reg                     sr_valid_r;
379 
  reg                     sr_valid_r1;
380 
  reg                     sr_valid_r2;
381 
  reg [DRAM_WIDTH-1:0]    old_sr_diff_r;
382 
  reg [DRAM_WIDTH-1:0]    old_sr_match_cyc2_r;
383 
  reg                     pat0_data_match_r;
384 
  reg                     pat1_data_match_r;
385 
  wire                    pat_data_match_r;
386 
  wire [RD_SHIFT_LEN-1:0] pat0_fall0 [3:0];
387 
  wire [RD_SHIFT_LEN-1:0] pat0_fall1 [3:0];
388 
  wire [RD_SHIFT_LEN-1:0] pat0_fall2 [3:0];
389 
  wire [RD_SHIFT_LEN-1:0] pat0_fall3 [3:0];
390 
  wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];
391 
  wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];
392 
  wire [RD_SHIFT_LEN-1:0] pat1_fall2 [3:0];
393 
  wire [RD_SHIFT_LEN-1:0] pat1_fall3 [3:0];
394 
  reg [DRAM_WIDTH-1:0]    pat0_match_fall0_r;
395 
  reg                     pat0_match_fall0_and_r;
396 
  reg [DRAM_WIDTH-1:0]    pat0_match_fall1_r;
397 
  reg                     pat0_match_fall1_and_r;
398 
  reg [DRAM_WIDTH-1:0]    pat0_match_fall2_r;
399 
  reg                     pat0_match_fall2_and_r;
400 
  reg [DRAM_WIDTH-1:0]    pat0_match_fall3_r;
401 
  reg                     pat0_match_fall3_and_r;
402 
  reg [DRAM_WIDTH-1:0]    pat0_match_rise0_r;
403 
  reg                     pat0_match_rise0_and_r;
404 
  reg [DRAM_WIDTH-1:0]    pat0_match_rise1_r;
405 
  reg                     pat0_match_rise1_and_r;
406 
  reg [DRAM_WIDTH-1:0]    pat0_match_rise2_r;
407 
  reg                     pat0_match_rise2_and_r;
408 
  reg [DRAM_WIDTH-1:0]    pat0_match_rise3_r;
409 
  reg                     pat0_match_rise3_and_r;
410 
  reg [DRAM_WIDTH-1:0]    pat1_match_fall0_r;
411 
  reg                     pat1_match_fall0_and_r;
412 
  reg [DRAM_WIDTH-1:0]    pat1_match_fall1_r;
413 
  reg                     pat1_match_fall1_and_r;
414 
  reg [DRAM_WIDTH-1:0]    pat1_match_fall2_r;
415 
  reg                     pat1_match_fall2_and_r;
416 
  reg [DRAM_WIDTH-1:0]    pat1_match_fall3_r;
417 
  reg                     pat1_match_fall3_and_r;
418 
  reg [DRAM_WIDTH-1:0]    pat1_match_rise0_r;
419 
  reg                     pat1_match_rise0_and_r;
420 
  reg [DRAM_WIDTH-1:0]    pat1_match_rise1_r;
421 
  reg                     pat1_match_rise1_and_r;
422 
  reg [DRAM_WIDTH-1:0]    pat1_match_rise2_r;
423 
  reg                     pat1_match_rise2_and_r;
424 
  reg [DRAM_WIDTH-1:0]    pat1_match_rise3_r;
425 
  reg                     pat1_match_rise3_and_r;
426 
  reg [4:0]               idelay_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1];
427 
  reg [5*DQS_WIDTH*RANKS-1:0] idelay_tap_cnt_w;
428 
  reg [4:0]               idelay_tap_cnt_slice_r;
429 
  reg                     idelay_tap_limit_r;
430 
 
431 
  wire [RD_SHIFT_LEN-1:0] pat0_rise0 [3:0];
432 
  wire [RD_SHIFT_LEN-1:0] pat0_rise1 [3:0];
433 
  wire [RD_SHIFT_LEN-1:0] pat0_rise2 [3:0];
434 
  wire [RD_SHIFT_LEN-1:0] pat0_rise3 [3:0];
435 
  wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];
436 
  wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];
437 
  wire [RD_SHIFT_LEN-1:0] pat1_rise2 [3:0];
438 
  wire [RD_SHIFT_LEN-1:0] pat1_rise3 [3:0];
439 
 
440 
  wire [RD_SHIFT_LEN-1:0] idel_pat0_rise0 [3:0];
441 
  wire [RD_SHIFT_LEN-1:0] idel_pat0_fall0 [3:0];
442 
  wire [RD_SHIFT_LEN-1:0] idel_pat0_rise1 [3:0];
443 
  wire [RD_SHIFT_LEN-1:0] idel_pat0_fall1 [3:0];
444 
  wire [RD_SHIFT_LEN-1:0] idel_pat0_rise2 [3:0];
445 
  wire [RD_SHIFT_LEN-1:0] idel_pat0_fall2 [3:0];
446 
  wire [RD_SHIFT_LEN-1:0] idel_pat0_rise3 [3:0];
447 
  wire [RD_SHIFT_LEN-1:0] idel_pat0_fall3 [3:0];
448 
  wire [RD_SHIFT_LEN-1:0] idel_pat1_rise0 [3:0];
449 
  wire [RD_SHIFT_LEN-1:0] idel_pat1_fall0 [3:0];
450 
  wire [RD_SHIFT_LEN-1:0] idel_pat1_rise1 [3:0];
451 
  wire [RD_SHIFT_LEN-1:0] idel_pat1_fall1 [3:0];
452 
  wire [RD_SHIFT_LEN-1:0] idel_pat1_rise2 [3:0];
453 
  wire [RD_SHIFT_LEN-1:0] idel_pat1_fall2 [3:0];
454 
  wire [RD_SHIFT_LEN-1:0] idel_pat1_rise3 [3:0];
455 
  wire [RD_SHIFT_LEN-1:0] idel_pat1_fall3 [3:0];
456 
 
457 
  reg [DRAM_WIDTH-1:0]    idel_pat0_match_rise0_r;
458 
  reg [DRAM_WIDTH-1:0]    idel_pat0_match_fall0_r;
459 
  reg [DRAM_WIDTH-1:0]    idel_pat0_match_rise1_r;
460 
  reg [DRAM_WIDTH-1:0]    idel_pat0_match_fall1_r;
461 
  reg [DRAM_WIDTH-1:0]    idel_pat0_match_rise2_r;
462 
  reg [DRAM_WIDTH-1:0]    idel_pat0_match_fall2_r;
463 
  reg [DRAM_WIDTH-1:0]    idel_pat0_match_rise3_r;
464 
  reg [DRAM_WIDTH-1:0]    idel_pat0_match_fall3_r;
465 
 
466 
  reg [DRAM_WIDTH-1:0]    idel_pat1_match_rise0_r;
467 
  reg [DRAM_WIDTH-1:0]    idel_pat1_match_fall0_r;
468 
  reg [DRAM_WIDTH-1:0]    idel_pat1_match_rise1_r;
469 
  reg [DRAM_WIDTH-1:0]    idel_pat1_match_fall1_r;
470 
  reg [DRAM_WIDTH-1:0]    idel_pat1_match_rise2_r;
471 
  reg [DRAM_WIDTH-1:0]    idel_pat1_match_fall2_r;
472 
  reg [DRAM_WIDTH-1:0]    idel_pat1_match_rise3_r;
473 
  reg [DRAM_WIDTH-1:0]    idel_pat1_match_fall3_r;
474 
 
475 
  reg                     idel_pat0_match_rise0_and_r;
476 
  reg                     idel_pat0_match_fall0_and_r;
477 
  reg                     idel_pat0_match_rise1_and_r;
478 
  reg                     idel_pat0_match_fall1_and_r;
479 
  reg                     idel_pat0_match_rise2_and_r;
480 
  reg                     idel_pat0_match_fall2_and_r;
481 
  reg                     idel_pat0_match_rise3_and_r;
482 
  reg                     idel_pat0_match_fall3_and_r;
483 
 
484 
  reg                     idel_pat1_match_rise0_and_r;
485 
  reg                     idel_pat1_match_fall0_and_r;
486 
  reg                     idel_pat1_match_rise1_and_r;
487 
  reg                     idel_pat1_match_fall1_and_r;
488 
  reg                     idel_pat1_match_rise2_and_r;
489 
  reg                     idel_pat1_match_fall2_and_r;
490 
  reg                     idel_pat1_match_rise3_and_r;
491 
  reg                     idel_pat1_match_fall3_and_r;
492 
 
493 
  reg                     idel_pat0_data_match_r;
494 
  reg                     idel_pat1_data_match_r;
495 
 
496 
  reg                     idel_pat_data_match;
497 
  reg                     idel_pat_data_match_r;
498 
 
499 
  reg [4:0]               idel_dec_cnt;
500 
 
501 
  reg [5:0]               rdlvl_dqs_tap_cnt_r [0:RANKS-1][0:DQS_WIDTH-1];
502 
  reg [1:0]               rnk_cnt_r;
503 
  reg                     rdlvl_rank_done_r;
504 
 
505 
  reg [3:0]               done_cnt;
506 
  reg [1:0]               regl_rank_cnt;
507 
  reg [DQS_CNT_WIDTH:0]   regl_dqs_cnt;
508 
  reg [DQS_CNT_WIDTH:0]   regl_dqs_cnt_r;
509 
  wire [DQS_CNT_WIDTH+2:0]regl_dqs_cnt_timing;
510 
  reg                     regl_rank_done_r;
511 
  reg                     rdlvl_stg1_start_r;
512 
 
513 
  reg                     dqs_po_dec_done_r1;
514 
  reg                     dqs_po_dec_done_r2;
515 
  reg                     fine_dly_dec_done_r1;
516 
  reg                     fine_dly_dec_done_r2;
517 
  reg [3:0]               wait_cnt_r;
518 
  reg [5:0]               pi_rdval_cnt;
519 
  reg                     pi_cnt_dec;
520 
 
521 
  reg                     mpr_valid_r;
522 
  reg                     mpr_valid_r1;
523 
  reg                     mpr_valid_r2;
524 
  reg                     mpr_rd_rise0_prev_r;
525 
  reg                     mpr_rd_fall0_prev_r;
526 
  reg                     mpr_rd_rise1_prev_r;
527 
  reg                     mpr_rd_fall1_prev_r;
528 
  reg                     mpr_rd_rise2_prev_r;
529 
  reg                     mpr_rd_fall2_prev_r;
530 
  reg                     mpr_rd_rise3_prev_r;
531 
  reg                     mpr_rd_fall3_prev_r;
532 
  reg                     mpr_rdlvl_done_r;
533 
  reg                     mpr_rdlvl_done_r1;
534 
  reg                     mpr_rdlvl_done_r2;
535 
  reg                     mpr_rdlvl_start_r;
536 
  reg                     mpr_rank_done_r;
537 
  reg [2:0]               stable_idel_cnt;
538 
  reg                     inhibit_edge_detect_r;
539 
  reg                     idel_pat_detect_valid_r;
540 
  reg                     idel_mpr_pat_detect_r;
541 
  reg                     mpr_pat_detect_r;
542 
  reg                     mpr_dec_cpt_r;
543 
  reg                     idel_adj_inc;   //IDELAY adjustment
544 
  wire [1:0]              idelay_adj;
545 
  wire                    pb_detect_edge_setup;
546 
  wire                    pb_detect_edge;
547 
  // Debug
548 
  reg [6*DQS_WIDTH-1:0] dbg_cpt_first_edge_taps;
549 
  reg [6*DQS_WIDTH-1:0] dbg_cpt_second_edge_taps;
550 
  reg [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt_w;
551 
 
552 
  //IDELAY adjustment setting for -1
553 
  //2'b10 : IDELAY - 1
554 
  //2'b01 : IDELAY + 1
555 
  //2'b00 : No IDELAY adjustment
556 
  assign idelay_adj = (IDELAY_ADJ == "ON") ? 2'b10: 2'b00;
557 
 
558 
  //***************************************************************************
559 
  // Debug
560 
  //***************************************************************************
561 
 
562 
  always @(*) begin
563 
    for (d = 0; d < RANKS; d = d + 1) begin
564 
      for (e = 0; e < DQS_WIDTH; e = e + 1) begin
565 
        idelay_tap_cnt_w[(5*e+5*DQS_WIDTH*d)+:5] = idelay_tap_cnt_r[d][e];
566 
        dbg_cpt_tap_cnt_w[(6*e+6*DQS_WIDTH*d)+:6] = rdlvl_dqs_tap_cnt_r[d][e];
567 
      end
568 
    end
569 
  end
570 
 
571 
  assign mpr_rdlvl_err         = rdlvl_stg1_err & (!mpr_rdlvl_done);
572 
  assign rdlvl_err              = rdlvl_stg1_err & (mpr_rdlvl_done);
573 
 
574 
 
575 
  assign dbg_phy_rdlvl[0]      = rdlvl_stg1_start;
576 
  assign dbg_phy_rdlvl[1]      = pat_data_match_r;
577 
  assign dbg_phy_rdlvl[2]      = mux_rd_valid_r;
578 
  assign dbg_phy_rdlvl[3]      = idelay_tap_limit_r;
579 
  assign dbg_phy_rdlvl[8:4]    = 'b0;
580 
  assign dbg_phy_rdlvl[14:9]   = cal1_state_r[5:0];
581 
  assign dbg_phy_rdlvl[20:15]  = cnt_idel_dec_cpt_r;
582 
  assign dbg_phy_rdlvl[21]     = found_first_edge_r;
583 
  assign dbg_phy_rdlvl[22]     = found_second_edge_r;
584 
  assign dbg_phy_rdlvl[23]     = found_edge_r;
585 
  assign dbg_phy_rdlvl[24]     = store_sr_r;
586 
  // [40:25] previously used for sr, old_sr shift registers. If connecting
587 
  // these signals again, don't forget to parameterize based on RD_SHIFT_LEN
588 
  assign dbg_phy_rdlvl[40:25]  = 'b0;
589 
  assign dbg_phy_rdlvl[41]     = sr_valid_r;
590 
  assign dbg_phy_rdlvl[42]     = found_stable_eye_r;
591 
  assign dbg_phy_rdlvl[48:43]  = tap_cnt_cpt_r;
592 
  assign dbg_phy_rdlvl[54:49]  = first_edge_taps_r;
593 
  assign dbg_phy_rdlvl[60:55]  = second_edge_taps_r;
594 
  assign dbg_phy_rdlvl[64:61]  = cal1_cnt_cpt_timing_r;
595 
  assign dbg_phy_rdlvl[65]     = cal1_dlyce_cpt_r;
596 
  assign dbg_phy_rdlvl[66]     = cal1_dlyinc_cpt_r;
597 
  assign dbg_phy_rdlvl[67]     = found_edge_r;
598 
  assign dbg_phy_rdlvl[68]     = found_first_edge_r;
599 
  assign dbg_phy_rdlvl[73:69]  = 'b0;
600 
  assign dbg_phy_rdlvl[74]     = idel_pat_data_match;
601 
  assign dbg_phy_rdlvl[75]     = idel_pat0_data_match_r;
602 
  assign dbg_phy_rdlvl[76]     = idel_pat1_data_match_r;
603 
  assign dbg_phy_rdlvl[77]     = pat0_data_match_r;
604 
  assign dbg_phy_rdlvl[78]     = pat1_data_match_r;
605 
  assign dbg_phy_rdlvl[79+:5*DQS_WIDTH*RANKS] = idelay_tap_cnt_w;
606 
  assign dbg_phy_rdlvl[170+:8] = mux_rd_rise0_r;
607 
  assign dbg_phy_rdlvl[178+:8] = mux_rd_fall0_r;
608 
  assign dbg_phy_rdlvl[186+:8] = mux_rd_rise1_r;
609 
  assign dbg_phy_rdlvl[194+:8] = mux_rd_fall1_r;
610 
  assign dbg_phy_rdlvl[202+:8] = mux_rd_rise2_r;
611 
  assign dbg_phy_rdlvl[210+:8] = mux_rd_fall2_r;
612 
  assign dbg_phy_rdlvl[218+:8] = mux_rd_rise3_r;
613 
  assign dbg_phy_rdlvl[226+:8] = mux_rd_fall3_r;
614 
 
615 
  //***************************************************************************
616 
  // Debug output
617 
  //***************************************************************************
618 
 
619 
  // CPT taps
620 
  assign dbg_cpt_first_edge_cnt  = dbg_cpt_first_edge_taps;
621 
  assign dbg_cpt_second_edge_cnt = dbg_cpt_second_edge_taps;
622 
  assign dbg_cpt_tap_cnt         = dbg_cpt_tap_cnt_w;
623 
  assign dbg_dq_idelay_tap_cnt   = idelay_tap_cnt_w;
624 
 
625 
  // Record first and second edges found during CPT calibration
626 
 
627 
  generate
628 
    always @(posedge clk)
629 
      if (rst) begin
630 
        dbg_cpt_first_edge_taps  <= #TCQ 'b0;
631 
        dbg_cpt_second_edge_taps <= #TCQ 'b0;
632 
      end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_CALC_IDEL)) begin
633 
        //for (ce_rnk_i = 0; ce_rnk_i < RANKS; ce_rnk_i = ce_rnk_i + 1) begin: gen_dbg_cpt_rnk
634 
          for (ce_i = 0; ce_i < DQS_WIDTH; ce_i = ce_i + 1) begin: gen_dbg_cpt_edge
635 
            if (found_first_edge_r)
636 
              dbg_cpt_first_edge_taps[(6*ce_i)+:6]
637 
                  <= #TCQ first_edge_taps_r;
638 
            if (found_second_edge_r)
639 
              dbg_cpt_second_edge_taps[(6*ce_i)+:6]
640 
                  <= #TCQ second_edge_taps_r;
641 
          end
642 
        //end
643 
      end else if (cal1_state_r == CAL1_CALC_IDEL) begin
644 
        // Record tap counts of first and second edge edges during
645 
        // CPT calibration for each DQS group. If neither edge has
646 
        // been found, then those taps will remain 0
647 
          if (found_first_edge_r)
648 
            dbg_cpt_first_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6]
649 
              <= #TCQ first_edge_taps_r;
650 
          if (found_second_edge_r)
651 
            dbg_cpt_second_edge_taps[((cal1_cnt_cpt_timing <<2) + (cal1_cnt_cpt_timing <<1))+:6]
652 
              <= #TCQ second_edge_taps_r;
653 
      end
654 
  endgenerate
655 
 
656 
  assign rdlvl_stg1_rnk_done = rdlvl_rank_done_r;// || regl_rank_done_r;
657 
  assign mpr_rnk_done        = mpr_rank_done_r;
658 
  assign mpr_rdlvl_done      = ((DRAM_TYPE == "DDR3") && (OCAL_EN == "ON")) ? //&& (SIM_CAL_OPTION == "NONE")
659 
                                mpr_rdlvl_done_r : 1'b1;
660 
 
661 
   //**************************************************************************
662 
   // DQS count to hard PHY during write calibration using Phaser_OUT Stage2
663 
   // coarse delay
664 
   //**************************************************************************
665 
   assign pi_stg2_rdlvl_cnt = (cal1_state_r == CAL1_REGL_LOAD) ? regl_dqs_cnt_r : cal1_cnt_cpt_r;
666 
 
667 
   assign idelay_ce  = cal1_dq_idel_ce;
668 
   assign idelay_inc = cal1_dq_idel_inc;
669 
 
670 
  //***************************************************************************
671 
  // Assert calib_in_common in FAST_CAL mode for IDELAY tap increments to all
672 
  // DQs simultaneously
673 
  //***************************************************************************
674 
 
675 
  always @(posedge clk) begin
676 
    if (rst)
677 
      rdlvl_assrt_common <= #TCQ 1'b0;
678 
    else if ((SIM_CAL_OPTION == "FAST_CAL") & rdlvl_stg1_start &
679 
            !rdlvl_stg1_start_r)
680 
      rdlvl_assrt_common <= #TCQ 1'b1;
681 
    else if (!idel_pat_data_match_r & idel_pat_data_match)
682 
      rdlvl_assrt_common <= #TCQ 1'b0;
683 
  end
684 
 
685 
  //***************************************************************************
686 
  // Data mux to route appropriate bit to calibration logic - i.e. calibration
687 
  // is done sequentially, one bit (or DQS group) at a time
688 
  //***************************************************************************
689 
 
690 
  generate
691 
    if (nCK_PER_CLK == 4) begin: rd_data_div4_logic_clk
692 
      assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
693 
      assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
694 
      assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
695 
      assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
696 
      assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];
697 
      assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];
698 
      assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];
699 
      assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];
700 
    end else begin: rd_data_div2_logic_clk
701 
      assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];
702 
      assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];
703 
      assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];
704 
      assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];
705 
    end
706 
  endgenerate
707 
 
708 
  always @(posedge clk) begin
709 
    rd_mux_sel_r <= #TCQ cal1_cnt_cpt_r;
710 
  end
711 
 
712 
  // Register outputs for improved timing.
713 
  // NOTE: Will need to change when per-bit DQ deskew is supported.
714 
  //       Currenly all bits in DQS group are checked in aggregate
715 
  generate
716 
    genvar mux_i;
717 
    for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd
718 
      always @(posedge clk) begin
719 
        mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r +
720 
                                                    mux_i];
721 
        mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r +
722 
                                                    mux_i];
723 
        mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r +
724 
                                                    mux_i];
725 
        mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r +
726 
                                                    mux_i];
727 
        mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r +
728 
                                                    mux_i];
729 
        mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r +
730 
                                                    mux_i];
731 
        mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r +
732 
                                                    mux_i];
733 
        mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r +
734 
                                                    mux_i];
735 
      end
736 
    end
737 
  endgenerate
738 
 
739 
  //***************************************************************************
740 
  // MPR Read Leveling
741 
  //***************************************************************************
742 
 
743 
  // storing the previous read data for checking later. Only bit 0 is used
744 
  // since MPR contents (01010101) are available generally on DQ[0] per
745 
  // JEDEC spec.
746 
   always @(posedge clk)begin
747 
     if ((cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) ||
748 
        ((cal1_state_r == CAL1_MPR_PAT_DETECT) && (idel_pat_detect_valid_r)))begin
749 
       mpr_rd_rise0_prev_r <= #TCQ mux_rd_rise0_r[0];
750 
       mpr_rd_fall0_prev_r <= #TCQ mux_rd_fall0_r[0];
751 
       mpr_rd_rise1_prev_r <= #TCQ mux_rd_rise1_r[0];
752 
       mpr_rd_fall1_prev_r <= #TCQ mux_rd_fall1_r[0];
753 
       mpr_rd_rise2_prev_r <= #TCQ mux_rd_rise2_r[0];
754 
       mpr_rd_fall2_prev_r <= #TCQ mux_rd_fall2_r[0];
755 
       mpr_rd_rise3_prev_r <= #TCQ mux_rd_rise3_r[0];
756 
       mpr_rd_fall3_prev_r <= #TCQ mux_rd_fall3_r[0];
757 
     end
758 
   end
759 
 
760 
   generate
761 
    if (nCK_PER_CLK == 4) begin: mpr_4to1
762 
   // changed stable count of 2 IDELAY taps at 78 ps resolution
763 
   always @(posedge clk) begin
764 
      if (rst | (cal1_state_r == CAL1_NEW_DQS_PREWAIT) |
765 
         //(cal1_state_r == CAL1_DETECT_EDGE) |
766 
         (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) |
767 
         (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) |
768 
         (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) |
769 
         (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) |
770 
         (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) |
771 
         (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) |
772 
         (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) |
773 
         (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0]))
774 
        stable_idel_cnt <= #TCQ 3'd0;
775 
      else if ((|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) &
776 
               ((cal1_state_r == CAL1_MPR_PAT_DETECT) &
777 
               (idel_pat_detect_valid_r))) begin
778 
        if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) &
779 
            (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) &
780 
            (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) &
781 
            (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) &
782 
            (mpr_rd_rise2_prev_r == mux_rd_rise2_r[0]) &
783 
            (mpr_rd_fall2_prev_r == mux_rd_fall2_r[0]) &
784 
            (mpr_rd_rise3_prev_r == mux_rd_rise3_r[0]) &
785 
            (mpr_rd_fall3_prev_r == mux_rd_fall3_r[0]) &
786 
            (stable_idel_cnt < 3'd2))
787 
          stable_idel_cnt <= #TCQ stable_idel_cnt + 1;
788 
      end
789 
   end
790 
 
791 
   always @(posedge clk) begin
792 
     if (rst |
793 
         (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
794 
          mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r &
795 
          mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r &
796 
          mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r))
797 
       inhibit_edge_detect_r <= 1'b1;
798 
     // Wait for settling time after idelay tap increment before
799 
     // de-asserting inhibit_edge_detect_r
800 
     else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) &
801 
              (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) &
802 
              (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
803 
               ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r &
804 
               ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r &
805 
               ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r))
806 
       inhibit_edge_detect_r <= 1'b0;
807 
   end
808 
 
809 
   //checking for transition from 01010101 to 10101010
810 
   always @(posedge clk)begin
811 
     if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |
812 
         inhibit_edge_detect_r)
813 
       idel_mpr_pat_detect_r     <= #TCQ 1'b0;
814 
     // 10101010 is not the correct pattern
815 
     else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
816 
               mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r &
817 
               mpr_rd_rise2_prev_r & ~mpr_rd_fall2_prev_r &
818 
               mpr_rd_rise3_prev_r & ~mpr_rd_fall3_prev_r) ||
819 
              ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT)
820 
               && (idel_pat_detect_valid_r)))
821 
              //|| (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2))
822 
       idel_mpr_pat_detect_r     <= #TCQ 1'b0;
823 
     // 01010101 to 10101010 is the correct transition
824 
     else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
825 
               ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r &
826 
               ~mpr_rd_rise2_prev_r & mpr_rd_fall2_prev_r &
827 
               ~mpr_rd_rise3_prev_r & mpr_rd_fall3_prev_r) &
828 
               (stable_idel_cnt == 3'd2) &
829 
               ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) ||
830 
                (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) ||
831 
                (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) ||
832 
                (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]) ||
833 
                (mpr_rd_rise2_prev_r != mux_rd_rise2_r[0]) ||
834 
                (mpr_rd_fall2_prev_r != mux_rd_fall2_r[0]) ||
835 
                (mpr_rd_rise3_prev_r != mux_rd_rise3_r[0]) ||
836 
                (mpr_rd_fall3_prev_r != mux_rd_fall3_r[0])))
837 
       idel_mpr_pat_detect_r     <= #TCQ 1'b1;
838 
   end
839 
    end else if (nCK_PER_CLK == 2) begin: mpr_2to1
840 
      // changed stable count of 2 IDELAY taps at 78 ps resolution
841 
      always @(posedge clk) begin
842 
         if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |
843 
            (mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) |
844 
            (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) |
845 
            (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) |
846 
            (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0]))
847 
           stable_idel_cnt <= #TCQ 3'd0;
848 
         else if ((idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd0) &
849 
                  ((cal1_state_r == CAL1_MPR_PAT_DETECT) &
850 
                  (idel_pat_detect_valid_r))) begin
851 
           if ((mpr_rd_rise0_prev_r == mux_rd_rise0_r[0]) &
852 
               (mpr_rd_fall0_prev_r == mux_rd_fall0_r[0]) &
853 
               (mpr_rd_rise1_prev_r == mux_rd_rise1_r[0]) &
854 
               (mpr_rd_fall1_prev_r == mux_rd_fall1_r[0]) &
855 
               (stable_idel_cnt < 3'd2))
856 
             stable_idel_cnt <= #TCQ stable_idel_cnt + 1;
857 
         end
858 
      end
859 
 
860 
      always @(posedge clk) begin
861 
        if (rst |
862 
            (mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
863 
             mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r))
864 
          inhibit_edge_detect_r <= 1'b1;
865 
        else if ((cal1_state_r == CAL1_MPR_PAT_DETECT) &
866 
                 (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] > 5'd1) &
867 
                 (~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
868 
                  ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r))
869 
          inhibit_edge_detect_r <= 1'b0;
870 
      end
871 
 
872 
      //checking for transition from 01010101 to 10101010
873 
      always @(posedge clk)begin
874 
        if (rst | (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) |
875 
            inhibit_edge_detect_r)
876 
          idel_mpr_pat_detect_r     <= #TCQ 1'b0;
877 
        // 1010 is not the correct pattern
878 
        else if ((mpr_rd_rise0_prev_r & ~mpr_rd_fall0_prev_r &
879 
                  mpr_rd_rise1_prev_r & ~mpr_rd_fall1_prev_r) ||
880 
                 ((stable_idel_cnt < 3'd2) & (cal1_state_r == CAL1_MPR_PAT_DETECT)
881 
                 & (idel_pat_detect_valid_r)))
882 
                 // ||(idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] < 5'd2))
883 
          idel_mpr_pat_detect_r     <= #TCQ 1'b0;
884 
        // 0101 to 1010 is the correct transition
885 
        else if ((~mpr_rd_rise0_prev_r & mpr_rd_fall0_prev_r &
886 
                  ~mpr_rd_rise1_prev_r & mpr_rd_fall1_prev_r) &
887 
                  (stable_idel_cnt == 3'd2) &
888 
                  ((mpr_rd_rise0_prev_r != mux_rd_rise0_r[0]) ||
889 
                   (mpr_rd_fall0_prev_r != mux_rd_fall0_r[0]) ||
890 
                   (mpr_rd_rise1_prev_r != mux_rd_rise1_r[0]) ||
891 
                   (mpr_rd_fall1_prev_r != mux_rd_fall1_r[0])))
892 
          idel_mpr_pat_detect_r     <= #TCQ 1'b1;
893 
      end
894 
    end
895 
  endgenerate
896 
 
897 
 
898 
 
899 
  // Registered signal indicates when mux_rd_rise/fall_r is valid
900 
  always @(posedge clk)
901 
    mux_rd_valid_r <= #TCQ ~phy_if_empty;
902 
 
903 
 
904 
  //***************************************************************************
905 
  // Decrement initial Phaser_IN fine delay value before proceeding with
906 
  // read calibration
907 
  //***************************************************************************
908 
 
909 
     always @(posedge clk) begin
910 
       dqs_po_dec_done_r1 <= #TCQ dqs_po_dec_done;
911 
       dqs_po_dec_done_r2 <= #TCQ dqs_po_dec_done_r1;
912 
       fine_dly_dec_done_r2 <= #TCQ fine_dly_dec_done_r1;
913 
       pi_fine_dly_dec_done <= #TCQ fine_dly_dec_done_r2;
914 
     end
915 
 
916 
     always @(posedge clk) begin
917 
       if (rst || pi_cnt_dec)
918 
         wait_cnt_r <= #TCQ 'd8;
919 
       else if (dqs_po_dec_done_r2 && (wait_cnt_r > 'd0))
920 
         wait_cnt_r <= #TCQ wait_cnt_r - 1;
921 
     end
922 
 
923 
     always @(posedge clk) begin
924 
     if (rst) begin
925 
       pi_rdval_cnt    <= #TCQ 'd0;
926 
     end else if (dqs_po_dec_done_r1 && ~dqs_po_dec_done_r2) begin
927 
       pi_rdval_cnt    <= #TCQ pi_counter_read_val;
928 
     end else if (pi_rdval_cnt > 'd0) begin
929 
       if (pi_cnt_dec)
930 
         pi_rdval_cnt  <= #TCQ pi_rdval_cnt - 1;
931 
       else
932 
         pi_rdval_cnt  <= #TCQ pi_rdval_cnt;
933 
     end else if (pi_rdval_cnt == 'd0) begin
934 
       pi_rdval_cnt    <= #TCQ pi_rdval_cnt;
935 
     end
936 
   end
937 
 
938 
   always @(posedge clk) begin
939 
     if (rst || (pi_rdval_cnt == 'd0))
940 
       pi_cnt_dec      <= #TCQ 1'b0;
941 
     else if (dqs_po_dec_done_r2 && (pi_rdval_cnt > 'd0)
942 
                  && (wait_cnt_r == 'd1))
943 
       pi_cnt_dec      <= #TCQ 1'b1;
944 
     else
945 
       pi_cnt_dec      <= #TCQ 1'b0;
946 
   end
947 
 
948 
   always @(posedge clk) begin
949 
     if (rst) begin
950 
       fine_dly_dec_done_r1 <= #TCQ 1'b0;
951 
     end else if (((pi_cnt_dec == 'd1) && (pi_rdval_cnt == 'd1)) ||
952 
                  (dqs_po_dec_done_r2 && (pi_rdval_cnt == 'd0))) begin
953 
       fine_dly_dec_done_r1 <= #TCQ 1'b1;
954 
     end
955 
   end
956 
 
957 
  //***************************************************************************
958 
  // Demultiplexor to control Phaser_IN delay values
959 
  //***************************************************************************
960 
 
961 
  // Read DQS
962 
  always @(posedge clk) begin
963 
    if (rst) begin
964 
      pi_en_stg2_f_timing     <= #TCQ 'b0;
965 
      pi_stg2_f_incdec_timing <= #TCQ 'b0;
966 
    end else if (pi_cnt_dec) begin
967 
      pi_en_stg2_f_timing     <= #TCQ 'b1;
968 
      pi_stg2_f_incdec_timing <= #TCQ 'b0;
969 
    end else if (cal1_dlyce_cpt_r) begin
970 
      if ((SIM_CAL_OPTION == "NONE") ||
971 
          (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
972 
        // Change only specified DQS
973 
        pi_en_stg2_f_timing     <= #TCQ 1'b1;
974 
        pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r;
975 
      end else if (SIM_CAL_OPTION == "FAST_CAL") begin
976 
        // if simulating, and "shortcuts" for calibration enabled, apply
977 
        // results to all DQSs (i.e. assume same delay on all
978 
        // DQSs).
979 
        pi_en_stg2_f_timing     <= #TCQ 1'b1;
980 
        pi_stg2_f_incdec_timing <= #TCQ cal1_dlyinc_cpt_r;
981 
      end
982 
    end else begin
983 
      pi_en_stg2_f_timing     <= #TCQ 'b0;
984 
      pi_stg2_f_incdec_timing <= #TCQ 'b0;
985 
    end
986 
  end
987 
 
988 
  // registered for timing
989 
  always @(posedge clk) begin
990 
    pi_en_stg2_f     <= #TCQ pi_en_stg2_f_timing;
991 
    pi_stg2_f_incdec <= #TCQ pi_stg2_f_incdec_timing;
992 
  end
993 
 
994 
   // This counter used to implement settling time between
995 
   // Phaser_IN rank register loads to different DQSs
996 
   always @(posedge clk) begin
997 
     if (rst)
998 
       done_cnt <= #TCQ 'b0;
999 
     else if (((cal1_state_r == CAL1_REGL_LOAD) &&
1000 
               (cal1_state_r1 == CAL1_NEXT_DQS)) ||
1001 
              ((done_cnt == 4'd1) && (cal1_state_r != CAL1_DONE)))
1002 
       done_cnt <= #TCQ 4'b1010;
1003 
     else if (done_cnt > 'b0)
1004 
       done_cnt <= #TCQ done_cnt - 1;
1005 
   end
1006 
 
1007 
   // During rank register loading the rank count must be sent to
1008 
   // Phaser_IN via the phy_ctl_wd?? If so phy_init will have to
1009 
   // issue NOPs during rank register loading with the appropriate
1010 
   // rank count
1011 
   always @(posedge clk) begin
1012 
     if (rst || (regl_rank_done_r == 1'b1))
1013 
       regl_rank_done_r <= #TCQ 1'b0;
1014 
     else if ((regl_dqs_cnt == DQS_WIDTH-1) &&
1015 
              (regl_rank_cnt != RANKS-1) &&
1016 
              (done_cnt == 4'd1))
1017 
       regl_rank_done_r <= #TCQ 1'b1;
1018 
   end
1019 
 
1020 
   // Temp wire for timing.
1021 
   // The following in the always block below causes timing issues
1022 
   // due to DSP block inference
1023 
   // 6*regl_dqs_cnt.
1024 
   // replacing this with two left shifts + 1 left shift to avoid
1025 
   // DSP multiplier.
1026 
   assign regl_dqs_cnt_timing = {2'd0, regl_dqs_cnt};
1027 
 
1028 
   // Load Phaser_OUT rank register with rdlvl delay value
1029 
   // for each DQS per rank.
1030 
   always @(posedge clk) begin
1031 
     if (rst || (done_cnt == 4'd0)) begin
1032 
       pi_stg2_load_timing    <= #TCQ 'b0;
1033 
       pi_stg2_reg_l_timing   <= #TCQ 'b0;
1034 
     end else if ((cal1_state_r == CAL1_REGL_LOAD) &&
1035 
                  (regl_dqs_cnt <= DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
1036 
       pi_stg2_load_timing  <= #TCQ 'b1;
1037 
       pi_stg2_reg_l_timing <= #TCQ
1038 
         rdlvl_dqs_tap_cnt_r[rnk_cnt_r][regl_dqs_cnt];
1039 
     end else begin
1040 
       pi_stg2_load_timing  <= #TCQ 'b0;
1041 
       pi_stg2_reg_l_timing <= #TCQ 'b0;
1042 
     end
1043 
   end
1044 
 
1045 
   // registered for timing
1046 
   always @(posedge clk) begin
1047 
     pi_stg2_load  <= #TCQ pi_stg2_load_timing;
1048 
     pi_stg2_reg_l <= #TCQ pi_stg2_reg_l_timing;
1049 
   end
1050 
 
1051 
   always @(posedge clk) begin
1052 
     if (rst || (done_cnt == 4'd0) ||
1053 
         (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
1054 
       regl_rank_cnt   <= #TCQ 2'b00;
1055 
     else if ((cal1_state_r == CAL1_REGL_LOAD) &&
1056 
              (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
1057 
       if (regl_rank_cnt == RANKS-1)
1058 
         regl_rank_cnt  <= #TCQ regl_rank_cnt;
1059 
       else
1060 
         regl_rank_cnt <= #TCQ regl_rank_cnt + 1;
1061 
     end
1062 
   end
1063 
 
1064 
   always @(posedge clk) begin
1065 
     if (rst || (done_cnt == 4'd0) ||
1066 
         (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
1067 
       regl_dqs_cnt    <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
1068 
     else if ((cal1_state_r == CAL1_REGL_LOAD) &&
1069 
              (regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1)) begin
1070 
       if (regl_rank_cnt == RANKS-1)
1071 
         regl_dqs_cnt  <= #TCQ regl_dqs_cnt;
1072 
       else
1073 
         regl_dqs_cnt  <= #TCQ 'b0;
1074 
     end else if ((cal1_state_r == CAL1_REGL_LOAD) && (regl_dqs_cnt != DQS_WIDTH-1)
1075 
                  && (done_cnt == 4'd1))
1076 
       regl_dqs_cnt  <= #TCQ regl_dqs_cnt + 1;
1077 
     else
1078 
       regl_dqs_cnt  <= #TCQ regl_dqs_cnt;
1079 
   end
1080 
 
1081 
 
1082 
   always @(posedge clk)
1083 
     regl_dqs_cnt_r <= #TCQ regl_dqs_cnt;
1084 
  //*****************************************************************
1085 
  // DQ Stage 1 CALIBRATION INCREMENT/DECREMENT LOGIC:
1086 
  // The actual IDELAY elements for each of the DQ bits is set via the
1087 
  // DLYVAL parallel load port. However, the stage 1 calibration
1088 
  // algorithm (well most of it) only needs to increment or decrement the DQ
1089 
  // IDELAY value by 1 at any one time.
1090 
  //*****************************************************************
1091 
 
1092 
  // Chip-select generation for each of the individual counters tracking
1093 
  // IDELAY tap values for each DQ
1094 
  generate
1095 
    for (z = 0; z < DQS_WIDTH; z = z + 1) begin: gen_dlyce_dq
1096 
      always @(posedge clk)
1097 
        if (rst)
1098 
          dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
1099 
        else
1100 
          if (SIM_CAL_OPTION == "SKIP_CAL")
1101 
            // If skipping calibration altogether (only for simulation), no
1102 
            // need to set DQ IODELAY values - they are hardcoded
1103 
            dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
1104 
          else if (SIM_CAL_OPTION == "FAST_CAL") begin
1105 
            // If fast calibration option (simulation only) selected, DQ
1106 
            // IODELAYs across all bytes are updated simultaneously
1107 
            // (although per-bit deskew within DQS[0] is still supported)
1108 
            for (h = 0; h < DRAM_WIDTH; h = h + 1) begin
1109 
              dlyce_dq_r[DRAM_WIDTH*z + h] <= #TCQ cal1_dlyce_dq_r;
1110 
            end
1111 
          end else if ((SIM_CAL_OPTION == "NONE") ||
1112 
                   (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
1113 
            if (cal1_cnt_cpt_r == z) begin
1114 
              for (g = 0; g < DRAM_WIDTH; g = g + 1) begin
1115 
                dlyce_dq_r[DRAM_WIDTH*z + g]
1116 
                <= #TCQ cal1_dlyce_dq_r;
1117 
              end
1118 
            end else
1119 
              dlyce_dq_r[DRAM_WIDTH*z+:DRAM_WIDTH] <= #TCQ 'b0;
1120 
          end
1121 
    end
1122 
  endgenerate
1123 
 
1124 
  // Also delay increment/decrement control to match delay on DLYCE
1125 
  always @(posedge clk)
1126 
    if (rst)
1127 
      dlyinc_dq_r <= #TCQ 1'b0;
1128 
    else
1129 
      dlyinc_dq_r <= #TCQ cal1_dlyinc_dq_r;
1130 
 
1131 
 
1132 
  // Each DQ has a counter associated with it to record current read-leveling
1133 
  // delay value
1134 
  always @(posedge clk)
1135 
    // Reset or skipping calibration all together
1136 
    if (rst | (SIM_CAL_OPTION == "SKIP_CAL")) begin
1137 
      for (aa = 0; aa < RANKS; aa = aa + 1) begin: rst_dlyval_dq_reg_r
1138 
        for (bb = 0; bb < DQ_WIDTH; bb = bb + 1)
1139 
          dlyval_dq_reg_r[aa][bb] <= #TCQ 'b0;
1140 
      end
1141 
    end else if (SIM_CAL_OPTION == "FAST_CAL") begin
1142 
      for (n = 0; n < RANKS; n = n + 1) begin: gen_dlyval_dq_reg_rnk
1143 
        for (r = 0; r < DQ_WIDTH; r = r + 1) begin: gen_dlyval_dq_reg
1144 
          if (dlyce_dq_r[r]) begin
1145 
            if (dlyinc_dq_r)
1146 
              dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] + 5'h01;
1147 
            else
1148 
              dlyval_dq_reg_r[n][r] <= #TCQ dlyval_dq_reg_r[n][r] - 5'h01;
1149 
          end
1150 
        end
1151 
      end
1152 
    end else begin
1153 
      if (dlyce_dq_r[cal1_cnt_cpt_r]) begin
1154 
        if (dlyinc_dq_r)
1155 
          dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ
1156 
            dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] + 5'h01;
1157 
        else
1158 
          dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] <= #TCQ
1159 
            dlyval_dq_reg_r[rnk_cnt_r][cal1_cnt_cpt_r] - 5'h01;
1160 
      end
1161 
    end
1162 
 
1163 
  // Register for timing (help with logic placement)
1164 
  always @(posedge clk) begin
1165 
    for (cc = 0; cc < RANKS; cc = cc + 1) begin: dlyval_dq_assgn
1166 
      for (dd = 0; dd < DQ_WIDTH; dd = dd + 1)
1167 
        dlyval_dq[((5*dd)+(cc*DQ_WIDTH*5))+:5] <= #TCQ dlyval_dq_reg_r[cc][dd];
1168 
      end
1169 
  end
1170 
 
1171 
  //***************************************************************************
1172 
  // Generate signal used to delay calibration state machine - used when:
1173 
  //  (1) IDELAY value changed
1174 
  //  (2) RD_MUX_SEL value changed
1175 
  // Use when a delay is necessary to give the change time to propagate
1176 
  // through the data pipeline (through IDELAY and ISERDES, and fabric
1177 
  // pipeline stages)
1178 
  //***************************************************************************
1179 
 
1180 
 
1181 
  // List all the stage 1 calibration wait states here.
1182 
        // verilint STARC-2.7.3.3b off
1183 
  always @(posedge clk)
1184 
    if ((cal1_state_r == CAL1_NEW_DQS_WAIT) ||
1185 
        (cal1_state_r == CAL1_MPR_NEW_DQS_WAIT) ||
1186 
        (cal1_state_r == CAL1_NEW_DQS_PREWAIT) ||
1187 
        (cal1_state_r == CAL1_VALID_WAIT) ||
1188 
        (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||
1189 
        (cal1_state_r == CAL1_PB_INC_CPT_WAIT) ||
1190 
        (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT) ||
1191 
        (cal1_state_r == CAL1_PB_INC_DQ_WAIT) ||
1192 
        (cal1_state_r == CAL1_PB_DEC_CPT_WAIT) ||
1193 
        (cal1_state_r == CAL1_IDEL_INC_CPT_WAIT) ||
1194 
                (cal1_state_r == CAL1_IDEL_DEC_CPT_WAIT) ||
1195 
        (cal1_state_r == CAL1_STORE_FIRST_WAIT) ||
1196 
        (cal1_state_r == CAL1_DQ_IDEL_TAP_INC_WAIT) ||
1197 
        (cal1_state_r == CAL1_DQ_IDEL_TAP_DEC_WAIT))
1198 
      cal1_wait_cnt_en_r <= #TCQ 1'b1;
1199 
    else
1200 
      cal1_wait_cnt_en_r <= #TCQ 1'b0;
1201 
// verilint STARC-2.7.3.3b on
1202 
  always @(posedge clk)
1203 
    if (!cal1_wait_cnt_en_r) begin
1204 
      cal1_wait_cnt_r <= #TCQ 5'b00000;
1205 
      cal1_wait_r     <= #TCQ 1'b1;
1206 
    end else begin
1207 
      if (cal1_wait_cnt_r != PIPE_WAIT_CNT - 1) begin
1208 
        cal1_wait_cnt_r <= #TCQ cal1_wait_cnt_r + 1;
1209 
        cal1_wait_r     <= #TCQ 1'b1;
1210 
      end else begin
1211 
        // Need to reset to 0 to handle the case when there are two
1212 
        // different WAIT states back-to-back
1213 
        cal1_wait_cnt_r <= #TCQ 5'b00000;
1214 
        cal1_wait_r     <= #TCQ 1'b0;
1215 
      end
1216 
    end
1217 
 
1218 
  //***************************************************************************
1219 
  // generate request to PHY_INIT logic to issue precharged. Required when
1220 
  // calibration can take a long time (during which there are only constant
1221 
  // reads present on this bus). In this case need to issue perioidic
1222 
  // precharges to avoid tRAS violation. This signal must meet the following
1223 
  // requirements: (1) only transition from 0->1 when prech is first needed,
1224 
  // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted
1225 
  //***************************************************************************
1226 
 
1227 
  always @(posedge clk)
1228 
    if (rst)
1229 
      rdlvl_prech_req <= #TCQ 1'b0;
1230 
    else
1231 
      rdlvl_prech_req <= #TCQ cal1_prech_req_r;
1232 
 
1233 
  //***************************************************************************
1234 
  // Serial-to-parallel register to store last RDDATA_SHIFT_LEN cycles of
1235 
  // data from ISERDES. The value of this register is also stored, so that
1236 
  // previous and current values of the ISERDES data can be compared while
1237 
  // varying the IODELAY taps to see if an "edge" of the data valid window
1238 
  // has been encountered since the last IODELAY tap adjustment
1239 
  //***************************************************************************
1240 
 
1241 
  //***************************************************************************
1242 
  // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES
1243 
  // NOTE: Written using discrete flops, but SRL can be used if the matching
1244 
  //   logic does the comparison sequentially, rather than parallel
1245 
  //***************************************************************************
1246 
 
1247 
  generate
1248 
    genvar rd_i;
1249 
    if (nCK_PER_CLK == 4) begin: gen_sr_div4
1250 
      if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1
1251 
        for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
1252 
          always @(posedge clk) begin
1253 
            if (mux_rd_valid_r) begin
1254 
              sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];
1255 
              sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];
1256 
              sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];
1257 
              sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];
1258 
              sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];
1259 
              sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];
1260 
              sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];
1261 
              sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];
1262 
            end
1263 
          end
1264 
        end
1265 
      end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1
1266 
        for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
1267 
          always @(posedge clk) begin
1268 
            if (mux_rd_valid_r) begin
1269 
              sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],
1270 
                                        mux_rd_rise0_r[rd_i]};
1271 
              sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],
1272 
                                        mux_rd_fall0_r[rd_i]};
1273 
              sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],
1274 
                                        mux_rd_rise1_r[rd_i]};
1275 
              sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],
1276 
                                        mux_rd_fall1_r[rd_i]};
1277 
              sr_rise2_r[rd_i] <= #TCQ {sr_rise2_r[rd_i][RD_SHIFT_LEN-2:0],
1278 
                                        mux_rd_rise2_r[rd_i]};
1279 
              sr_fall2_r[rd_i] <= #TCQ {sr_fall2_r[rd_i][RD_SHIFT_LEN-2:0],
1280 
                                        mux_rd_fall2_r[rd_i]};
1281 
              sr_rise3_r[rd_i] <= #TCQ {sr_rise3_r[rd_i][RD_SHIFT_LEN-2:0],
1282 
                                        mux_rd_rise3_r[rd_i]};
1283 
              sr_fall3_r[rd_i] <= #TCQ {sr_fall3_r[rd_i][RD_SHIFT_LEN-2:0],
1284 
                                        mux_rd_fall3_r[rd_i]};
1285 
            end
1286 
          end
1287 
        end
1288 
      end
1289 
    end else if (nCK_PER_CLK == 2) begin: gen_sr_div2
1290 
      if (RD_SHIFT_LEN == 1) begin: gen_sr_len_eq1
1291 
        for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
1292 
          always @(posedge clk) begin
1293 
            if (mux_rd_valid_r) begin
1294 
              sr_rise0_r[rd_i] <= #TCQ {mux_rd_rise0_r[rd_i]};
1295 
              sr_fall0_r[rd_i] <= #TCQ {mux_rd_fall0_r[rd_i]};
1296 
              sr_rise1_r[rd_i] <= #TCQ {mux_rd_rise1_r[rd_i]};
1297 
              sr_fall1_r[rd_i] <= #TCQ {mux_rd_fall1_r[rd_i]};
1298 
            end
1299 
          end
1300 
        end
1301 
      end else if (RD_SHIFT_LEN > 1) begin: gen_sr_len_gt1
1302 
        for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr
1303 
          always @(posedge clk) begin
1304 
            if (mux_rd_valid_r) begin
1305 
              sr_rise0_r[rd_i] <= #TCQ {sr_rise0_r[rd_i][RD_SHIFT_LEN-2:0],
1306 
                                        mux_rd_rise0_r[rd_i]};
1307 
              sr_fall0_r[rd_i] <= #TCQ {sr_fall0_r[rd_i][RD_SHIFT_LEN-2:0],
1308 
                                        mux_rd_fall0_r[rd_i]};
1309 
              sr_rise1_r[rd_i] <= #TCQ {sr_rise1_r[rd_i][RD_SHIFT_LEN-2:0],
1310 
                                        mux_rd_rise1_r[rd_i]};
1311 
              sr_fall1_r[rd_i] <= #TCQ {sr_fall1_r[rd_i][RD_SHIFT_LEN-2:0],
1312 
                                        mux_rd_fall1_r[rd_i]};
1313 
            end
1314 
          end
1315 
        end
1316 
      end
1317 
    end
1318 
  endgenerate
1319 
 
1320 
  //***************************************************************************
1321 
  // Conversion to pattern calibration
1322 
  //***************************************************************************
1323 
 
1324 
  // Pattern for DQ IDELAY calibration
1325 
 
1326 
  //*****************************************************************
1327 
  // Expected data pattern when DQ shifted to the right such that
1328 
  // DQS before the left edge of the DVW:
1329 
  // Based on pattern of ({rise,fall}) =
1330 
  //   0x1, 0xB, 0x4, 0x4, 0xB, 0x9
1331 
  // Each nibble will look like:
1332 
  //   bit3: 0, 1, 0, 0, 1, 1
1333 
  //   bit2: 0, 0, 1, 1, 0, 0
1334 
  //   bit1: 0, 1, 0, 0, 1, 0
1335 
  //   bit0: 1, 1, 0, 0, 1, 1
1336 
  // Or if the write is early it could look like:
1337 
  //   0x4, 0x4, 0xB, 0x9, 0x6, 0xE
1338 
  //   bit3: 0, 0, 1, 1, 0, 1
1339 
  //   bit2: 1, 1, 0, 0, 1, 1
1340 
  //   bit1: 0, 0, 1, 0, 1, 1
1341 
  //   bit0: 0, 0, 1, 1, 0, 0
1342 
  // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN
1343 
  // and the actual training pattern contents change
1344 
  //*****************************************************************
1345 
 
1346 
  generate
1347 
    if (nCK_PER_CLK == 4) begin: gen_pat_div4
1348 
      // Pattern for DQ IDELAY increment
1349 
 
1350 
      // Target pattern for "early write"
1351 
      assign {idel_pat0_rise0[3], idel_pat0_rise0[2],
1352 
              idel_pat0_rise0[1], idel_pat0_rise0[0]} = 4'h1;
1353 
      assign {idel_pat0_fall0[3], idel_pat0_fall0[2],
1354 
              idel_pat0_fall0[1], idel_pat0_fall0[0]} = 4'h7;
1355 
      assign {idel_pat0_rise1[3], idel_pat0_rise1[2],
1356 
              idel_pat0_rise1[1], idel_pat0_rise1[0]} = 4'hE;
1357 
      assign {idel_pat0_fall1[3], idel_pat0_fall1[2],
1358 
              idel_pat0_fall1[1], idel_pat0_fall1[0]} = 4'hC;
1359 
      assign {idel_pat0_rise2[3], idel_pat0_rise2[2],
1360 
              idel_pat0_rise2[1], idel_pat0_rise2[0]} = 4'h9;
1361 
      assign {idel_pat0_fall2[3], idel_pat0_fall2[2],
1362 
              idel_pat0_fall2[1], idel_pat0_fall2[0]} = 4'h2;
1363 
      assign {idel_pat0_rise3[3], idel_pat0_rise3[2],
1364 
              idel_pat0_rise3[1], idel_pat0_rise3[0]} = 4'h4;
1365 
      assign {idel_pat0_fall3[3], idel_pat0_fall3[2],
1366 
              idel_pat0_fall3[1], idel_pat0_fall3[0]} = 4'hB;
1367 
 
1368 
      // Target pattern for "on-time write"
1369 
      assign {idel_pat1_rise0[3], idel_pat1_rise0[2],
1370 
              idel_pat1_rise0[1], idel_pat1_rise0[0]} = 4'h4;
1371 
      assign {idel_pat1_fall0[3], idel_pat1_fall0[2],
1372 
              idel_pat1_fall0[1], idel_pat1_fall0[0]} = 4'h9;
1373 
      assign {idel_pat1_rise1[3], idel_pat1_rise1[2],
1374 
              idel_pat1_rise1[1], idel_pat1_rise1[0]} = 4'h3;
1375 
      assign {idel_pat1_fall1[3], idel_pat1_fall1[2],
1376 
              idel_pat1_fall1[1], idel_pat1_fall1[0]} = 4'h7;
1377 
      assign {idel_pat1_rise2[3], idel_pat1_rise2[2],
1378 
              idel_pat1_rise2[1], idel_pat1_rise2[0]} = 4'hE;
1379 
      assign {idel_pat1_fall2[3], idel_pat1_fall2[2],
1380 
              idel_pat1_fall2[1], idel_pat1_fall2[0]} = 4'hC;
1381 
      assign {idel_pat1_rise3[3], idel_pat1_rise3[2],
1382 
              idel_pat1_rise3[1], idel_pat1_rise3[0]} = 4'h9;
1383 
      assign {idel_pat1_fall3[3], idel_pat1_fall3[2],
1384 
              idel_pat1_fall3[1], idel_pat1_fall3[0]} = 4'h2;
1385 
 
1386 
 
1387 
      // Correct data valid window for "early write"
1388 
      assign {pat0_rise0[3], pat0_rise0[2],
1389 
              pat0_rise0[1], pat0_rise0[0]} = 4'h7;
1390 
      assign {pat0_fall0[3], pat0_fall0[2],
1391 
              pat0_fall0[1], pat0_fall0[0]} = 4'hE;
1392 
      assign {pat0_rise1[3], pat0_rise1[2],
1393 
              pat0_rise1[1], pat0_rise1[0]} = 4'hC;
1394 
      assign {pat0_fall1[3], pat0_fall1[2],
1395 
              pat0_fall1[1], pat0_fall1[0]} = 4'h9;
1396 
      assign {pat0_rise2[3], pat0_rise2[2],
1397 
              pat0_rise2[1], pat0_rise2[0]} = 4'h2;
1398 
      assign {pat0_fall2[3], pat0_fall2[2],
1399 
              pat0_fall2[1], pat0_fall2[0]} = 4'h4;
1400 
      assign {pat0_rise3[3], pat0_rise3[2],
1401 
              pat0_rise3[1], pat0_rise3[0]} = 4'hB;
1402 
      assign {pat0_fall3[3], pat0_fall3[2],
1403 
              pat0_fall3[1], pat0_fall3[0]} = 4'h1;
1404 
 
1405 
      // Correct data valid window for "on-time write"
1406 
      assign {pat1_rise0[3], pat1_rise0[2],
1407 
              pat1_rise0[1], pat1_rise0[0]} = 4'h9;
1408 
      assign {pat1_fall0[3], pat1_fall0[2],
1409 
              pat1_fall0[1], pat1_fall0[0]} = 4'h3;
1410 
      assign {pat1_rise1[3], pat1_rise1[2],
1411 
              pat1_rise1[1], pat1_rise1[0]} = 4'h7;
1412 
      assign {pat1_fall1[3], pat1_fall1[2],
1413 
              pat1_fall1[1], pat1_fall1[0]} = 4'hE;
1414 
      assign {pat1_rise2[3], pat1_rise2[2],
1415 
              pat1_rise2[1], pat1_rise2[0]} = 4'hC;
1416 
      assign {pat1_fall2[3], pat1_fall2[2],
1417 
              pat1_fall2[1], pat1_fall2[0]} = 4'h9;
1418 
      assign {pat1_rise3[3], pat1_rise3[2],
1419 
              pat1_rise3[1], pat1_rise3[0]} = 4'h2;
1420 
      assign {pat1_fall3[3], pat1_fall3[2],
1421 
              pat1_fall3[1], pat1_fall3[0]} = 4'h4;
1422 
 
1423 
    end else if (nCK_PER_CLK == 2) begin: gen_pat_div2
1424 
 
1425 
            // Pattern for DQ IDELAY increment
1426 
 
1427 
      // Target pattern for "early write"
1428 
      assign idel_pat0_rise0[3] = 2'b01;
1429 
      assign idel_pat0_fall0[3] = 2'b00;
1430 
      assign idel_pat0_rise1[3] = 2'b10;
1431 
      assign idel_pat0_fall1[3] = 2'b11;
1432 
 
1433 
      assign idel_pat0_rise0[2] = 2'b00;
1434 
      assign idel_pat0_fall0[2] = 2'b10;
1435 
      assign idel_pat0_rise1[2] = 2'b11;
1436 
      assign idel_pat0_fall1[2] = 2'b10;
1437 
 
1438 
      assign idel_pat0_rise0[1] = 2'b00;
1439 
      assign idel_pat0_fall0[1] = 2'b11;
1440 
      assign idel_pat0_rise1[1] = 2'b10;
1441 
      assign idel_pat0_fall1[1] = 2'b01;
1442 
 
1443 
      assign idel_pat0_rise0[0] = 2'b11;
1444 
      assign idel_pat0_fall0[0] = 2'b10;
1445 
      assign idel_pat0_rise1[0] = 2'b00;
1446 
      assign idel_pat0_fall1[0] = 2'b01;
1447 
 
1448 
 
1449 
      // Target pattern for "on-time write"
1450 
      assign idel_pat1_rise0[3] = 2'b01;
1451 
      assign idel_pat1_fall0[3] = 2'b11;
1452 
      assign idel_pat1_rise1[3] = 2'b01;
1453 
      assign idel_pat1_fall1[3] = 2'b00;
1454 
 
1455 
      assign idel_pat1_rise0[2] = 2'b11;
1456 
      assign idel_pat1_fall0[2] = 2'b01;
1457 
      assign idel_pat1_rise1[2] = 2'b00;
1458 
      assign idel_pat1_fall1[2] = 2'b10;
1459 
 
1460 
      assign idel_pat1_rise0[1] = 2'b01;
1461 
      assign idel_pat1_fall0[1] = 2'b00;
1462 
      assign idel_pat1_rise1[1] = 2'b10;
1463 
      assign idel_pat1_fall1[1] = 2'b11;
1464 
 
1465 
      assign idel_pat1_rise0[0] = 2'b00;
1466 
      assign idel_pat1_fall0[0] = 2'b10;
1467 
      assign idel_pat1_rise1[0] = 2'b11;
1468 
      assign idel_pat1_fall1[0] = 2'b10;
1469 
 
1470 
 
1471 
      // Correct data valid window for "early write"
1472 
      assign pat0_rise0[3] = 2'b00;
1473 
      assign pat0_fall0[3] = 2'b10;
1474 
      assign pat0_rise1[3] = 2'b11;
1475 
      assign pat0_fall1[3] = 2'b10;
1476 
 
1477 
      assign pat0_rise0[2] = 2'b10;
1478 
      assign pat0_fall0[2] = 2'b11;
1479 
      assign pat0_rise1[2] = 2'b10;
1480 
      assign pat0_fall1[2] = 2'b00;
1481 
 
1482 
      assign pat0_rise0[1] = 2'b11;
1483 
      assign pat0_fall0[1] = 2'b10;
1484 
      assign pat0_rise1[1] = 2'b01;
1485 
      assign pat0_fall1[1] = 2'b00;
1486 
 
1487 
      assign pat0_rise0[0] = 2'b10;
1488 
      assign pat0_fall0[0] = 2'b00;
1489 
      assign pat0_rise1[0] = 2'b01;
1490 
      assign pat0_fall1[0] = 2'b11;
1491 
 
1492 
      // Correct data valid window for "on-time write"
1493 
      assign pat1_rise0[3] = 2'b11;
1494 
      assign pat1_fall0[3] = 2'b01;
1495 
      assign pat1_rise1[3] = 2'b00;
1496 
      assign pat1_fall1[3] = 2'b10;
1497 
 
1498 
      assign pat1_rise0[2] = 2'b01;
1499 
      assign pat1_fall0[2] = 2'b00;
1500 
      assign pat1_rise1[2] = 2'b10;
1501 
      assign pat1_fall1[2] = 2'b11;
1502 
 
1503 
      assign pat1_rise0[1] = 2'b00;
1504 
      assign pat1_fall0[1] = 2'b10;
1505 
      assign pat1_rise1[1] = 2'b11;
1506 
      assign pat1_fall1[1] = 2'b10;
1507 
 
1508 
      assign pat1_rise0[0] = 2'b10;
1509 
      assign pat1_fall0[0] = 2'b11;
1510 
      assign pat1_rise1[0] = 2'b10;
1511 
      assign pat1_fall1[0] = 2'b00;
1512 
    end
1513 
  endgenerate
1514 
 
1515 
  // Each bit of each byte is compared to expected pattern.
1516 
  // This was done to prevent (and "drastically decrease") the chance that
1517 
  // invalid data clocked in when the DQ bus is tri-state (along with a
1518 
  // combination of the correct data) will resemble the expected data
1519 
  // pattern. A better fix for this is to change the training pattern and/or
1520 
  // make the pattern longer.
1521 
  generate
1522 
    genvar pt_i;
1523 
    if (nCK_PER_CLK == 4) begin: gen_pat_match_div4
1524 
      for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
1525 
 
1526 
        // DQ IDELAY pattern detection
1527 
        always @(posedge clk) begin
1528 
          if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4])
1529 
            idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
1530 
          else
1531 
            idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
1532 
 
1533 
          if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4])
1534 
            idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
1535 
          else
1536 
            idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
1537 
 
1538 
          if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4])
1539 
            idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
1540 
          else
1541 
            idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
1542 
 
1543 
          if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4])
1544 
            idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
1545 
          else
1546 
            idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
1547 
 
1548 
          if (sr_rise2_r[pt_i] == idel_pat0_rise2[pt_i%4])
1549 
            idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b1;
1550 
          else
1551 
            idel_pat0_match_rise2_r[pt_i] <= #TCQ 1'b0;
1552 
 
1553 
          if (sr_fall2_r[pt_i] == idel_pat0_fall2[pt_i%4])
1554 
            idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b1;
1555 
          else
1556 
            idel_pat0_match_fall2_r[pt_i] <= #TCQ 1'b0;
1557 
 
1558 
          if (sr_rise3_r[pt_i] == idel_pat0_rise3[pt_i%4])
1559 
            idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b1;
1560 
          else
1561 
            idel_pat0_match_rise3_r[pt_i] <= #TCQ 1'b0;
1562 
 
1563 
          if (sr_fall3_r[pt_i] == idel_pat0_fall3[pt_i%4])
1564 
            idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b1;
1565 
          else
1566 
            idel_pat0_match_fall3_r[pt_i] <= #TCQ 1'b0;
1567 
        end
1568 
 
1569 
        always @(posedge clk) begin
1570 
          if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4])
1571 
            idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
1572 
          else
1573 
            idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
1574 
 
1575 
          if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4])
1576 
            idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
1577 
          else
1578 
            idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
1579 
 
1580 
          if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4])
1581 
            idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
1582 
          else
1583 
            idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
1584 
 
1585 
          if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4])
1586 
            idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
1587 
          else
1588 
            idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
1589 
 
1590 
          if (sr_rise2_r[pt_i] == idel_pat1_rise2[pt_i%4])
1591 
            idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b1;
1592 
          else
1593 
            idel_pat1_match_rise2_r[pt_i] <= #TCQ 1'b0;
1594 
 
1595 
          if (sr_fall2_r[pt_i] == idel_pat1_fall2[pt_i%4])
1596 
            idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b1;
1597 
          else
1598 
            idel_pat1_match_fall2_r[pt_i] <= #TCQ 1'b0;
1599 
 
1600 
          if (sr_rise3_r[pt_i] == idel_pat1_rise3[pt_i%4])
1601 
            idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b1;
1602 
          else
1603 
            idel_pat1_match_rise3_r[pt_i] <= #TCQ 1'b0;
1604 
 
1605 
          if (sr_fall3_r[pt_i] == idel_pat1_fall3[pt_i%4])
1606 
            idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b1;
1607 
          else
1608 
            idel_pat1_match_fall3_r[pt_i] <= #TCQ 1'b0;
1609 
        end
1610 
 
1611 
        // DQS DVW pattern detection
1612 
        always @(posedge clk) begin
1613 
          if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4])
1614 
            pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
1615 
          else
1616 
            pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
1617 
 
1618 
          if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4])
1619 
            pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
1620 
          else
1621 
            pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
1622 
 
1623 
          if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4])
1624 
            pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
1625 
          else
1626 
            pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
1627 
 
1628 
          if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4])
1629 
            pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
1630 
          else
1631 
            pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
1632 
 
1633 
          if (sr_rise2_r[pt_i] == pat0_rise2[pt_i%4])
1634 
            pat0_match_rise2_r[pt_i] <= #TCQ 1'b1;
1635 
          else
1636 
            pat0_match_rise2_r[pt_i] <= #TCQ 1'b0;
1637 
 
1638 
          if (sr_fall2_r[pt_i] == pat0_fall2[pt_i%4])
1639 
            pat0_match_fall2_r[pt_i] <= #TCQ 1'b1;
1640 
          else
1641 
            pat0_match_fall2_r[pt_i] <= #TCQ 1'b0;
1642 
 
1643 
          if (sr_rise3_r[pt_i] == pat0_rise3[pt_i%4])
1644 
            pat0_match_rise3_r[pt_i] <= #TCQ 1'b1;
1645 
          else
1646 
            pat0_match_rise3_r[pt_i] <= #TCQ 1'b0;
1647 
 
1648 
          if (sr_fall3_r[pt_i] == pat0_fall3[pt_i%4])
1649 
            pat0_match_fall3_r[pt_i] <= #TCQ 1'b1;
1650 
          else
1651 
            pat0_match_fall3_r[pt_i] <= #TCQ 1'b0;
1652 
        end
1653 
 
1654 
        always @(posedge clk) begin
1655 
          if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
1656 
            pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
1657 
          else
1658 
            pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
1659 
 
1660 
          if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
1661 
            pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
1662 
          else
1663 
            pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
1664 
 
1665 
          if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
1666 
            pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
1667 
          else
1668 
            pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
1669 
 
1670 
          if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
1671 
            pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
1672 
          else
1673 
            pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
1674 
 
1675 
          if (sr_rise2_r[pt_i] == pat1_rise2[pt_i%4])
1676 
            pat1_match_rise2_r[pt_i] <= #TCQ 1'b1;
1677 
          else
1678 
            pat1_match_rise2_r[pt_i] <= #TCQ 1'b0;
1679 
 
1680 
          if (sr_fall2_r[pt_i] == pat1_fall2[pt_i%4])
1681 
            pat1_match_fall2_r[pt_i] <= #TCQ 1'b1;
1682 
          else
1683 
            pat1_match_fall2_r[pt_i] <= #TCQ 1'b0;
1684 
 
1685 
          if (sr_rise3_r[pt_i] == pat1_rise3[pt_i%4])
1686 
            pat1_match_rise3_r[pt_i] <= #TCQ 1'b1;
1687 
          else
1688 
            pat1_match_rise3_r[pt_i] <= #TCQ 1'b0;
1689 
 
1690 
          if (sr_fall3_r[pt_i] == pat1_fall3[pt_i%4])
1691 
            pat1_match_fall3_r[pt_i] <= #TCQ 1'b1;
1692 
          else
1693 
            pat1_match_fall3_r[pt_i] <= #TCQ 1'b0;
1694 
        end
1695 
 
1696 
      end
1697 
 
1698 
      // Combine pattern match "subterms" for DQ-IDELAY stage
1699 
      always @(posedge clk) begin
1700 
        idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r;
1701 
        idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r;
1702 
        idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r;
1703 
        idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r;
1704 
        idel_pat0_match_rise2_and_r <= #TCQ &idel_pat0_match_rise2_r;
1705 
        idel_pat0_match_fall2_and_r <= #TCQ &idel_pat0_match_fall2_r;
1706 
        idel_pat0_match_rise3_and_r <= #TCQ &idel_pat0_match_rise3_r;
1707 
        idel_pat0_match_fall3_and_r <= #TCQ &idel_pat0_match_fall3_r;
1708 
        idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r &&
1709 
                                        idel_pat0_match_fall0_and_r &&
1710 
                                        idel_pat0_match_rise1_and_r &&
1711 
                                        idel_pat0_match_fall1_and_r &&
1712 
                                        idel_pat0_match_rise2_and_r &&
1713 
                                        idel_pat0_match_fall2_and_r &&
1714 
                                        idel_pat0_match_rise3_and_r &&
1715 
                                        idel_pat0_match_fall3_and_r);
1716 
      end
1717 
 
1718 
      always @(posedge clk) begin
1719 
        idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r;
1720 
        idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r;
1721 
        idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r;
1722 
        idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r;
1723 
        idel_pat1_match_rise2_and_r <= #TCQ &idel_pat1_match_rise2_r;
1724 
        idel_pat1_match_fall2_and_r <= #TCQ &idel_pat1_match_fall2_r;
1725 
        idel_pat1_match_rise3_and_r <= #TCQ &idel_pat1_match_rise3_r;
1726 
        idel_pat1_match_fall3_and_r <= #TCQ &idel_pat1_match_fall3_r;
1727 
        idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r &&
1728 
                                        idel_pat1_match_fall0_and_r &&
1729 
                                        idel_pat1_match_rise1_and_r &&
1730 
                                        idel_pat1_match_fall1_and_r &&
1731 
                                        idel_pat1_match_rise2_and_r &&
1732 
                                        idel_pat1_match_fall2_and_r &&
1733 
                                        idel_pat1_match_rise3_and_r &&
1734 
                                        idel_pat1_match_fall3_and_r);
1735 
      end
1736 
 
1737 
      always @(*)
1738 
        idel_pat_data_match <= #TCQ idel_pat0_data_match_r |
1739 
                                    idel_pat1_data_match_r;
1740 
 
1741 
      always @(posedge clk)
1742 
        idel_pat_data_match_r <= #TCQ idel_pat_data_match;
1743 
 
1744 
      // Combine pattern match "subterms" for DQS-PHASER_IN stage
1745 
      always @(posedge clk) begin
1746 
        pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r;
1747 
        pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r;
1748 
        pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r;
1749 
        pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r;
1750 
        pat0_match_rise2_and_r <= #TCQ &pat0_match_rise2_r;
1751 
        pat0_match_fall2_and_r <= #TCQ &pat0_match_fall2_r;
1752 
        pat0_match_rise3_and_r <= #TCQ &pat0_match_rise3_r;
1753 
        pat0_match_fall3_and_r <= #TCQ &pat0_match_fall3_r;
1754 
        pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&
1755 
                                   pat0_match_fall0_and_r &&
1756 
                                   pat0_match_rise1_and_r &&
1757 
                                   pat0_match_fall1_and_r &&
1758 
                                   pat0_match_rise2_and_r &&
1759 
                                   pat0_match_fall2_and_r &&
1760 
                                   pat0_match_rise3_and_r &&
1761 
                                   pat0_match_fall3_and_r);
1762 
      end
1763 
 
1764 
      always @(posedge clk) begin
1765 
        pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
1766 
        pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
1767 
        pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
1768 
        pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
1769 
        pat1_match_rise2_and_r <= #TCQ &pat1_match_rise2_r;
1770 
        pat1_match_fall2_and_r <= #TCQ &pat1_match_fall2_r;
1771 
        pat1_match_rise3_and_r <= #TCQ &pat1_match_rise3_r;
1772 
        pat1_match_fall3_and_r <= #TCQ &pat1_match_fall3_r;
1773 
        pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
1774 
                                   pat1_match_fall0_and_r &&
1775 
                                   pat1_match_rise1_and_r &&
1776 
                                   pat1_match_fall1_and_r &&
1777 
                                   pat1_match_rise2_and_r &&
1778 
                                   pat1_match_fall2_and_r &&
1779 
                                   pat1_match_rise3_and_r &&
1780 
                                   pat1_match_fall3_and_r);
1781 
      end
1782 
 
1783 
      assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r;
1784 
 
1785 
    end else if (nCK_PER_CLK == 2) begin: gen_pat_match_div2
1786 
      for (pt_i = 0; pt_i < DRAM_WIDTH; pt_i = pt_i + 1) begin: gen_pat_match
1787 
 
1788 
        // DQ IDELAY pattern detection
1789 
        always @(posedge clk) begin
1790 
          if (sr_rise0_r[pt_i] == idel_pat0_rise0[pt_i%4])
1791 
            idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
1792 
          else
1793 
            idel_pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
1794 
 
1795 
          if (sr_fall0_r[pt_i] == idel_pat0_fall0[pt_i%4])
1796 
            idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
1797 
          else
1798 
            idel_pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
1799 
 
1800 
          if (sr_rise1_r[pt_i] == idel_pat0_rise1[pt_i%4])
1801 
            idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
1802 
          else
1803 
            idel_pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
1804 
 
1805 
          if (sr_fall1_r[pt_i] == idel_pat0_fall1[pt_i%4])
1806 
            idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
1807 
          else
1808 
            idel_pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
1809 
        end
1810 
 
1811 
        always @(posedge clk) begin
1812 
          if (sr_rise0_r[pt_i] == idel_pat1_rise0[pt_i%4])
1813 
            idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
1814 
          else
1815 
            idel_pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
1816 
 
1817 
          if (sr_fall0_r[pt_i] == idel_pat1_fall0[pt_i%4])
1818 
            idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
1819 
          else
1820 
            idel_pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
1821 
 
1822 
          if (sr_rise1_r[pt_i] == idel_pat1_rise1[pt_i%4])
1823 
            idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
1824 
          else
1825 
            idel_pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
1826 
 
1827 
          if (sr_fall1_r[pt_i] == idel_pat1_fall1[pt_i%4])
1828 
            idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
1829 
          else
1830 
            idel_pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
1831 
        end
1832 
 
1833 
        // DQS DVW pattern detection
1834 
        always @(posedge clk) begin
1835 
          if (sr_rise0_r[pt_i] == pat0_rise0[pt_i%4])
1836 
            pat0_match_rise0_r[pt_i] <= #TCQ 1'b1;
1837 
          else
1838 
            pat0_match_rise0_r[pt_i] <= #TCQ 1'b0;
1839 
 
1840 
          if (sr_fall0_r[pt_i] == pat0_fall0[pt_i%4])
1841 
            pat0_match_fall0_r[pt_i] <= #TCQ 1'b1;
1842 
          else
1843 
            pat0_match_fall0_r[pt_i] <= #TCQ 1'b0;
1844 
 
1845 
          if (sr_rise1_r[pt_i] == pat0_rise1[pt_i%4])
1846 
            pat0_match_rise1_r[pt_i] <= #TCQ 1'b1;
1847 
          else
1848 
            pat0_match_rise1_r[pt_i] <= #TCQ 1'b0;
1849 
 
1850 
          if (sr_fall1_r[pt_i] == pat0_fall1[pt_i%4])
1851 
            pat0_match_fall1_r[pt_i] <= #TCQ 1'b1;
1852 
          else
1853 
            pat0_match_fall1_r[pt_i] <= #TCQ 1'b0;
1854 
        end
1855 
 
1856 
        always @(posedge clk) begin
1857 
          if (sr_rise0_r[pt_i] == pat1_rise0[pt_i%4])
1858 
            pat1_match_rise0_r[pt_i] <= #TCQ 1'b1;
1859 
          else
1860 
            pat1_match_rise0_r[pt_i] <= #TCQ 1'b0;
1861 
 
1862 
          if (sr_fall0_r[pt_i] == pat1_fall0[pt_i%4])
1863 
            pat1_match_fall0_r[pt_i] <= #TCQ 1'b1;
1864 
          else
1865 
            pat1_match_fall0_r[pt_i] <= #TCQ 1'b0;
1866 
 
1867 
          if (sr_rise1_r[pt_i] == pat1_rise1[pt_i%4])
1868 
            pat1_match_rise1_r[pt_i] <= #TCQ 1'b1;
1869 
          else
1870 
            pat1_match_rise1_r[pt_i] <= #TCQ 1'b0;
1871 
 
1872 
          if (sr_fall1_r[pt_i] == pat1_fall1[pt_i%4])
1873 
            pat1_match_fall1_r[pt_i] <= #TCQ 1'b1;
1874 
          else
1875 
            pat1_match_fall1_r[pt_i] <= #TCQ 1'b0;
1876 
        end
1877 
 
1878 
      end
1879 
 
1880 
        // Combine pattern match "subterms" for DQ-IDELAY stage
1881 
      always @(posedge clk) begin
1882 
        idel_pat0_match_rise0_and_r <= #TCQ &idel_pat0_match_rise0_r;
1883 
        idel_pat0_match_fall0_and_r <= #TCQ &idel_pat0_match_fall0_r;
1884 
        idel_pat0_match_rise1_and_r <= #TCQ &idel_pat0_match_rise1_r;
1885 
        idel_pat0_match_fall1_and_r <= #TCQ &idel_pat0_match_fall1_r;
1886 
        idel_pat0_data_match_r <= #TCQ (idel_pat0_match_rise0_and_r &&
1887 
                                        idel_pat0_match_fall0_and_r &&
1888 
                                        idel_pat0_match_rise1_and_r &&
1889 
                                        idel_pat0_match_fall1_and_r);
1890 
      end
1891 
 
1892 
      always @(posedge clk) begin
1893 
        idel_pat1_match_rise0_and_r <= #TCQ &idel_pat1_match_rise0_r;
1894 
        idel_pat1_match_fall0_and_r <= #TCQ &idel_pat1_match_fall0_r;
1895 
        idel_pat1_match_rise1_and_r <= #TCQ &idel_pat1_match_rise1_r;
1896 
        idel_pat1_match_fall1_and_r <= #TCQ &idel_pat1_match_fall1_r;
1897 
        idel_pat1_data_match_r <= #TCQ (idel_pat1_match_rise0_and_r &&
1898 
                                        idel_pat1_match_fall0_and_r &&
1899 
                                        idel_pat1_match_rise1_and_r &&
1900 
                                        idel_pat1_match_fall1_and_r);
1901 
      end
1902 
 
1903 
      always @(posedge clk) begin
1904 
        if (sr_valid_r2)
1905 
          idel_pat_data_match <= #TCQ idel_pat0_data_match_r |
1906 
                                      idel_pat1_data_match_r;
1907 
      end
1908 
 
1909 
      //assign idel_pat_data_match = idel_pat0_data_match_r |
1910 
      //                             idel_pat1_data_match_r;
1911 
 
1912 
      always @(posedge clk)
1913 
        idel_pat_data_match_r <= #TCQ idel_pat_data_match;
1914 
 
1915 
      // Combine pattern match "subterms" for DQS-PHASER_IN stage
1916 
      always @(posedge clk) begin
1917 
        pat0_match_rise0_and_r <= #TCQ &pat0_match_rise0_r;
1918 
        pat0_match_fall0_and_r <= #TCQ &pat0_match_fall0_r;
1919 
        pat0_match_rise1_and_r <= #TCQ &pat0_match_rise1_r;
1920 
        pat0_match_fall1_and_r <= #TCQ &pat0_match_fall1_r;
1921 
        pat0_data_match_r <= #TCQ (pat0_match_rise0_and_r &&
1922 
                                   pat0_match_fall0_and_r &&
1923 
                                   pat0_match_rise1_and_r &&
1924 
                                   pat0_match_fall1_and_r);
1925 
      end
1926 
 
1927 
      always @(posedge clk) begin
1928 
        pat1_match_rise0_and_r <= #TCQ &pat1_match_rise0_r;
1929 
        pat1_match_fall0_and_r <= #TCQ &pat1_match_fall0_r;
1930 
        pat1_match_rise1_and_r <= #TCQ &pat1_match_rise1_r;
1931 
        pat1_match_fall1_and_r <= #TCQ &pat1_match_fall1_r;
1932 
        pat1_data_match_r <= #TCQ (pat1_match_rise0_and_r &&
1933 
                                   pat1_match_fall0_and_r &&
1934 
                                   pat1_match_rise1_and_r &&
1935 
                                   pat1_match_fall1_and_r);
1936 
      end
1937 
 
1938 
      assign pat_data_match_r = pat0_data_match_r | pat1_data_match_r;
1939 
 
1940 
    end
1941 
 
1942 
  endgenerate
1943 
 
1944 
 
1945 
  always @(posedge clk) begin
1946 
    rdlvl_stg1_start_r <= #TCQ rdlvl_stg1_start;
1947 
    mpr_rdlvl_done_r1  <= #TCQ mpr_rdlvl_done_r;
1948 
    mpr_rdlvl_done_r2  <= #TCQ mpr_rdlvl_done_r1;
1949 
    mpr_rdlvl_start_r  <= #TCQ mpr_rdlvl_start;
1950 
  end
1951 
 
1952 
  //***************************************************************************
1953 
  // First stage calibration: Capture clock
1954 
  //***************************************************************************
1955 
 
1956 
  //*****************************************************************
1957 
  // Keep track of how many samples have been written to shift registers
1958 
  // Every time RD_SHIFT_LEN samples have been written, then we have a
1959 
  // full read training pattern loaded into the sr_* registers. Then assert
1960 
  // sr_valid_r to indicate that: (1) comparison between the sr_* and
1961 
  // old_sr_* and prev_sr_* registers can take place, (2) transfer of
1962 
  // the contents of sr_* to old_sr_* and prev_sr_* registers can also
1963 
  // take place
1964 
  //*****************************************************************
1965 
// verilint STARC-2.2.3.3 off
1966 
  always @(posedge clk)
1967 
    if (rst || (mpr_rdlvl_done_r && ~rdlvl_stg1_start)) begin
1968 
      cnt_shift_r <= #TCQ 'b1;
1969 
      sr_valid_r  <= #TCQ 1'b0;
1970 
      mpr_valid_r <= #TCQ 1'b0;
1971 
    end else begin
1972 
      if (mux_rd_valid_r && mpr_rdlvl_start && ~mpr_rdlvl_done_r) begin
1973 
        if (cnt_shift_r == 'b0)
1974 
          mpr_valid_r <= #TCQ 1'b1;
1975 
        else begin
1976 
          mpr_valid_r <= #TCQ 1'b0;
1977 
          cnt_shift_r <= #TCQ cnt_shift_r + 1;
1978 
        end
1979 
      end else
1980 
        mpr_valid_r <= #TCQ 1'b0;
1981 
 
1982 
      if (mux_rd_valid_r && rdlvl_stg1_start) begin
1983 
        if (cnt_shift_r == RD_SHIFT_LEN-1) begin
1984 
          sr_valid_r <= #TCQ 1'b1;
1985 
          cnt_shift_r <= #TCQ 'b0;
1986 
        end else begin
1987 
          sr_valid_r <= #TCQ 1'b0;
1988 
          cnt_shift_r <= #TCQ cnt_shift_r + 1;
1989 
        end
1990 
      end else
1991 
        // When the current mux_rd_* contents are not valid, then
1992 
        // retain the current value of cnt_shift_r, and make sure
1993 
        // that sr_valid_r = 0 to prevent any downstream loads or
1994 
        // comparisons
1995 
        sr_valid_r <= #TCQ 1'b0;
1996 
    end
1997 
// verilint STARC-2.2.3.3 on
1998 
  //*****************************************************************
1999 
  // Logic to determine when either edge of the data eye encountered
2000 
  // Pre- and post-IDELAY update data pattern is compared, if they
2001 
  // differ, than an edge has been encountered. Currently no attempt
2002 
  // made to determine if the data pattern itself is "correct", only
2003 
  // whether it changes after incrementing the IDELAY (possible
2004 
  // future enhancement)
2005 
  //*****************************************************************
2006 
 
2007 
  // One-way control for ensuring that state machine request to store
2008 
  // current read data into OLD SR shift register only occurs on a
2009 
  // valid clock cycle. The FSM provides a one-cycle request pulse.
2010 
  // It is the responsibility of the FSM to wait the worst-case time
2011 
  // before relying on any downstream results of this load.
2012 
  always @(posedge clk)
2013 
    if (rst)
2014 
      store_sr_r      <= #TCQ 1'b0;
2015 
    else begin
2016 
      if (store_sr_req_r)
2017 
        store_sr_r <= #TCQ 1'b1;
2018 
      else if ((sr_valid_r || mpr_valid_r) && store_sr_r)
2019 
        store_sr_r <= #TCQ 1'b0;
2020 
    end
2021 
 
2022 
  // Transfer current data to old data, prior to incrementing delay
2023 
  // Also store data from current sampling window - so that we can detect
2024 
  // if the current delay tap yields data that is "jittery"
2025 
  generate
2026 
    if (nCK_PER_CLK == 4) begin: gen_old_sr_div4
2027 
    for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr
2028 
      always @(posedge clk) begin
2029 
        if (sr_valid_r || mpr_valid_r) begin
2030 
          // Load last sample (i.e. from current sampling interval)
2031 
          prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
2032 
          prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
2033 
          prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
2034 
          prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
2035 
          prev_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];
2036 
          prev_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];
2037 
          prev_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];
2038 
          prev_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];
2039 
        end
2040 
        if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin
2041 
          old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
2042 
          old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
2043 
          old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
2044 
          old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
2045 
          old_sr_rise2_r[z] <= #TCQ sr_rise2_r[z];
2046 
          old_sr_fall2_r[z] <= #TCQ sr_fall2_r[z];
2047 
          old_sr_rise3_r[z] <= #TCQ sr_rise3_r[z];
2048 
          old_sr_fall3_r[z] <= #TCQ sr_fall3_r[z];
2049 
        end
2050 
      end
2051 
    end
2052 
    end else if (nCK_PER_CLK == 2) begin: gen_old_sr_div2
2053 
      for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_old_sr
2054 
        always @(posedge clk) begin
2055 
          if (sr_valid_r || mpr_valid_r) begin
2056 
            prev_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
2057 
            prev_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
2058 
            prev_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
2059 
            prev_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
2060 
          end
2061 
          if ((sr_valid_r || mpr_valid_r) && store_sr_r) begin
2062 
            old_sr_rise0_r[z] <= #TCQ sr_rise0_r[z];
2063 
            old_sr_fall0_r[z] <= #TCQ sr_fall0_r[z];
2064 
            old_sr_rise1_r[z] <= #TCQ sr_rise1_r[z];
2065 
            old_sr_fall1_r[z] <= #TCQ sr_fall1_r[z];
2066 
          end
2067 
        end
2068 
      end
2069 
    end
2070 
  endgenerate
2071 
 
2072 
  //*******************************************************
2073 
  // Match determination occurs over 3 cycles - pipelined for better timing
2074 
  //*******************************************************
2075 
 
2076 
  // Match valid with # of cycles of pipelining in match determination
2077 
  always @(posedge clk) begin
2078 
    sr_valid_r1  <= #TCQ sr_valid_r;
2079 
    sr_valid_r2  <= #TCQ sr_valid_r1;
2080 
    mpr_valid_r1 <= #TCQ mpr_valid_r;
2081 
    mpr_valid_r2 <= #TCQ mpr_valid_r1;
2082 
  end
2083 
 
2084 
  generate
2085 
    if (nCK_PER_CLK == 4) begin: gen_sr_match_div4
2086 
    for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match
2087 
      always @(posedge clk) begin
2088 
        // CYCLE1: Compare all bits in DQS grp, generate separate term for
2089 
        //  each bit over four bit times. For example, if there are 8-bits
2090 
        //  per DQS group, 32 terms are generated on cycle 1
2091 
        // NOTE: Structure HDL such that X on data bus will result in a
2092 
        //  mismatch. This is required for memory models that can drive the
2093 
        //  bus with X's to model uncertainty regions (e.g. Denali)
2094 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z]))
2095 
          old_sr_match_rise0_r[z] <= #TCQ 1'b1;
2096 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2097 
          old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z];
2098 
        else
2099 
          old_sr_match_rise0_r[z] <= #TCQ 1'b0;
2100 
 
2101 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z]))
2102 
          old_sr_match_fall0_r[z] <= #TCQ 1'b1;
2103 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2104 
          old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z];
2105 
        else
2106 
          old_sr_match_fall0_r[z] <= #TCQ 1'b0;
2107 
 
2108 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z]))
2109 
          old_sr_match_rise1_r[z] <= #TCQ 1'b1;
2110 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2111 
          old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z];
2112 
        else
2113 
          old_sr_match_rise1_r[z] <= #TCQ 1'b0;
2114 
 
2115 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z]))
2116 
          old_sr_match_fall1_r[z] <= #TCQ 1'b1;
2117 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2118 
          old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z];
2119 
        else
2120 
          old_sr_match_fall1_r[z] <= #TCQ 1'b0;
2121 
 
2122 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == old_sr_rise2_r[z]))
2123 
          old_sr_match_rise2_r[z] <= #TCQ 1'b1;
2124 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2125 
          old_sr_match_rise2_r[z] <= #TCQ old_sr_match_rise2_r[z];
2126 
        else
2127 
          old_sr_match_rise2_r[z] <= #TCQ 1'b0;
2128 
 
2129 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == old_sr_fall2_r[z]))
2130 
          old_sr_match_fall2_r[z] <= #TCQ 1'b1;
2131 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2132 
          old_sr_match_fall2_r[z] <= #TCQ old_sr_match_fall2_r[z];
2133 
        else
2134 
          old_sr_match_fall2_r[z] <= #TCQ 1'b0;
2135 
 
2136 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == old_sr_rise3_r[z]))
2137 
          old_sr_match_rise3_r[z] <= #TCQ 1'b1;
2138 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2139 
          old_sr_match_rise3_r[z] <= #TCQ old_sr_match_rise3_r[z];
2140 
        else
2141 
          old_sr_match_rise3_r[z] <= #TCQ 1'b0;
2142 
 
2143 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == old_sr_fall3_r[z]))
2144 
          old_sr_match_fall3_r[z] <= #TCQ 1'b1;
2145 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2146 
          old_sr_match_fall3_r[z] <= #TCQ old_sr_match_fall3_r[z];
2147 
        else
2148 
          old_sr_match_fall3_r[z] <= #TCQ 1'b0;
2149 
 
2150 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z]))
2151 
          prev_sr_match_rise0_r[z] <= #TCQ 1'b1;
2152 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2153 
          prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z];
2154 
        else
2155 
          prev_sr_match_rise0_r[z] <= #TCQ 1'b0;
2156 
 
2157 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z]))
2158 
          prev_sr_match_fall0_r[z] <= #TCQ 1'b1;
2159 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2160 
          prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z];
2161 
        else
2162 
          prev_sr_match_fall0_r[z] <= #TCQ 1'b0;
2163 
 
2164 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z]))
2165 
          prev_sr_match_rise1_r[z] <= #TCQ 1'b1;
2166 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2167 
          prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z];
2168 
        else
2169 
          prev_sr_match_rise1_r[z] <= #TCQ 1'b0;
2170 
 
2171 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z]))
2172 
          prev_sr_match_fall1_r[z] <= #TCQ 1'b1;
2173 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2174 
          prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z];
2175 
        else
2176 
          prev_sr_match_fall1_r[z] <= #TCQ 1'b0;
2177 
 
2178 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_rise2_r[z] == prev_sr_rise2_r[z]))
2179 
          prev_sr_match_rise2_r[z] <= #TCQ 1'b1;
2180 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2181 
          prev_sr_match_rise2_r[z] <= #TCQ prev_sr_match_rise2_r[z];
2182 
        else
2183 
          prev_sr_match_rise2_r[z] <= #TCQ 1'b0;
2184 
 
2185 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_fall2_r[z] == prev_sr_fall2_r[z]))
2186 
          prev_sr_match_fall2_r[z] <= #TCQ 1'b1;
2187 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2188 
          prev_sr_match_fall2_r[z] <= #TCQ prev_sr_match_fall2_r[z];
2189 
        else
2190 
          prev_sr_match_fall2_r[z] <= #TCQ 1'b0;
2191 
 
2192 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_rise3_r[z] == prev_sr_rise3_r[z]))
2193 
          prev_sr_match_rise3_r[z] <= #TCQ 1'b1;
2194 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2195 
          prev_sr_match_rise3_r[z] <= #TCQ prev_sr_match_rise3_r[z];
2196 
        else
2197 
          prev_sr_match_rise3_r[z] <= #TCQ 1'b0;
2198 
 
2199 
        if ((pat_data_match_r || mpr_valid_r1) && (sr_fall3_r[z] == prev_sr_fall3_r[z]))
2200 
          prev_sr_match_fall3_r[z] <= #TCQ 1'b1;
2201 
        else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2202 
          prev_sr_match_fall3_r[z] <= #TCQ prev_sr_match_fall3_r[z];
2203 
        else
2204 
          prev_sr_match_fall3_r[z] <= #TCQ 1'b0;
2205 
 
2206 
        // CYCLE2: Combine all the comparisons for every 8 words (rise0,
2207 
        //  fall0,rise1, fall1) in the calibration sequence. Now we're down
2208 
        //  to DRAM_WIDTH terms
2209 
          old_sr_match_cyc2_r[z] <= #TCQ
2210 
                                    old_sr_match_rise0_r[z] &
2211 
                                  old_sr_match_fall0_r[z] &
2212 
                                  old_sr_match_rise1_r[z] &
2213 
                                  old_sr_match_fall1_r[z] &
2214 
                                  old_sr_match_rise2_r[z] &
2215 
                                  old_sr_match_fall2_r[z] &
2216 
                                  old_sr_match_rise3_r[z] &
2217 
                                  old_sr_match_fall3_r[z];
2218 
          prev_sr_match_cyc2_r[z] <= #TCQ
2219 
                                     prev_sr_match_rise0_r[z] &
2220 
                                   prev_sr_match_fall0_r[z] &
2221 
                                   prev_sr_match_rise1_r[z] &
2222 
                                   prev_sr_match_fall1_r[z] &
2223 
                                   prev_sr_match_rise2_r[z] &
2224 
                                   prev_sr_match_fall2_r[z] &
2225 
                                   prev_sr_match_rise3_r[z] &
2226 
                                   prev_sr_match_fall3_r[z];
2227 
 
2228 
        // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen),
2229 
        //  and qualify with pipelined valid signal) - probably don't need
2230 
        //  a cycle just do do this....
2231 
        if (sr_valid_r2 || mpr_valid_r2) begin
2232 
          old_sr_diff_r[z]  <= #TCQ ~old_sr_match_cyc2_r[z];
2233 
          prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z];
2234 
        end else begin
2235 
          old_sr_diff_r[z]  <= #TCQ 'b0;
2236 
          prev_sr_diff_r[z] <= #TCQ 'b0;
2237 
        end
2238 
        end
2239 
      end
2240 
    end if (nCK_PER_CLK == 2) begin: gen_sr_match_div2
2241 
      for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_sr_match
2242 
        always @(posedge clk) begin
2243 
          if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == old_sr_rise0_r[z]))
2244 
            old_sr_match_rise0_r[z] <= #TCQ 1'b1;
2245 
          else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2246 
            old_sr_match_rise0_r[z] <= #TCQ old_sr_match_rise0_r[z];
2247 
          else
2248 
            old_sr_match_rise0_r[z] <= #TCQ 1'b0;
2249 
 
2250 
          if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == old_sr_fall0_r[z]))
2251 
            old_sr_match_fall0_r[z] <= #TCQ 1'b1;
2252 
          else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2253 
            old_sr_match_fall0_r[z] <= #TCQ old_sr_match_fall0_r[z];
2254 
          else
2255 
            old_sr_match_fall0_r[z] <= #TCQ 1'b0;
2256 
 
2257 
          if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == old_sr_rise1_r[z]))
2258 
            old_sr_match_rise1_r[z] <= #TCQ 1'b1;
2259 
          else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2260 
            old_sr_match_rise1_r[z] <= #TCQ old_sr_match_rise1_r[z];
2261 
          else
2262 
            old_sr_match_rise1_r[z] <= #TCQ 1'b0;
2263 
 
2264 
          if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == old_sr_fall1_r[z]))
2265 
            old_sr_match_fall1_r[z] <= #TCQ 1'b1;
2266 
          else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2267 
            old_sr_match_fall1_r[z] <= #TCQ old_sr_match_fall1_r[z];
2268 
          else
2269 
            old_sr_match_fall1_r[z] <= #TCQ 1'b0;
2270 
 
2271 
          if ((pat_data_match_r || mpr_valid_r1) && (sr_rise0_r[z] == prev_sr_rise0_r[z]))
2272 
            prev_sr_match_rise0_r[z] <= #TCQ 1'b1;
2273 
          else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2274 
            prev_sr_match_rise0_r[z] <= #TCQ prev_sr_match_rise0_r[z];
2275 
          else
2276 
            prev_sr_match_rise0_r[z] <= #TCQ 1'b0;
2277 
 
2278 
          if ((pat_data_match_r || mpr_valid_r1) && (sr_fall0_r[z] == prev_sr_fall0_r[z]))
2279 
            prev_sr_match_fall0_r[z] <= #TCQ 1'b1;
2280 
          else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2281 
            prev_sr_match_fall0_r[z] <= #TCQ prev_sr_match_fall0_r[z];
2282 
          else
2283 
            prev_sr_match_fall0_r[z] <= #TCQ 1'b0;
2284 
 
2285 
          if ((pat_data_match_r || mpr_valid_r1) && (sr_rise1_r[z] == prev_sr_rise1_r[z]))
2286 
            prev_sr_match_rise1_r[z] <= #TCQ 1'b1;
2287 
          else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2288 
            prev_sr_match_rise1_r[z] <= #TCQ prev_sr_match_rise1_r[z];
2289 
          else
2290 
            prev_sr_match_rise1_r[z] <= #TCQ 1'b0;
2291 
 
2292 
          if ((pat_data_match_r || mpr_valid_r1) && (sr_fall1_r[z] == prev_sr_fall1_r[z]))
2293 
            prev_sr_match_fall1_r[z] <= #TCQ 1'b1;
2294 
          else if (~mpr_valid_r1 && mpr_rdlvl_start && ~mpr_rdlvl_done_r)
2295 
            prev_sr_match_fall1_r[z] <= #TCQ prev_sr_match_fall1_r[z];
2296 
          else
2297 
            prev_sr_match_fall1_r[z] <= #TCQ 1'b0;
2298 
 
2299 
          old_sr_match_cyc2_r[z] <= #TCQ
2300 
                                    old_sr_match_rise0_r[z] &
2301 
                                    old_sr_match_fall0_r[z] &
2302 
                                    old_sr_match_rise1_r[z] &
2303 
                                    old_sr_match_fall1_r[z];
2304 
          prev_sr_match_cyc2_r[z] <= #TCQ
2305 
                                     prev_sr_match_rise0_r[z] &
2306 
                                     prev_sr_match_fall0_r[z] &
2307 
                                     prev_sr_match_rise1_r[z] &
2308 
                                     prev_sr_match_fall1_r[z];
2309 
 
2310 
          // CYCLE3: Invert value (i.e. assert when DIFFERENCE in value seen),
2311 
          //  and qualify with pipelined valid signal) - probably don't need
2312 
          //  a cycle just do do this....
2313 
          if (sr_valid_r2 || mpr_valid_r2) begin
2314 
            old_sr_diff_r[z]  <= #TCQ ~old_sr_match_cyc2_r[z];
2315 
            prev_sr_diff_r[z] <= #TCQ ~prev_sr_match_cyc2_r[z];
2316 
          end else begin
2317 
            old_sr_diff_r[z]  <= #TCQ 'b0;
2318 
            prev_sr_diff_r[z] <= #TCQ 'b0;
2319 
          end
2320 
        end
2321 
     end
2322 
    end
2323 
  endgenerate
2324 
 
2325 
  //***************************************************************************
2326 
  // First stage calibration: DQS Capture
2327 
  //***************************************************************************
2328 
 
2329 
 
2330 
  //*******************************************************
2331 
  // Counters for tracking # of samples compared
2332 
  // For each comparision point (i.e. to determine if an edge has
2333 
  // occurred after each IODELAY increment when read leveling),
2334 
  // multiple samples are compared in order to average out the effects
2335 
  // of jitter. If any one of these samples is different than the "old"
2336 
  // sample corresponding to the previous IODELAY value, then an edge
2337 
  // is declared to be detected.
2338 
  //*******************************************************
2339 
 
2340 
  // Two cascaded counters are used to keep track of # of samples compared,
2341 
  // in order to make it easier to meeting timing on these paths. Once
2342 
  // optimal sampling interval is determined, it may be possible to remove
2343 
  // the second counter
2344 
  always @(posedge clk)
2345 
    samp_edge_cnt0_en_r <= #TCQ
2346 
                          (cal1_state_r == CAL1_PAT_DETECT) ||
2347 
                          (cal1_state_r == CAL1_DETECT_EDGE) ||
2348 
                          (cal1_state_r == CAL1_PB_DETECT_EDGE) ||
2349 
                          (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ);
2350 
 
2351 
  // First counter counts # of samples compared
2352 
  always @(posedge clk)
2353 
    if (rst)
2354 
      samp_edge_cnt0_r <= #TCQ 'b0;
2355 
    else begin
2356 
      if (!samp_edge_cnt0_en_r)
2357 
        // Reset sample counter when not in any of the "sampling" states
2358 
        samp_edge_cnt0_r <= #TCQ 'b0;
2359 
      else if (sr_valid_r2 || mpr_valid_r2)
2360 
        // Otherwise, count # of samples compared
2361 
        samp_edge_cnt0_r <= #TCQ samp_edge_cnt0_r + 1;
2362 
    end
2363 
 
2364 
  // Counter #2 enable generation
2365 
  always @(posedge clk)
2366 
    if (rst)
2367 
      samp_edge_cnt1_en_r <= #TCQ 1'b0;
2368 
    else begin
2369 
      // Assert pulse when correct number of samples compared
2370 
      if ((samp_edge_cnt0_r == DETECT_EDGE_SAMPLE_CNT0) &&
2371 
          (sr_valid_r2 || mpr_valid_r2))
2372 
        samp_edge_cnt1_en_r <= #TCQ 1'b1;
2373 
      else
2374 
        samp_edge_cnt1_en_r <= #TCQ 1'b0;
2375 
    end
2376 
 
2377 
  // Counter #2
2378 
  always @(posedge clk)
2379 
    if (rst)
2380 
      samp_edge_cnt1_r <= #TCQ 'b0;
2381 
    else
2382 
      if (!samp_edge_cnt0_en_r)
2383 
        samp_edge_cnt1_r <= #TCQ 'b0;
2384 
      else if (samp_edge_cnt1_en_r)
2385 
        samp_edge_cnt1_r <= #TCQ samp_edge_cnt1_r + 1;
2386 
 
2387 
  always @(posedge clk)
2388 
    if (rst)
2389 
      samp_cnt_done_r <= #TCQ 1'b0;
2390 
    else begin
2391 
      if (!samp_edge_cnt0_en_r)
2392 
        samp_cnt_done_r <= #TCQ 'b0;
2393 
      else if ((SIM_CAL_OPTION == "FAST_CAL") ||
2394 
               (SIM_CAL_OPTION == "FAST_WIN_DETECT")) begin
2395 
        if (samp_edge_cnt0_r == SR_VALID_DELAY-1)
2396 
          // For simulation only, stay in edge detection mode a minimum
2397 
          // amount of time - just enough for two data compares to finish
2398 
          samp_cnt_done_r <= #TCQ 1'b1;
2399 
      end else begin
2400 
        if (samp_edge_cnt1_r == DETECT_EDGE_SAMPLE_CNT1)
2401 
          samp_cnt_done_r <= #TCQ 1'b1;
2402 
      end
2403 
    end
2404 
 
2405 
  //*****************************************************************
2406 
  // Logic to keep track of (on per-bit basis):
2407 
  //  1. When a region of stability preceded by a known edge occurs
2408 
  //  2. If for the current tap, the read data jitters
2409 
  //  3. If an edge occured between the current and previous tap
2410 
  //  4. When the current edge detection/sampling interval can end
2411 
  // Essentially, these are a series of status bits - the stage 1
2412 
  // calibration FSM monitors these to determine when an edge is
2413 
  // found. Additional information is provided to help the FSM
2414 
  // determine if a left or right edge has been found.
2415 
  //****************************************************************
2416 
 
2417 
  assign pb_detect_edge_setup
2418 
    = (cal1_state_r == CAL1_STORE_FIRST_WAIT) ||
2419 
      (cal1_state_r == CAL1_PB_STORE_FIRST_WAIT) ||
2420 
      (cal1_state_r == CAL1_PB_DEC_CPT_LEFT_WAIT);
2421 
 
2422 
  assign pb_detect_edge
2423 
    = (cal1_state_r == CAL1_PAT_DETECT) ||
2424 
      (cal1_state_r == CAL1_DETECT_EDGE) ||
2425 
      (cal1_state_r == CAL1_PB_DETECT_EDGE) ||
2426 
      (cal1_state_r == CAL1_PB_DETECT_EDGE_DQ);
2427 
 
2428 
  generate
2429 
    for (z = 0; z < DRAM_WIDTH; z = z + 1) begin: gen_track_left_edge
2430 
      always @(posedge clk) begin
2431 
        if (pb_detect_edge_setup) begin
2432 
          // Reset eye size, stable eye marker, and jitter marker before
2433 
          // starting new edge detection iteration
2434 
          pb_cnt_eye_size_r[z]     <= #TCQ 5'd0;
2435 
          pb_detect_edge_done_r[z] <= #TCQ 1'b0;
2436 
          pb_found_stable_eye_r[z] <= #TCQ 1'b0;
2437 
          pb_last_tap_jitter_r[z]  <= #TCQ 1'b0;
2438 
          pb_found_edge_last_r[z]  <= #TCQ 1'b0;
2439 
          pb_found_edge_r[z]       <= #TCQ 1'b0;
2440 
          pb_found_first_edge_r[z] <= #TCQ 1'b0;
2441 
        end else if (pb_detect_edge) begin
2442 
          // Save information on which DQ bits are already out of the
2443 
          // data valid window - those DQ bits will later not have their
2444 
          // IDELAY tap value incremented
2445 
          pb_found_edge_last_r[z] <= #TCQ pb_found_edge_r[z];
2446 
 
2447 
          if (!pb_detect_edge_done_r[z]) begin
2448 
            if (samp_cnt_done_r) begin
2449 
              // If we've reached end of sampling interval, no jitter on
2450 
              // current tap has been found (although an edge could have
2451 
              // been found between the current and previous taps), and
2452 
              // the sampling interval is complete. Increment the stable
2453 
              // eye counter if no edge found, and always clear the jitter
2454 
              // flag in preparation for the next tap.
2455 
              pb_last_tap_jitter_r[z]  <= #TCQ 1'b0;
2456 
              pb_detect_edge_done_r[z] <= #TCQ 1'b1;
2457 
              if (!pb_found_edge_r[z] && !pb_last_tap_jitter_r[z]) begin
2458 
                // If the data was completely stable during this tap and
2459 
                // no edge was found between this and the previous tap
2460 
                // then increment the stable eye counter "as appropriate"
2461 
                if (pb_cnt_eye_size_r[z] != MIN_EYE_SIZE-1)
2462 
                  pb_cnt_eye_size_r[z] <= #TCQ pb_cnt_eye_size_r[z] + 1;
2463 
                else //if (pb_found_first_edge_r[z])
2464 
                  // We've reached minimum stable eye width
2465 
                  pb_found_stable_eye_r[z] <= #TCQ 1'b1;
2466 
              end else begin
2467 
                // Otherwise, an edge was found, either because of a
2468 
                // difference between this and the previous tap's read
2469 
                // data, and/or because the previous tap's data jittered
2470 
                // (but not the current tap's data), then just set the
2471 
                // edge found flag, and enable the stable eye counter
2472 
                pb_cnt_eye_size_r[z]     <= #TCQ 5'd0;
2473 
                pb_found_stable_eye_r[z] <= #TCQ 1'b0;
2474 
                pb_found_edge_r[z]       <= #TCQ 1'b1;
2475 
                pb_detect_edge_done_r[z] <= #TCQ 1'b1;
2476 
              end
2477 
            end else if (prev_sr_diff_r[z]) begin
2478 
              // If we find that the current tap read data jitters, then
2479 
              // set edge and jitter found flags, "enable" the eye size
2480 
              // counter, and stop sampling interval for this bit
2481 
              pb_cnt_eye_size_r[z]     <= #TCQ 5'd0;
2482 
              pb_found_stable_eye_r[z] <= #TCQ 1'b0;
2483 
              pb_last_tap_jitter_r[z]  <= #TCQ 1'b1;
2484 
              pb_found_edge_r[z]       <= #TCQ 1'b1;
2485 
              pb_found_first_edge_r[z] <= #TCQ 1'b1;
2486 
              pb_detect_edge_done_r[z] <= #TCQ 1'b1;
2487 
            end else if (old_sr_diff_r[z] || pb_last_tap_jitter_r[z]) begin
2488 
              // If either an edge was found (i.e. difference between
2489 
              // current tap and previous tap read data), or the previous
2490 
              // tap exhibited jitter (which means by definition that the
2491 
              // current tap cannot match the previous tap because the
2492 
              // previous tap gave unstable data), then set the edge found
2493 
              // flag, and "enable" eye size counter. But do not stop
2494 
              // sampling interval - we still need to check if the current
2495 
              // tap exhibits jitter
2496 
              pb_cnt_eye_size_r[z]     <= #TCQ 5'd0;
2497 
              pb_found_stable_eye_r[z] <= #TCQ 1'b0;
2498 
              pb_found_edge_r[z]       <= #TCQ 1'b1;
2499 
              pb_found_first_edge_r[z] <= #TCQ 1'b1;
2500 
            end
2501 
          end
2502 
        end else begin
2503 
          // Before every edge detection interval, reset "intra-tap" flags
2504 
          pb_found_edge_r[z]       <= #TCQ 1'b0;
2505 
          pb_detect_edge_done_r[z] <= #TCQ 1'b0;
2506 
        end
2507 
      end
2508 
    end
2509 
  endgenerate
2510 
 
2511 
  // Combine the above per-bit status flags into combined terms when
2512 
  // performing deskew on the aggregate data window
2513 
  always @(posedge clk) begin
2514 
    detect_edge_done_r <= #TCQ &pb_detect_edge_done_r;
2515 
    found_edge_r       <= #TCQ |pb_found_edge_r;
2516 
    found_edge_all_r   <= #TCQ &pb_found_edge_r;
2517 
    found_stable_eye_r <= #TCQ &pb_found_stable_eye_r;
2518 
  end
2519 
 
2520 
  // last IODELAY "stable eye" indicator is updated only after
2521 
  // detect_edge_done_r is asserted - so that when we do find the "right edge"
2522 
  // of the data valid window, found_edge_r = 1, AND found_stable_eye_r = 1
2523 
  // when detect_edge_done_r = 1 (otherwise, if found_stable_eye_r updates
2524 
  // immediately, then it never possible to have found_stable_eye_r = 1
2525 
  // when we detect an edge - and we'll never know whether we've found
2526 
  // a "right edge")
2527 
  always @(posedge clk)
2528 
    if (pb_detect_edge_setup)
2529 
      found_stable_eye_last_r <= #TCQ 1'b0;
2530 
    else if (detect_edge_done_r)
2531 
      found_stable_eye_last_r <= #TCQ found_stable_eye_r;
2532 
 
2533 
  //*****************************************************************
2534 
  // Keep track of DQ IDELAYE2 taps used
2535 
  //*****************************************************************
2536 
 
2537 
  // Added additional register stage to improve timing
2538 
  always @(posedge clk)
2539 
    if (rst)
2540 
      idelay_tap_cnt_slice_r <= 5'h0;
2541 
    else
2542 
      idelay_tap_cnt_slice_r <= idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing];
2543 
 
2544 
  always @(posedge clk)
2545 
    if (rst || (SIM_CAL_OPTION == "SKIP_CAL")) begin //|| new_cnt_cpt_r
2546 
      for (s = 0; s < RANKS; s = s + 1) begin
2547 
        for (t = 0; t < DQS_WIDTH; t = t + 1) begin
2548 
          idelay_tap_cnt_r[s][t] <= #TCQ idelaye2_init_val;
2549 
        end
2550 
      end
2551 
    end else if (SIM_CAL_OPTION == "FAST_CAL") begin
2552 
      for (u = 0; u < RANKS; u = u + 1) begin
2553 
        for (w = 0; w < DQS_WIDTH; w = w + 1) begin
2554 
          if (cal1_dq_idel_ce) begin
2555 
            if (cal1_dq_idel_inc)
2556 
              idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] + 1;
2557 
            else
2558 
              idelay_tap_cnt_r[u][w] <= #TCQ idelay_tap_cnt_r[u][w] - 1;
2559 
          end
2560 
        end
2561 
      end
2562 
    end else if ((rnk_cnt_r == RANKS-1) && (RANKS == 2) &&
2563 
                    rdlvl_rank_done_r && (cal1_state_r == CAL1_IDLE)) begin
2564 
      for (f = 0; f < DQS_WIDTH; f = f + 1) begin
2565 
        idelay_tap_cnt_r[rnk_cnt_r][f] <= #TCQ idelay_tap_cnt_r[(rnk_cnt_r-1)][f];
2566 
      end
2567 
    end else if (cal1_dq_idel_ce) begin
2568 
      if (cal1_dq_idel_inc)
2569 
        idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r + 5'h1;
2570 
      else
2571 
        idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing] <= #TCQ idelay_tap_cnt_slice_r - 5'h1;
2572 
    end else if (idelay_ld)
2573 
      idelay_tap_cnt_r[0][wrcal_cnt] <= #TCQ 5'b00000;
2574 
 
2575 
  always @(posedge clk)
2576 
    if (rst || new_cnt_cpt_r)
2577 
      idelay_tap_limit_r <= #TCQ 1'b0;
2578 
    else if (idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_r] == 'd31)
2579 
      idelay_tap_limit_r <= #TCQ 1'b1;
2580 
 
2581 
  //*****************************************************************
2582 
  // keep track of edge tap counts found, and current capture clock
2583 
  // tap count
2584 
  //*****************************************************************
2585 
 
2586 
  always @(posedge clk)
2587 
    if (rst || new_cnt_cpt_r ||
2588 
        (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
2589 
      tap_cnt_cpt_r   <= #TCQ 'b0;
2590 
    else if (cal1_dlyce_cpt_r) begin
2591 
      if (cal1_dlyinc_cpt_r)
2592 
        tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r + 1;
2593 
      else if (tap_cnt_cpt_r != 'd0)
2594 
        tap_cnt_cpt_r <= #TCQ tap_cnt_cpt_r - 1;
2595 
    end
2596 
 
2597 
  always @(posedge clk)
2598 
    if (rst || new_cnt_cpt_r ||
2599 
       (cal1_state_r1 == CAL1_DQ_IDEL_TAP_INC) ||
2600 
       (mpr_rdlvl_done_r1 && ~mpr_rdlvl_done_r2))
2601 
      tap_limit_cpt_r <= #TCQ 1'b0;
2602 
    else if (tap_cnt_cpt_r == 6'd63)
2603 
      tap_limit_cpt_r <= #TCQ 1'b1;
2604 
 
2605 
   always @(posedge clk)
2606 
     cal1_cnt_cpt_timing_r <= #TCQ cal1_cnt_cpt_r;
2607 
 
2608 
   assign cal1_cnt_cpt_timing = {2'b00, cal1_cnt_cpt_r};
2609 
 
2610 
   // Storing DQS tap values at the end of each DQS read leveling
2611 
   always @(posedge clk) begin
2612 
     if (rst) begin
2613 
       for (a = 0; a < RANKS; a = a + 1) begin: rst_rdlvl_dqs_tap_count_loop
2614 
         for (b = 0; b < DQS_WIDTH; b = b + 1)
2615 
           rdlvl_dqs_tap_cnt_r[a][b] <= #TCQ 'b0;
2616 
       end
2617 
     end else if ((SIM_CAL_OPTION == "FAST_CAL") & (cal1_state_r1 == CAL1_NEXT_DQS)) begin
2618 
       for (p = 0; p < RANKS; p = p +1) begin: rdlvl_dqs_tap_rank_cnt
2619 
         for(q = 0; q < DQS_WIDTH; q = q +1) begin: rdlvl_dqs_tap_cnt
2620 
           rdlvl_dqs_tap_cnt_r[p][q] <= #TCQ tap_cnt_cpt_r;
2621 
         end
2622 
       end
2623 
     end else if (SIM_CAL_OPTION == "SKIP_CAL") begin
2624 
       for (j = 0; j < RANKS; j = j +1) begin: rdlvl_dqs_tap_rnk_cnt
2625 
         for(i = 0; i < DQS_WIDTH; i = i +1) begin: rdlvl_dqs_cnt
2626 
           rdlvl_dqs_tap_cnt_r[j][i] <= #TCQ 6'd31;
2627 
         end
2628 
       end
2629 
     end else if (cal1_state_r1 == CAL1_NEXT_DQS) begin
2630 
       rdlvl_dqs_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing_r] <= #TCQ tap_cnt_cpt_r;
2631 
     end
2632 
   end
2633 
 
2634 
 
2635 
  // Counter to track maximum DQ IODELAY tap usage during the per-bit
2636 
  // deskew portion of stage 1 calibration
2637 
  always @(posedge clk)
2638 
    if (rst) begin
2639 
      idel_tap_cnt_dq_pb_r   <= #TCQ 'b0;
2640 
      idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
2641 
    end else
2642 
      if (new_cnt_cpt_r) begin
2643 
        idel_tap_cnt_dq_pb_r   <= #TCQ 'b0;
2644 
        idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
2645 
      end else if (|cal1_dlyce_dq_r) begin
2646 
        if (cal1_dlyinc_dq_r)
2647 
          idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r + 1;
2648 
        else
2649 
          idel_tap_cnt_dq_pb_r <= #TCQ idel_tap_cnt_dq_pb_r - 1;
2650 
 
2651 
        if (idel_tap_cnt_dq_pb_r == 31)
2652 
          idel_tap_limit_dq_pb_r <= #TCQ 1'b1;
2653 
        else
2654 
          idel_tap_limit_dq_pb_r <= #TCQ 1'b0;
2655 
      end
2656 
 
2657 
 
2658 
  //*****************************************************************
2659 
 
2660 
  always @(posedge clk)
2661 
    cal1_state_r1 <= #TCQ cal1_state_r;
2662 
 
2663 
  always @(posedge clk)
2664 
    if (rst) begin
2665 
      cal1_cnt_cpt_r        <= #TCQ 'b0;
2666 
      cal1_dlyce_cpt_r      <= #TCQ 1'b0;
2667 
      cal1_dlyinc_cpt_r     <= #TCQ 1'b0;
2668 
      cal1_dq_idel_ce       <= #TCQ 1'b0;
2669 
      cal1_dq_idel_inc      <= #TCQ 1'b0;
2670 
      cal1_prech_req_r      <= #TCQ 1'b0;
2671 
      cal1_state_r          <= #TCQ CAL1_IDLE;
2672 
      cnt_idel_dec_cpt_r    <= #TCQ 6'bxxxxxx;
2673 
      found_first_edge_r    <= #TCQ 1'b0;
2674 
      found_second_edge_r   <= #TCQ 1'b0;
2675 
      right_edge_taps_r     <= #TCQ 6'bxxxxxx;
2676 
      first_edge_taps_r     <= #TCQ 6'bxxxxxx;
2677 
      new_cnt_cpt_r         <= #TCQ 1'b0;
2678 
      rdlvl_stg1_done       <= #TCQ 1'b0;
2679 
      rdlvl_stg1_err        <= #TCQ 1'b0;
2680 
      second_edge_taps_r    <= #TCQ 6'bxxxxxx;
2681 
      store_sr_req_pulsed_r <= #TCQ 1'b0;
2682 
      store_sr_req_r        <= #TCQ 1'b0;
2683 
      rnk_cnt_r             <= #TCQ 2'b00;
2684 
      rdlvl_rank_done_r     <= #TCQ 1'b0;
2685 
      idel_dec_cnt          <= #TCQ 'd0;
2686 
      rdlvl_last_byte_done  <= #TCQ 1'b0;
2687 
      idel_pat_detect_valid_r <= #TCQ 1'b0;
2688 
      mpr_rank_done_r       <= #TCQ 1'b0;
2689 
      mpr_last_byte_done    <= #TCQ 1'b0;
2690 
      idel_adj_inc          <= #TCQ 1'b0;
2691 
      if (OCAL_EN == "ON")
2692 
        mpr_rdlvl_done_r      <= #TCQ 1'b0;
2693 
      else
2694 
        mpr_rdlvl_done_r      <= #TCQ 1'b1;
2695 
      mpr_dec_cpt_r         <= #TCQ 1'b0;
2696 
    end else begin
2697 
      // default (inactive) states for all "pulse" outputs
2698 
                        // verilint STARC-2.2.3.3 off
2699 
      cal1_prech_req_r    <= #TCQ 1'b0;
2700 
      cal1_dlyce_cpt_r    <= #TCQ 1'b0;
2701 
      cal1_dlyinc_cpt_r   <= #TCQ 1'b0;
2702 
      cal1_dq_idel_ce     <= #TCQ 1'b0;
2703 
      cal1_dq_idel_inc    <= #TCQ 1'b0;
2704 
      new_cnt_cpt_r       <= #TCQ 1'b0;
2705 
      store_sr_req_pulsed_r <= #TCQ 1'b0;
2706 
      store_sr_req_r      <= #TCQ 1'b0;
2707 
 
2708 
      case (cal1_state_r)
2709 
 
2710 
        CAL1_IDLE: begin
2711 
          rdlvl_rank_done_r    <= #TCQ 1'b0;
2712 
          rdlvl_last_byte_done <= #TCQ 1'b0;
2713 
          mpr_rank_done_r      <= #TCQ 1'b0;
2714 
          mpr_last_byte_done   <= #TCQ 1'b0;
2715 
          if (mpr_rdlvl_start && ~mpr_rdlvl_start_r) begin
2716 
              cal1_state_r  <= #TCQ CAL1_MPR_NEW_DQS_WAIT;
2717 
          end else
2718 
          if (rdlvl_stg1_start && ~rdlvl_stg1_start_r) begin
2719 
            if (SIM_CAL_OPTION == "SKIP_CAL")
2720 
              cal1_state_r  <= #TCQ CAL1_REGL_LOAD;
2721 
            else if (SIM_CAL_OPTION == "FAST_CAL")
2722 
              cal1_state_r  <= #TCQ CAL1_NEXT_DQS;
2723 
            else begin
2724 
              new_cnt_cpt_r <= #TCQ 1'b1;
2725 
              cal1_state_r  <= #TCQ CAL1_NEW_DQS_WAIT;
2726 
            end
2727 
          end
2728 
        end
2729 
 
2730 
        CAL1_MPR_NEW_DQS_WAIT: begin
2731 
          cal1_prech_req_r  <= #TCQ 1'b0;
2732 
          if (!cal1_wait_r && mpr_valid_r)
2733 
            cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;
2734 
        end
2735 
 
2736 
        // Wait for the new DQS group to change
2737 
        // also gives time for the read data IN_FIFO to
2738 
        // output the updated data for the new DQS group
2739 
        CAL1_NEW_DQS_WAIT: begin
2740 
          rdlvl_rank_done_r    <= #TCQ 1'b0;
2741 
          rdlvl_last_byte_done <= #TCQ 1'b0;
2742 
          mpr_rank_done_r      <= #TCQ 1'b0;
2743 
          mpr_last_byte_done   <= #TCQ 1'b0;
2744 
          cal1_prech_req_r     <= #TCQ 1'b0;
2745 
          if (|pi_counter_read_val) begin //VK_REVIEW
2746 
            mpr_dec_cpt_r      <= #TCQ 1'b1;
2747 
            cal1_state_r       <= #TCQ CAL1_IDEL_DEC_CPT;
2748 
            cnt_idel_dec_cpt_r <= #TCQ pi_counter_read_val;
2749 
          end else if (!cal1_wait_r) begin
2750 
          //if (!cal1_wait_r) begin
2751 
            // Store "previous tap" read data. Technically there is no
2752 
            // "previous" read data, since we are starting a new DQS
2753 
            // group, so we'll never find an edge at tap 0 unless the
2754 
            // data is fluctuating/jittering
2755 
            store_sr_req_r <= #TCQ 1'b1;
2756 
            // If per-bit deskew is disabled, then skip the first
2757 
            // portion of stage 1 calibration
2758 
            if (PER_BIT_DESKEW == "OFF")
2759 
              cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
2760 
            else if (PER_BIT_DESKEW == "ON")
2761 
              cal1_state_r <= #TCQ CAL1_PB_STORE_FIRST_WAIT;
2762 
          end
2763 
        end
2764 
        //*****************************************************************
2765 
        // Per-bit deskew states
2766 
        //*****************************************************************
2767 
 
2768 
        // Wait state following storage of initial read data
2769 
        CAL1_PB_STORE_FIRST_WAIT:
2770 
          if (!cal1_wait_r)
2771 
            cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;
2772 
 
2773 
        // Look for an edge on all DQ bits in current DQS group
2774 
        CAL1_PB_DETECT_EDGE:
2775 
          if (detect_edge_done_r) begin
2776 
            if (found_stable_eye_r) begin
2777 
              // If we've found the left edge for all bits (or more precisely,
2778 
              // we've found the left edge, and then part of the stable
2779 
              // window thereafter), then proceed to positioning the CPT clock
2780 
              // right before the left margin
2781 
              cnt_idel_dec_cpt_r <= #TCQ MIN_EYE_SIZE + 1;
2782 
              cal1_state_r       <= #TCQ CAL1_PB_DEC_CPT_LEFT;
2783 
            end else begin
2784 
              // If we've reached the end of the sampling time, and haven't
2785 
              // yet found the left margin of all the DQ bits, then:
2786 
              if (!tap_limit_cpt_r) begin
2787 
                // If we still have taps left to use, then store current value
2788 
                // of read data, increment the capture clock, and continue to
2789 
                // look for (left) edges
2790 
                store_sr_req_r <= #TCQ 1'b1;
2791 
                cal1_state_r    <= #TCQ CAL1_PB_INC_CPT;
2792 
              end else begin
2793 
                // If we ran out of taps moving the capture clock, and we
2794 
                // haven't finished edge detection, then reset the capture
2795 
                // clock taps to 0 (gradually, one tap at a time...
2796 
                // then exit the per-bit portion of the algorithm -
2797 
                // i.e. proceed to adjust the capture clock and DQ IODELAYs as
2798 
                cnt_idel_dec_cpt_r <= #TCQ 6'd63;
2799 
                cal1_state_r       <= #TCQ CAL1_PB_DEC_CPT;
2800 
              end
2801 
            end
2802 
          end
2803 
 
2804 
        // Increment delay for DQS
2805 
        CAL1_PB_INC_CPT: begin
2806 
          cal1_dlyce_cpt_r  <= #TCQ 1'b1;
2807 
          cal1_dlyinc_cpt_r <= #TCQ 1'b1;
2808 
          cal1_state_r      <= #TCQ CAL1_PB_INC_CPT_WAIT;
2809 
        end
2810 
 
2811 
        // Wait for IODELAY for both capture and internal nodes within
2812 
        // ISERDES to settle, before checking again for an edge
2813 
        CAL1_PB_INC_CPT_WAIT: begin
2814 
          cal1_dlyce_cpt_r  <= #TCQ 1'b0;
2815 
          cal1_dlyinc_cpt_r <= #TCQ 1'b0;
2816 
          if (!cal1_wait_r)
2817 
            cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE;
2818 
        end
2819 
        // We've found the left edges of the windows for all DQ bits
2820 
        // (actually, we found it MIN_EYE_SIZE taps ago) Decrement capture
2821 
        // clock IDELAY to position just outside left edge of data window
2822 
        CAL1_PB_DEC_CPT_LEFT:
2823 
          if (cnt_idel_dec_cpt_r == 6'b000000)
2824 
            cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_LEFT_WAIT;
2825 
          else begin
2826 
            cal1_dlyce_cpt_r   <= #TCQ 1'b1;
2827 
            cal1_dlyinc_cpt_r  <= #TCQ 1'b0;
2828 
            cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
2829 
          end
2830 
 
2831 
        CAL1_PB_DEC_CPT_LEFT_WAIT:
2832 
          if (!cal1_wait_r)
2833 
            cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;
2834 
 
2835 
        // If there is skew between individual DQ bits, then after we've
2836 
        // positioned the CPT clock, we will be "in the window" for some
2837 
        // DQ bits ("early" DQ bits), and "out of the window" for others
2838 
        // ("late" DQ bits). Increase DQ taps until we are out of the
2839 
        // window for all DQ bits
2840 
        CAL1_PB_DETECT_EDGE_DQ:
2841 
          if (detect_edge_done_r)
2842 
            if (found_edge_all_r) begin
2843 
              // We're out of the window for all DQ bits in this DQS group
2844 
              // We're done with per-bit deskew for this group - now decr
2845 
              // capture clock IODELAY tap count back to 0, and proceed
2846 
              // with the rest of stage 1 calibration for this DQS group
2847 
              cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;
2848 
              cal1_state_r       <= #TCQ CAL1_PB_DEC_CPT;
2849 
            end else
2850 
              if (!idel_tap_limit_dq_pb_r)
2851 
                // If we still have DQ taps available for deskew, keep
2852 
                // incrementing IODELAY tap count for the appropriate DQ bits
2853 
                cal1_state_r <= #TCQ CAL1_PB_INC_DQ;
2854 
              else begin
2855 
                // Otherwise, stop immediately (we've done the best we can)
2856 
                // and proceed with rest of stage 1 calibration
2857 
                cnt_idel_dec_cpt_r <= #TCQ tap_cnt_cpt_r;
2858 
                cal1_state_r <= #TCQ CAL1_PB_DEC_CPT;
2859 
              end
2860 
 
2861 
        CAL1_PB_INC_DQ: begin
2862 
          // Increment only those DQ for which an edge hasn't been found yet
2863 
          cal1_dlyce_dq_r  <= #TCQ ~pb_found_edge_last_r;
2864 
          cal1_dlyinc_dq_r <= #TCQ 1'b1;
2865 
          cal1_state_r     <= #TCQ CAL1_PB_INC_DQ_WAIT;
2866 
        end
2867 
 
2868 
        CAL1_PB_INC_DQ_WAIT:
2869 
          if (!cal1_wait_r)
2870 
            cal1_state_r <= #TCQ CAL1_PB_DETECT_EDGE_DQ;
2871 
 
2872 
        // Decrement capture clock taps back to initial value
2873 
        CAL1_PB_DEC_CPT:
2874 
          if (cnt_idel_dec_cpt_r == 6'b000000)
2875 
            cal1_state_r <= #TCQ CAL1_PB_DEC_CPT_WAIT;
2876 
          else begin
2877 
            cal1_dlyce_cpt_r   <= #TCQ 1'b1;
2878 
            cal1_dlyinc_cpt_r  <= #TCQ 1'b0;
2879 
            cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
2880 
          end
2881 
 
2882 
        // Wait for capture clock to settle, then proceed to rest of
2883 
        // state 1 calibration for this DQS group
2884 
        CAL1_PB_DEC_CPT_WAIT:
2885 
          if (!cal1_wait_r) begin
2886 
            store_sr_req_r <= #TCQ 1'b1;
2887 
            cal1_state_r    <= #TCQ CAL1_STORE_FIRST_WAIT;
2888 
          end
2889 
 
2890 
        // When first starting calibration for a DQS group, save the
2891 
        // current value of the read data shift register, and use this
2892 
        // as a reference. Note that for the first iteration of the
2893 
        // edge detection loop, we will in effect be checking for an edge
2894 
        // at IODELAY taps = 0 - normally, we are comparing the read data
2895 
        // for IODELAY taps = N, with the read data for IODELAY taps = N-1
2896 
        // An edge can only be found at IODELAY taps = 0 if the read data
2897 
        // is changing during this time (possible due to jitter)
2898 
        CAL1_STORE_FIRST_WAIT: begin
2899 
          mpr_dec_cpt_r  <= #TCQ 1'b0;
2900 
          if (!cal1_wait_r)
2901 
            cal1_state_r <= #TCQ CAL1_PAT_DETECT;
2902 
        end
2903 
 
2904 
        CAL1_VALID_WAIT: begin
2905 
          if (!cal1_wait_r)
2906 
            cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;
2907 
        end
2908 
 
2909 
        CAL1_MPR_PAT_DETECT: begin
2910 
          // MPR read leveling for centering DQS in valid window before
2911 
          // OCLKDELAYED calibration begins in order to eliminate read issues
2912 
          if (idel_pat_detect_valid_r == 1'b0) begin
2913 
            cal1_state_r  <= #TCQ CAL1_VALID_WAIT;
2914 
            idel_pat_detect_valid_r <= #TCQ 1'b1;
2915 
          end else if (idel_pat_detect_valid_r && idel_mpr_pat_detect_r) begin
2916 
            cal1_state_r  <= #TCQ CAL1_DETECT_EDGE;
2917 
            idel_dec_cnt  <= #TCQ 'd0;
2918 
          end else if (!idelay_tap_limit_r)
2919 
            cal1_state_r  <= #TCQ CAL1_DQ_IDEL_TAP_INC;
2920 
          else
2921 
            cal1_state_r  <= #TCQ CAL1_RDLVL_ERR;
2922 
        end
2923 
 
2924 
        CAL1_PAT_DETECT: begin
2925 
          // All DQ bits associated with a DQS are pushed to the right one IDELAY
2926 
          // tap at a time until first rising DQS is in the tri-state region
2927 
          // before first rising edge window.
2928 
          // The detect_edge_done_r condition included to support averaging
2929 
          // during IDELAY tap increments
2930 
          if (detect_edge_done_r) begin
2931 
            if (idel_pat_data_match) begin
2932 
              case (idelay_adj)
2933 
                2'b01: begin
2934 
                  cal1_state_r <= CAL1_DQ_IDEL_TAP_INC;
2935 
                  idel_dec_cnt <= #TCQ 1'b0;
2936 
                  idel_adj_inc <= #TCQ 1'b1;
2937 
                end
2938 
                2'b10: begin   //DEC by 1
2939 
                  cal1_state_r  <= #TCQ  CAL1_DQ_IDEL_TAP_DEC ;
2940 
                  idel_dec_cnt  <= #TCQ 1'b1;
2941 
                  idel_adj_inc  <= #TCQ 1'b0;
2942 
                end
2943 
                default: begin
2944 
                  cal1_state_r  <= #TCQ CAL1_DETECT_EDGE;
2945 
                  idel_dec_cnt  <= #TCQ 1'b0;
2946 
                  idel_adj_inc  <= #TCQ 1'b0;
2947 
                end
2948 
              endcase
2949 
            end else if (!idelay_tap_limit_r) begin
2950 
              cal1_state_r  <= #TCQ CAL1_DQ_IDEL_TAP_INC;
2951 
            end else begin
2952 
              cal1_state_r  <= #TCQ CAL1_RDLVL_ERR;
2953 
            end
2954 
          end
2955 
        end
2956 
 
2957 
        // Increment IDELAY tap by 1 for DQ bits in the byte being calibrated
2958 
        // until left edge of valid window detected
2959 
        CAL1_DQ_IDEL_TAP_INC: begin
2960 
          cal1_dq_idel_ce         <= #TCQ 1'b1;
2961 
          cal1_dq_idel_inc        <= #TCQ 1'b1;
2962 
          cal1_state_r            <= #TCQ CAL1_DQ_IDEL_TAP_INC_WAIT;
2963 
          idel_pat_detect_valid_r <= #TCQ 1'b0;
2964 
        end
2965 
 
2966 
        CAL1_DQ_IDEL_TAP_INC_WAIT: begin
2967 
          cal1_dq_idel_ce     <= #TCQ 1'b0;
2968 
          cal1_dq_idel_inc    <= #TCQ 1'b0;
2969 
          if (!cal1_wait_r) begin
2970 
              idel_adj_inc        <= #TCQ 1'b0;
2971 
            if (idel_adj_inc)
2972 
              cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
2973 
            else  if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))
2974 
              cal1_state_r <= #TCQ CAL1_MPR_PAT_DETECT;
2975 
            else
2976 
              cal1_state_r <= #TCQ CAL1_PAT_DETECT;
2977 
          end
2978 
        end
2979 
 
2980 
        // Decrement by 2 IDELAY taps once idel_pat_data_match detected
2981 
        CAL1_DQ_IDEL_TAP_DEC: begin
2982 
          cal1_dq_idel_inc    <= #TCQ 1'b0;
2983 
          cal1_state_r        <= #TCQ CAL1_DQ_IDEL_TAP_DEC_WAIT;
2984 
          if (idel_dec_cnt >= 'd0)
2985 
            cal1_dq_idel_ce     <= #TCQ 1'b1;
2986 
          else
2987 
            cal1_dq_idel_ce     <= #TCQ 1'b0;
2988 
          if (idel_dec_cnt > 'd0)
2989 
            idel_dec_cnt <= #TCQ idel_dec_cnt - 1;
2990 
          else
2991 
            idel_dec_cnt <= #TCQ idel_dec_cnt;
2992 
        end
2993 
 
2994 
        CAL1_DQ_IDEL_TAP_DEC_WAIT: begin
2995 
          cal1_dq_idel_ce     <= #TCQ 1'b0;
2996 
          cal1_dq_idel_inc    <= #TCQ 1'b0;
2997 
          if (!cal1_wait_r) begin
2998 
            if ((idel_dec_cnt > 'd0) || (pi_rdval_cnt > 'd0))
2999 
              cal1_state_r <= #TCQ CAL1_DQ_IDEL_TAP_DEC;
3000 
            else if (mpr_dec_cpt_r)
3001 
              cal1_state_r <= #TCQ CAL1_STORE_FIRST_WAIT;
3002 
            else
3003 
              cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
3004 
          end
3005 
        end
3006 
 
3007 
        // Check for presence of data eye edge. During this state, we
3008 
        // sample the read data multiple times, and look for changes
3009 
        // in the read data, specifically:
3010 
        //   1. A change in the read data compared with the value of
3011 
        //      read data from the previous delay tap. This indicates
3012 
        //      that the most recent tap delay increment has moved us
3013 
        //      into either a new window, or moved/kept us in the
3014 
        //      transition/jitter region between windows. Note that this
3015 
        //      condition only needs to be checked for once, and for
3016 
        //      logistical purposes, we check this soon after entering
3017 
        //      this state (see comment in CAL1_DETECT_EDGE below for
3018 
        //      why this is done)
3019 
        //   2. A change in the read data while we are in this state
3020 
        //      (i.e. in the absence of a tap delay increment). This
3021 
        //      indicates that we're close enough to a window edge that
3022 
        //      jitter will cause the read data to change even in the
3023 
        //      absence of a tap delay change
3024 
        CAL1_DETECT_EDGE: begin
3025 
          // Essentially wait for the first comparision to finish, then
3026 
          // store current data into "old" data register. This store
3027 
          // happens now, rather than later (e.g. when we've have already
3028 
          // left this state) in order to avoid the situation the data that
3029 
          // is stored as "old" data has not been used in an "active
3030 
          // comparison" - i.e. data is stored after the last comparison
3031 
          // of this state. In this case, we can miss an edge if the
3032 
          // following sequence occurs:
3033 
          //   1. Comparison completes in this state - no edge found
3034 
          //   2. "Momentary jitter" occurs which "pushes" the data out the
3035 
          //      equivalent of one delay tap
3036 
          //   3. We store this jittered data as the "old" data
3037 
          //   4. "Jitter" no longer present
3038 
          //   5. We increment the delay tap by one
3039 
          //   6. Now we compare the current with the "old" data - they're
3040 
          //      the same, and no edge is detected
3041 
          // NOTE: Given the large # of comparisons done in this state, it's
3042 
          //  highly unlikely the above sequence will occur in actual H/W
3043 
 
3044 
          // Wait for the first load of read data into the comparison
3045 
          // shift register to finish, then load the current read data
3046 
          // into the "old" data register. This allows us to do one
3047 
          // initial comparision between the current read data, and
3048 
          // stored data corresponding to the previous delay tap
3049 
          idel_pat_detect_valid_r <= #TCQ 1'b0;
3050 
          if (!store_sr_req_pulsed_r) begin
3051 
            // Pulse store_sr_req_r only once in this state
3052 
            store_sr_req_r        <= #TCQ 1'b1;
3053 
            store_sr_req_pulsed_r <= #TCQ 1'b1;
3054 
          end else begin
3055 
            store_sr_req_r        <= #TCQ 1'b0;
3056 
            store_sr_req_pulsed_r <= #TCQ 1'b1;
3057 
          end
3058 
 
3059 
          // Continue to sample read data and look for edges until the
3060 
          // appropriate time interval (shorter for simulation-only,
3061 
          // much, much longer for actual h/w) has elapsed
3062 
          if (detect_edge_done_r) begin
3063 
            if (tap_limit_cpt_r)
3064 
              // Only one edge detected and ran out of taps since only one
3065 
              // bit time worth of taps available for window detection. This
3066 
              // can happen if at tap 0 DQS is in previous window which results
3067 
              // in only left edge being detected. Or at tap 0 DQS is in the
3068 
              // current window resulting in only right edge being detected.
3069 
              // Depending on the frequency this case can also happen if at
3070 
              // tap 0 DQS is in the left noise region resulting in only left
3071 
              // edge being detected.
3072 
              cal1_state_r <= #TCQ CAL1_CALC_IDEL;
3073 
            else if (found_edge_r) begin
3074 
              // Sticky bit - asserted after we encounter an edge, although
3075 
              // the current edge may not be considered the "first edge" this
3076 
              // just means we found at least one edge
3077 
              found_first_edge_r <= #TCQ 1'b1;
3078 
 
3079 
              // Only the right edge of the data valid window is found
3080 
              // Record the inner right edge tap value
3081 
              if (!found_first_edge_r && found_stable_eye_last_r) begin
3082 
                if (tap_cnt_cpt_r == 'd0)
3083 
                  right_edge_taps_r <= #TCQ 'd0;
3084 
                else
3085 
                  right_edge_taps_r <= #TCQ tap_cnt_cpt_r;
3086 
              end
3087 
 
3088 
              // Both edges of data valid window found:
3089 
              // If we've found a second edge after a region of stability
3090 
              // then we must have just passed the second ("right" edge of
3091 
              // the window. Record this second_edge_taps = current tap-1,
3092 
              // because we're one past the actual second edge tap, where
3093 
              // the edge taps represent the extremes of the data valid
3094 
              // window (i.e. smallest & largest taps where data still valid
3095 
              if (found_first_edge_r && found_stable_eye_last_r) begin
3096 
                found_second_edge_r <= #TCQ 1'b1;
3097 
                second_edge_taps_r <= #TCQ tap_cnt_cpt_r - 1;
3098 
                cal1_state_r <= #TCQ CAL1_CALC_IDEL;
3099 
              end else begin
3100 
                // Otherwise, an edge was found (just not the "second" edge)
3101 
                // Assuming DQS is in the correct window at tap 0 of Phaser IN
3102 
                // fine tap. The first edge found is the right edge of the valid
3103 
                // window and is the beginning of the jitter region hence done!
3104 
                first_edge_taps_r <= #TCQ tap_cnt_cpt_r;
3105 
                cal1_state_r <= #TCQ CAL1_IDEL_INC_CPT;
3106 
              end
3107 
            end else
3108 
              // Otherwise, if we haven't found an edge....
3109 
              // If we still have taps left to use, then keep incrementing
3110 
            cal1_state_r  <= #TCQ CAL1_IDEL_INC_CPT;
3111 
          end
3112 
        end
3113 
 
3114 
        // Increment Phaser_IN delay for DQS
3115 
        CAL1_IDEL_INC_CPT: begin
3116 
          cal1_state_r        <= #TCQ CAL1_IDEL_INC_CPT_WAIT;
3117 
          if (~tap_limit_cpt_r) begin
3118 
            cal1_dlyce_cpt_r    <= #TCQ 1'b1;
3119 
            cal1_dlyinc_cpt_r   <= #TCQ 1'b1;
3120 
          end else begin
3121 
            cal1_dlyce_cpt_r    <= #TCQ 1'b0;
3122 
            cal1_dlyinc_cpt_r   <= #TCQ 1'b0;
3123 
          end
3124 
        end
3125 
 
3126 
        // Wait for Phaser_In to settle, before checking again for an edge
3127 
        CAL1_IDEL_INC_CPT_WAIT: begin
3128 
          cal1_dlyce_cpt_r    <= #TCQ 1'b0;
3129 
          cal1_dlyinc_cpt_r   <= #TCQ 1'b0;
3130 
          if (!cal1_wait_r)
3131 
            cal1_state_r <= #TCQ CAL1_DETECT_EDGE;
3132 
        end
3133 
 
3134 
        // Calculate final value of Phaser_IN taps. At this point, one or both
3135 
        // edges of data eye have been found, and/or all taps have been
3136 
        // exhausted looking for the edges
3137 
        // NOTE: We're calculating the amount to decrement by, not the
3138 
        //  absolute setting for DQS.
3139 
        CAL1_CALC_IDEL: begin
3140 
         // CASE1: If 2 edges found.
3141 
          if (found_second_edge_r)
3142 
            cnt_idel_dec_cpt_r
3143 
              <=  #TCQ ((second_edge_taps_r -
3144 
                         first_edge_taps_r)>>1) + 1;
3145 
          else if (right_edge_taps_r > 6'd0)
3146 
            // Only right edge detected
3147 
            // right_edge_taps_r is the inner right edge tap value
3148 
            // hence used for calculation
3149 
            cnt_idel_dec_cpt_r
3150 
              <=  #TCQ (tap_cnt_cpt_r - (right_edge_taps_r>>1));
3151 
          else if (found_first_edge_r)
3152 
            // Only left edge detected
3153 
            cnt_idel_dec_cpt_r
3154 
              <=  #TCQ ((tap_cnt_cpt_r - first_edge_taps_r)>>1);
3155 
          else
3156 
            cnt_idel_dec_cpt_r
3157 
              <=  #TCQ (tap_cnt_cpt_r>>1);
3158 
          // Now use the value we just calculated to decrement CPT taps
3159 
          // to the desired calibration point
3160 
          cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
3161 
        end
3162 
 
3163 
        // decrement capture clock for final adjustment - center
3164 
        // capture clock in middle of data eye. This adjustment will occur
3165 
        // only when both the edges are found usign CPT taps. Must do this
3166 
        // incrementally to avoid clock glitching (since CPT drives clock
3167 
        // divider within each ISERDES)
3168 
        CAL1_IDEL_DEC_CPT: begin
3169 
          cal1_dlyce_cpt_r  <= #TCQ 1'b1;
3170 
          cal1_dlyinc_cpt_r <= #TCQ 1'b0;
3171 
          // once adjustment is complete, we're done with calibration for
3172 
          // this DQS, repeat for next DQS
3173 
          cnt_idel_dec_cpt_r <= #TCQ cnt_idel_dec_cpt_r - 1;
3174 
          if (cnt_idel_dec_cpt_r == 6'b000001) begin
3175 
            if (mpr_dec_cpt_r) begin
3176 
              if (|idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing]) begin
3177 
                idel_dec_cnt  <= #TCQ idelay_tap_cnt_r[rnk_cnt_r][cal1_cnt_cpt_timing];
3178 
                cal1_state_r  <= #TCQ CAL1_DQ_IDEL_TAP_DEC;
3179 
              end else
3180 
                cal1_state_r  <= #TCQ CAL1_STORE_FIRST_WAIT;
3181 
            end else
3182 
              cal1_state_r <= #TCQ CAL1_NEXT_DQS;
3183 
          end else
3184 
            cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT_WAIT;
3185 
        end
3186 
 
3187 
        CAL1_IDEL_DEC_CPT_WAIT: begin
3188 
          cal1_dlyce_cpt_r  <= #TCQ 1'b0;
3189 
          cal1_dlyinc_cpt_r <= #TCQ 1'b0;
3190 
                  if (!cal1_wait_r)
3191 
            cal1_state_r <= #TCQ CAL1_IDEL_DEC_CPT;
3192 
        end
3193 
 
3194 
        // Determine whether we're done, or have more DQS's to calibrate
3195 
        // Also request precharge after every byte, as appropriate
3196 
        CAL1_NEXT_DQS: begin
3197 
          //if (mpr_rdlvl_done_r || (DRAM_TYPE == "DDR2"))
3198 
            cal1_prech_req_r  <= #TCQ 1'b1;
3199 
          //else
3200 
          //  cal1_prech_req_r  <= #TCQ 1'b0;
3201 
          cal1_dlyce_cpt_r  <= #TCQ 1'b0;
3202 
          cal1_dlyinc_cpt_r <= #TCQ 1'b0;
3203 
          // Prepare for another iteration with next DQS group
3204 
          found_first_edge_r  <= #TCQ 1'b0;
3205 
          found_second_edge_r <= #TCQ 1'b0;
3206 
          first_edge_taps_r <= #TCQ 'd0;
3207 
          second_edge_taps_r <= #TCQ 'd0;
3208 
          if ((SIM_CAL_OPTION == "FAST_CAL") ||
3209 
              (cal1_cnt_cpt_r >= DQS_WIDTH-1)) begin
3210 
            if (mpr_rdlvl_done_r) begin
3211 
              rdlvl_last_byte_done <= #TCQ 1'b1;
3212 
              mpr_last_byte_done   <= #TCQ 1'b0;
3213 
            end else begin
3214 
              rdlvl_last_byte_done <= #TCQ 1'b0;
3215 
              mpr_last_byte_done   <= #TCQ 1'b1;
3216 
            end
3217 
          end
3218 
 
3219 
          // Wait until precharge that occurs in between calibration of
3220 
          // DQS groups is finished
3221 
          if (prech_done) begin // || (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))) begin
3222 
            if (SIM_CAL_OPTION == "FAST_CAL") begin
3223 
              //rdlvl_rank_done_r <= #TCQ 1'b1;
3224 
              rdlvl_last_byte_done <= #TCQ 1'b0;
3225 
              mpr_last_byte_done   <= #TCQ 1'b0;
3226 
              cal1_state_r <= #TCQ CAL1_DONE; //CAL1_REGL_LOAD;
3227 
            end else if (cal1_cnt_cpt_r >= DQS_WIDTH-1) begin
3228 
              if (~mpr_rdlvl_done_r) begin
3229 
                mpr_rank_done_r <= #TCQ 1'b1;
3230 
                // if (rnk_cnt_r == RANKS-1) begin
3231 
                  // All DQS groups in all ranks done
3232 
                cal1_state_r <= #TCQ CAL1_DONE;
3233 
                cal1_cnt_cpt_r <= #TCQ 'b0;
3234 
                // end else begin
3235 
                  // // Process DQS groups in next rank
3236 
                  // rnk_cnt_r      <= #TCQ rnk_cnt_r + 1;
3237 
                  // new_cnt_cpt_r  <= #TCQ 1'b1;
3238 
                  // cal1_cnt_cpt_r <= #TCQ 'b0;
3239 
                  // cal1_state_r   <= #TCQ CAL1_IDLE;
3240 
                // end
3241 
              end else begin
3242 
                // All DQS groups in a rank done
3243 
                rdlvl_rank_done_r <= #TCQ 1'b1;
3244 
                if (rnk_cnt_r == RANKS-1) begin
3245 
                  // All DQS groups in all ranks done
3246 
                  cal1_state_r <= #TCQ CAL1_REGL_LOAD;
3247 
                end else begin
3248 
                  // Process DQS groups in next rank
3249 
                  rnk_cnt_r      <= #TCQ rnk_cnt_r + 1;
3250 
                  new_cnt_cpt_r  <= #TCQ 1'b1;
3251 
                  cal1_cnt_cpt_r <= #TCQ 'b0;
3252 
                  cal1_state_r   <= #TCQ CAL1_IDLE;
3253 
                end
3254 
              end
3255 
            end else begin
3256 
              // Process next DQS group
3257 
              new_cnt_cpt_r  <= #TCQ 1'b1;
3258 
              cal1_cnt_cpt_r <= #TCQ cal1_cnt_cpt_r + 1;
3259 
              cal1_state_r   <= #TCQ CAL1_NEW_DQS_PREWAIT;
3260 
            end
3261 
          end
3262 
        end
3263 
 
3264 
        CAL1_NEW_DQS_PREWAIT: begin
3265 
          if (!cal1_wait_r) begin
3266 
              if (~mpr_rdlvl_done_r & (DRAM_TYPE == "DDR3"))
3267 
                  cal1_state_r  <= #TCQ CAL1_MPR_NEW_DQS_WAIT;
3268 
                else
3269 
                cal1_state_r   <= #TCQ CAL1_NEW_DQS_WAIT;
3270 
          end
3271 
        end
3272 
 
3273 
        // Load rank registers in Phaser_IN
3274 
        CAL1_REGL_LOAD: begin
3275 
          rdlvl_rank_done_r <= #TCQ 1'b0;
3276 
          mpr_rank_done_r   <= #TCQ 1'b0;
3277 
          cal1_prech_req_r  <= #TCQ 1'b0;
3278 
          cal1_cnt_cpt_r    <= #TCQ 'b0;
3279 
          rnk_cnt_r         <= #TCQ 2'b00;
3280 
          if ((regl_rank_cnt == RANKS-1) &&
3281 
              ((regl_dqs_cnt == DQS_WIDTH-1) && (done_cnt == 4'd1))) begin
3282 
            cal1_state_r <= #TCQ CAL1_DONE;
3283 
            rdlvl_last_byte_done <= #TCQ 1'b0;
3284 
            mpr_last_byte_done   <= #TCQ 1'b0;
3285 
          end else
3286 
            cal1_state_r <= #TCQ CAL1_REGL_LOAD;
3287 
        end
3288 
 
3289 
        CAL1_RDLVL_ERR: begin
3290 
          rdlvl_stg1_err <= #TCQ 1'b1;
3291 
        end
3292 
 
3293 
        // Done with this stage of calibration
3294 
        // if used, allow DEBUG_PORT to control taps
3295 
        CAL1_DONE: begin
3296 
          mpr_rdlvl_done_r  <= #TCQ 1'b1;
3297 
          cal1_prech_req_r  <= #TCQ 1'b0;
3298 
          if (~mpr_rdlvl_done_r && (OCAL_EN=="ON") && (DRAM_TYPE == "DDR3")) begin
3299 
            rdlvl_stg1_done   <= #TCQ 1'b0;
3300 
            cal1_state_r <= #TCQ CAL1_IDLE;
3301 
          end else
3302 
            rdlvl_stg1_done   <= #TCQ 1'b1;
3303 
        end
3304 
 
3305 
      endcase
3306 
    end
3307 
// verilint STARC-2.2.3.3 on
3308 
 
3309 
 
3310 
 
3311 
 
3312 
endmodule

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