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//*****************************************************************************

//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version:

//  \   \         Application: MIG

//  /   /         Filename: ddr_phy_wrcal.v

// /___/   /\     Date Last Modified: $Date: 2011/06/02 08:35:09 $

// \   \  /  \    Date Created:

//  \___\/\___\

//

//Device: 7 Series

//Design Name: DDR3 SDRAM

//Purpose:

//  Write calibration logic to align DQS to correct CK edge

//Reference:

//Revision History:

//*****************************************************************************

/******************************************************************************

**$Id: ddr_phy_wrcal.v,v 1.1 2011/06/02 08:35:09 mishra Exp $

**$Date: 2011/06/02 08:35:09 $

**$Author:

**$Revision:

**$Source:

******************************************************************************/

`timescale 1ps/1ps

module mig_7series_v2_3_ddr_phy_wrcal #

  (

   parameter TCQ             = 100,    // clk->out delay (sim only)

   parameter nCK_PER_CLK     = 2,      // # of memory clocks per CLK

   parameter CLK_PERIOD      = 2500,

   parameter DQ_WIDTH        = 64,     // # of DQ (data)

   parameter DQS_CNT_WIDTH   = 3,      // = ceil(log2(DQS_WIDTH))

   parameter DQS_WIDTH       = 8,      // # of DQS (strobe)

   parameter DRAM_WIDTH      = 8,      // # of DQ per DQS

   parameter PRE_REV3ES      = "OFF",  // Delay O/Ps using Phaser_Out fine dly

   parameter SIM_CAL_OPTION  = "NONE"  // Skip various calibration steps

   )

  (

   input                        clk,

   input                        rst,

   // Calibration status, control signals

   input                        wrcal_start,

   input                        wrcal_rd_wait,

   input                        wrcal_sanity_chk,

   input                        dqsfound_retry_done,

   input                        phy_rddata_en,

   output                       dqsfound_retry,

   output                       wrcal_read_req,

   output reg                   wrcal_act_req,

   output reg                   wrcal_done,

   output reg                   wrcal_pat_err,

   output reg                   wrcal_prech_req,

   output reg                   temp_wrcal_done,

   output reg                   wrcal_sanity_chk_done,

   input                        prech_done,

   // Captured data in resync clock domain

   input [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,

   // Write level values of Phaser_Out coarse and fine

   // delay taps required to load Phaser_Out register

   input [3*DQS_WIDTH-1:0]      wl_po_coarse_cnt,

   input [6*DQS_WIDTH-1:0]      wl_po_fine_cnt,

   input                        wrlvl_byte_done,

   output reg                   wrlvl_byte_redo,

   output reg                   early1_data,

   output reg                   early2_data,

   // DQ IDELAY

   output reg                   idelay_ld,

   output reg                   wrcal_pat_resume,   // to phy_init for write

   output reg [DQS_CNT_WIDTH:0] po_stg2_wrcal_cnt,

   output                       phy_if_reset,

   // Debug Port

   output [6*DQS_WIDTH-1:0]     dbg_final_po_fine_tap_cnt,

   output [3*DQS_WIDTH-1:0]     dbg_final_po_coarse_tap_cnt,

   output [99:0]                dbg_phy_wrcal

   );

  // Length of calibration sequence (in # of words)

  //localparam CAL_PAT_LEN = 8;

  // Read data shift register length

  localparam RD_SHIFT_LEN = 1; //(nCK_PER_CLK == 4) ? 1 : 2;

  // # of reads for reliable read capture

  localparam NUM_READS = 2;

  // # of cycles to wait after changing RDEN count value

  localparam RDEN_WAIT_CNT = 12;

  localparam  COARSE_CNT = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 3 : 6;

  localparam  FINE_CNT   = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 22 : 44;

  localparam CAL2_IDLE            = 4'h0;

  localparam CAL2_READ_WAIT       = 4'h1;

  localparam CAL2_NEXT_DQS        = 4'h2;

  localparam CAL2_WRLVL_WAIT      = 4'h3;

  localparam CAL2_IFIFO_RESET     = 4'h4;

  localparam CAL2_DQ_IDEL_DEC     = 4'h5;

  localparam CAL2_DONE            = 4'h6;

  localparam CAL2_SANITY_WAIT     = 4'h7;

  localparam CAL2_ERR             = 4'h8;

  integer                 i,j,k,l,m,p,q,d;

  reg [2:0]               po_coarse_tap_cnt [0:DQS_WIDTH-1];

  reg [3*DQS_WIDTH-1:0]   po_coarse_tap_cnt_w;

  reg [5:0]               po_fine_tap_cnt [0:DQS_WIDTH-1];

  reg [6*DQS_WIDTH-1:0]   po_fine_tap_cnt_w;

 reg [DQS_CNT_WIDTH:0] wrcal_dqs_cnt_r/* synthesis syn_maxfan = 10 */;

  reg [4:0]               not_empty_wait_cnt;

  reg [3:0]               tap_inc_wait_cnt;

  reg                     cal2_done_r;

  reg                     cal2_done_r1;

  reg                     cal2_prech_req_r;

  reg [3:0]               cal2_state_r;

  reg [3:0]               cal2_state_r1;

  reg [2:0]               wl_po_coarse_cnt_w [0:DQS_WIDTH-1];

  reg [5:0]               wl_po_fine_cnt_w [0:DQS_WIDTH-1];

  reg                     cal2_if_reset;

  reg                     wrcal_pat_resume_r;

  reg                     wrcal_pat_resume_r1;

  reg                     wrcal_pat_resume_r2;

  reg                     wrcal_pat_resume_r3;

  reg [DRAM_WIDTH-1:0]    mux_rd_fall0_r;

  reg [DRAM_WIDTH-1:0]    mux_rd_fall1_r;

  reg [DRAM_WIDTH-1:0]    mux_rd_rise0_r;

  reg [DRAM_WIDTH-1:0]    mux_rd_rise1_r;

  reg [DRAM_WIDTH-1:0]    mux_rd_fall2_r;

  reg [DRAM_WIDTH-1:0]    mux_rd_fall3_r;

  reg [DRAM_WIDTH-1:0]    mux_rd_rise2_r;

  reg [DRAM_WIDTH-1:0]    mux_rd_rise3_r;

  reg                     pat_data_match_r;

  reg                     pat1_data_match_r;

  reg                     pat1_data_match_r1;

  reg                     pat2_data_match_r;

  reg                     pat_data_match_valid_r;

  wire [RD_SHIFT_LEN-1:0] pat_fall0 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat_fall1 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat_fall2 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat_fall3 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat1_fall0 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat1_fall1 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat2_fall0 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat2_fall1 [3:0];

  wire [RD_SHIFT_LEN-1:0] early_fall0 [3:0];

  wire [RD_SHIFT_LEN-1:0] early_fall1 [3:0];

  wire [RD_SHIFT_LEN-1:0] early_fall2 [3:0];

  wire [RD_SHIFT_LEN-1:0] early_fall3 [3:0];

  wire [RD_SHIFT_LEN-1:0] early1_fall0 [3:0];

  wire [RD_SHIFT_LEN-1:0] early1_fall1 [3:0];

  wire [RD_SHIFT_LEN-1:0] early2_fall0 [3:0];

  wire [RD_SHIFT_LEN-1:0] early2_fall1 [3:0];

  reg [DRAM_WIDTH-1:0]    pat_match_fall0_r;

  reg                     pat_match_fall0_and_r;

  reg [DRAM_WIDTH-1:0]    pat_match_fall1_r;

  reg                     pat_match_fall1_and_r;

  reg [DRAM_WIDTH-1:0]    pat_match_fall2_r;

  reg                     pat_match_fall2_and_r;

  reg [DRAM_WIDTH-1:0]    pat_match_fall3_r;

  reg                     pat_match_fall3_and_r;

  reg [DRAM_WIDTH-1:0]    pat_match_rise0_r;

  reg                     pat_match_rise0_and_r;

  reg [DRAM_WIDTH-1:0]    pat_match_rise1_r;

  reg                     pat_match_rise1_and_r;

  reg [DRAM_WIDTH-1:0]    pat_match_rise2_r;

  reg                     pat_match_rise2_and_r;

  reg [DRAM_WIDTH-1:0]    pat_match_rise3_r;

  reg                     pat_match_rise3_and_r;

  reg [DRAM_WIDTH-1:0]    pat1_match_rise0_r;

  reg [DRAM_WIDTH-1:0]    pat1_match_rise1_r;

  reg [DRAM_WIDTH-1:0]    pat1_match_fall0_r;

  reg [DRAM_WIDTH-1:0]    pat1_match_fall1_r;

  reg [DRAM_WIDTH-1:0]    pat2_match_rise0_r;

  reg [DRAM_WIDTH-1:0]    pat2_match_rise1_r;

  reg [DRAM_WIDTH-1:0]    pat2_match_fall0_r;

  reg [DRAM_WIDTH-1:0]    pat2_match_fall1_r;

  reg                     pat1_match_rise0_and_r;

  reg                     pat1_match_rise1_and_r;

  reg                     pat1_match_fall0_and_r;

  reg                     pat1_match_fall1_and_r;

  reg                     pat2_match_rise0_and_r;

  reg                     pat2_match_rise1_and_r;

  reg                     pat2_match_fall0_and_r;

  reg                     pat2_match_fall1_and_r;

  reg                     early1_data_match_r;

  reg                     early1_data_match_r1;

  reg [DRAM_WIDTH-1:0]    early1_match_fall0_r;

  reg                     early1_match_fall0_and_r;

  reg [DRAM_WIDTH-1:0]    early1_match_fall1_r;

  reg                     early1_match_fall1_and_r;

  reg [DRAM_WIDTH-1:0]    early1_match_fall2_r;

  reg                     early1_match_fall2_and_r;

  reg [DRAM_WIDTH-1:0]    early1_match_fall3_r;

  reg                     early1_match_fall3_and_r;

  reg [DRAM_WIDTH-1:0]    early1_match_rise0_r;

  reg                     early1_match_rise0_and_r;

  reg [DRAM_WIDTH-1:0]    early1_match_rise1_r;

  reg                     early1_match_rise1_and_r;

  reg [DRAM_WIDTH-1:0]    early1_match_rise2_r;

  reg                     early1_match_rise2_and_r;

  reg [DRAM_WIDTH-1:0]    early1_match_rise3_r;

  reg                     early1_match_rise3_and_r;

  reg                     early2_data_match_r;

  reg [DRAM_WIDTH-1:0]    early2_match_fall0_r;

  reg                     early2_match_fall0_and_r;

  reg [DRAM_WIDTH-1:0]    early2_match_fall1_r;

  reg                     early2_match_fall1_and_r;

  reg [DRAM_WIDTH-1:0]    early2_match_fall2_r;

  reg                     early2_match_fall2_and_r;

  reg [DRAM_WIDTH-1:0]    early2_match_fall3_r;

  reg                     early2_match_fall3_and_r;

  reg [DRAM_WIDTH-1:0]    early2_match_rise0_r;

  reg                     early2_match_rise0_and_r;

  reg [DRAM_WIDTH-1:0]    early2_match_rise1_r;

  reg                     early2_match_rise1_and_r;

  reg [DRAM_WIDTH-1:0]    early2_match_rise2_r;

  reg                     early2_match_rise2_and_r;

  reg [DRAM_WIDTH-1:0]    early2_match_rise3_r;

  reg                     early2_match_rise3_and_r;

  wire [RD_SHIFT_LEN-1:0] pat_rise0 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat_rise1 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat_rise2 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat_rise3 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat1_rise0 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat1_rise1 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat2_rise0 [3:0];

  wire [RD_SHIFT_LEN-1:0] pat2_rise1 [3:0];

  wire [RD_SHIFT_LEN-1:0] early_rise0 [3:0];

  wire [RD_SHIFT_LEN-1:0] early_rise1 [3:0];

  wire [RD_SHIFT_LEN-1:0] early_rise2 [3:0];

  wire [RD_SHIFT_LEN-1:0] early_rise3 [3:0];

  wire [RD_SHIFT_LEN-1:0] early1_rise0 [3:0];

  wire [RD_SHIFT_LEN-1:0] early1_rise1 [3:0];

  wire [RD_SHIFT_LEN-1:0] early2_rise0 [3:0];

  wire [RD_SHIFT_LEN-1:0] early2_rise1 [3:0];

  wire [DQ_WIDTH-1:0]     rd_data_rise0;

  wire [DQ_WIDTH-1:0]     rd_data_fall0;

  wire [DQ_WIDTH-1:0]     rd_data_rise1;

  wire [DQ_WIDTH-1:0]     rd_data_fall1;

  wire [DQ_WIDTH-1:0]     rd_data_rise2;

  wire [DQ_WIDTH-1:0]     rd_data_fall2;

  wire [DQ_WIDTH-1:0]     rd_data_rise3;

  wire [DQ_WIDTH-1:0]     rd_data_fall3;

  reg [DQS_CNT_WIDTH:0]   rd_mux_sel_r;

  reg                     rd_active_posedge_r;

  reg                     rd_active_r;

  reg                     rd_active_r1;

  reg                     rd_active_r2;

  reg                     rd_active_r3;

  reg                     rd_active_r4;

  reg                     rd_active_r5;

  reg [RD_SHIFT_LEN-1:0]  sr_fall0_r [DRAM_WIDTH-1:0];

  reg [RD_SHIFT_LEN-1:0]  sr_fall1_r [DRAM_WIDTH-1:0];

  reg [RD_SHIFT_LEN-1:0]  sr_rise0_r [DRAM_WIDTH-1:0];

  reg [RD_SHIFT_LEN-1:0]  sr_rise1_r [DRAM_WIDTH-1:0];

  reg [RD_SHIFT_LEN-1:0]  sr_fall2_r [DRAM_WIDTH-1:0];

  reg [RD_SHIFT_LEN-1:0]  sr_fall3_r [DRAM_WIDTH-1:0];

  reg [RD_SHIFT_LEN-1:0]  sr_rise2_r [DRAM_WIDTH-1:0];

  reg [RD_SHIFT_LEN-1:0]  sr_rise3_r [DRAM_WIDTH-1:0];

  reg                     wrlvl_byte_done_r;

  reg                     idelay_ld_done;

  reg                     pat1_detect;

  reg                     early1_detect;

  reg                     wrcal_sanity_chk_r;

  reg                     wrcal_sanity_chk_err;

  //***************************************************************************

  // Debug

  //***************************************************************************

  always @(*) begin

    for (d = 0; d < DQS_WIDTH; d = d + 1) begin

      po_fine_tap_cnt_w[(6*d)+:6]   = po_fine_tap_cnt[d];

      po_coarse_tap_cnt_w[(3*d)+:3] = po_coarse_tap_cnt[d];

    end

  end

  assign dbg_final_po_fine_tap_cnt   = po_fine_tap_cnt_w;

  assign dbg_final_po_coarse_tap_cnt = po_coarse_tap_cnt_w;

  assign dbg_phy_wrcal[0]    = pat_data_match_r;

  assign dbg_phy_wrcal[4:1]  = cal2_state_r1[3:0];

  assign dbg_phy_wrcal[5]    = wrcal_sanity_chk_err;

  assign dbg_phy_wrcal[6]    = wrcal_start;

  assign dbg_phy_wrcal[7]    = wrcal_done;

  assign dbg_phy_wrcal[8]    = pat_data_match_valid_r;

  assign dbg_phy_wrcal[13+:DQS_CNT_WIDTH]= wrcal_dqs_cnt_r;

  assign dbg_phy_wrcal[17+:5]  = not_empty_wait_cnt;

  assign dbg_phy_wrcal[22]     = early1_data;

  assign dbg_phy_wrcal[23]     = early2_data;

  assign dbg_phy_wrcal[24+:8]     = mux_rd_rise0_r;

  assign dbg_phy_wrcal[32+:8]     = mux_rd_fall0_r;

  assign dbg_phy_wrcal[40+:8]     = mux_rd_rise1_r;

  assign dbg_phy_wrcal[48+:8]     = mux_rd_fall1_r;

  assign dbg_phy_wrcal[56+:8]     = mux_rd_rise2_r;

  assign dbg_phy_wrcal[64+:8]     = mux_rd_fall2_r;

  assign dbg_phy_wrcal[72+:8]     = mux_rd_rise3_r;

  assign dbg_phy_wrcal[80+:8]     = mux_rd_fall3_r;

  assign dbg_phy_wrcal[88]     = early1_data_match_r;

  assign dbg_phy_wrcal[89]     = early2_data_match_r;

  assign dbg_phy_wrcal[90]     = wrcal_sanity_chk_r & pat_data_match_valid_r;

  assign dbg_phy_wrcal[91]     = wrcal_sanity_chk_r;

  assign dbg_phy_wrcal[92]     = wrcal_sanity_chk_done;

  assign dqsfound_retry        = 1'b0;

  assign wrcal_read_req        = 1'b0;

  assign phy_if_reset          = cal2_if_reset;

   //**************************************************************************

   // DQS count to hard PHY during write calibration using Phaser_OUT Stage2

   // coarse delay 

   //**************************************************************************

   always @(posedge clk) begin

     po_stg2_wrcal_cnt  <= #TCQ wrcal_dqs_cnt_r;

     wrlvl_byte_done_r  <= #TCQ wrlvl_byte_done;

         wrcal_sanity_chk_r <= #TCQ wrcal_sanity_chk;

   end

  //***************************************************************************

  // Data mux to route appropriate byte to calibration logic - i.e. calibration

  // is done sequentially, one byte (or DQS group) at a time

  //***************************************************************************

  generate

    if (nCK_PER_CLK == 4) begin: gen_rd_data_div4

      assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];

      assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];

      assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];

      assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];

      assign rd_data_rise2 = rd_data[5*DQ_WIDTH-1:4*DQ_WIDTH];

      assign rd_data_fall2 = rd_data[6*DQ_WIDTH-1:5*DQ_WIDTH];

      assign rd_data_rise3 = rd_data[7*DQ_WIDTH-1:6*DQ_WIDTH];

      assign rd_data_fall3 = rd_data[8*DQ_WIDTH-1:7*DQ_WIDTH];

    end else if (nCK_PER_CLK == 2) begin: gen_rd_data_div2

      assign rd_data_rise0 = rd_data[DQ_WIDTH-1:0];

      assign rd_data_fall0 = rd_data[2*DQ_WIDTH-1:DQ_WIDTH];

      assign rd_data_rise1 = rd_data[3*DQ_WIDTH-1:2*DQ_WIDTH];

      assign rd_data_fall1 = rd_data[4*DQ_WIDTH-1:3*DQ_WIDTH];

    end

  endgenerate

  //**************************************************************************

  // Final Phaser OUT coarse and fine delay taps after write calibration

  // Sum of taps used during write leveling taps and write calibration

  //**************************************************************************

  always @(*) begin

    for (m = 0; m < DQS_WIDTH; m = m + 1) begin

      wl_po_coarse_cnt_w[m] = wl_po_coarse_cnt[3*m+:3];

      wl_po_fine_cnt_w[m]   = wl_po_fine_cnt[6*m+:6];

    end

  end

  always @(posedge clk) begin

    if (rst) begin

      for (p = 0; p < DQS_WIDTH; p = p + 1) begin

        po_coarse_tap_cnt[p] <= #TCQ {3{1'b0}};

        po_fine_tap_cnt[p]   <= #TCQ {6{1'b0}};

      end

    end else if (cal2_done_r && ~cal2_done_r1) begin

      for (q = 0; q < DQS_WIDTH; q = q + 1) begin

        po_coarse_tap_cnt[q] <= #TCQ wl_po_coarse_cnt_w[i];

        po_fine_tap_cnt[q]   <= #TCQ wl_po_fine_cnt_w[i];

      end

    end

  end

  always @(posedge clk) begin

    rd_mux_sel_r <= #TCQ wrcal_dqs_cnt_r;

  end

  // Register outputs for improved timing.

  // NOTE: Will need to change when per-bit DQ deskew is supported.

  //       Currenly all bits in DQS group are checked in aggregate

  generate

    genvar mux_i;

    if (nCK_PER_CLK == 4) begin: gen_mux_rd_div4

      for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd

        always @(posedge clk) begin

          mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_rise2_r[mux_i] <= #TCQ rd_data_rise2[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_fall2_r[mux_i] <= #TCQ rd_data_fall2[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_rise3_r[mux_i] <= #TCQ rd_data_rise3[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_fall3_r[mux_i] <= #TCQ rd_data_fall3[DRAM_WIDTH*rd_mux_sel_r + mux_i];

        end

      end

    end else if (nCK_PER_CLK == 2) begin: gen_mux_rd_div2

      for (mux_i = 0; mux_i < DRAM_WIDTH; mux_i = mux_i + 1) begin: gen_mux_rd

        always @(posedge clk) begin

          mux_rd_rise0_r[mux_i] <= #TCQ rd_data_rise0[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_fall0_r[mux_i] <= #TCQ rd_data_fall0[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_rise1_r[mux_i] <= #TCQ rd_data_rise1[DRAM_WIDTH*rd_mux_sel_r + mux_i];

          mux_rd_fall1_r[mux_i] <= #TCQ rd_data_fall1[DRAM_WIDTH*rd_mux_sel_r + mux_i];

        end

      end

    end

  endgenerate

  //***************************************************************************

  // generate request to PHY_INIT logic to issue precharged. Required when

  // calibration can take a long time (during which there are only constant

  // reads present on this bus). In this case need to issue perioidic

  // precharges to avoid tRAS violation. This signal must meet the following

  // requirements: (1) only transition from 0->1 when prech is first needed,

  // (2) stay at 1 and only transition 1->0 when RDLVL_PRECH_DONE asserted

  //***************************************************************************

  always @(posedge clk)

    if (rst)

      wrcal_prech_req <= #TCQ 1'b0;

    else

      // Combine requests from all stages here

      wrcal_prech_req <= #TCQ cal2_prech_req_r;

  //***************************************************************************

  // Shift register to store last RDDATA_SHIFT_LEN cycles of data from ISERDES

  // NOTE: Written using discrete flops, but SRL can be used if the matching

  //   logic does the comparison sequentially, rather than parallel

  //***************************************************************************

  generate

    genvar rd_i;

    if (nCK_PER_CLK == 4) begin: gen_sr_div4

      for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr

        always @(posedge clk) begin

          sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];

          sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];

          sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];

          sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];

          sr_rise2_r[rd_i] <= #TCQ mux_rd_rise2_r[rd_i];

          sr_fall2_r[rd_i] <= #TCQ mux_rd_fall2_r[rd_i];

          sr_rise3_r[rd_i] <= #TCQ mux_rd_rise3_r[rd_i];

          sr_fall3_r[rd_i] <= #TCQ mux_rd_fall3_r[rd_i];

        end

      end

    end else if (nCK_PER_CLK == 2) begin: gen_sr_div2

      for (rd_i = 0; rd_i < DRAM_WIDTH; rd_i = rd_i + 1) begin: gen_sr

        always @(posedge clk) begin

          sr_rise0_r[rd_i] <= #TCQ mux_rd_rise0_r[rd_i];

          sr_fall0_r[rd_i] <= #TCQ mux_rd_fall0_r[rd_i];

          sr_rise1_r[rd_i] <= #TCQ mux_rd_rise1_r[rd_i];

          sr_fall1_r[rd_i] <= #TCQ mux_rd_fall1_r[rd_i];

        end

      end

    end

  endgenerate

 //***************************************************************************

  // Write calibration:

  // During write leveling DQS is aligned to the nearest CK edge that may not 

  // be the correct CK edge. Write calibration is required to align the DQS to 

  // the correct CK edge that clocks the write command.  

  // The Phaser_Out coarse delay line is adjusted if required to add a memory

  // clock cycle of delay in order to read back the expected pattern.

  //***************************************************************************

  always @(posedge clk) begin

    rd_active_r         <= #TCQ phy_rddata_en;

    rd_active_r1        <= #TCQ rd_active_r;

    rd_active_r2        <= #TCQ rd_active_r1;

    rd_active_r3        <= #TCQ rd_active_r2;

    rd_active_r4        <= #TCQ rd_active_r3;

    rd_active_r5        <= #TCQ rd_active_r4;

  end

  //*****************************************************************

  // Expected data pattern when properly received by read capture

  // logic:

  // Based on pattern of ({rise,fall}) =

  //   0xF, 0x0, 0xA, 0x5, 0x5, 0xA, 0x9, 0x6

  // Each nibble will look like:

  //   bit3: 1, 0, 1, 0, 0, 1, 1, 0

  //   bit2: 1, 0, 0, 1, 1, 0, 0, 1

  //   bit1: 1, 0, 1, 0, 0, 1, 0, 1

  //   bit0: 1, 0, 0, 1, 1, 0, 1, 0

  // Change the hard-coded pattern below accordingly as RD_SHIFT_LEN

  // and the actual training pattern contents change

  //*****************************************************************

  generate

    if (nCK_PER_CLK == 4) begin: gen_pat_div4

    // FF00AA5555AA9966

      assign pat_rise0[3] = 1'b1;

      assign pat_fall0[3] = 1'b0;

      assign pat_rise1[3] = 1'b1;

      assign pat_fall1[3] = 1'b0;

      assign pat_rise2[3] = 1'b0;

      assign pat_fall2[3] = 1'b1;

      assign pat_rise3[3] = 1'b1;

      assign pat_fall3[3] = 1'b0;

      assign pat_rise0[2] = 1'b1;

      assign pat_fall0[2] = 1'b0;

      assign pat_rise1[2] = 1'b0;

      assign pat_fall1[2] = 1'b1;

      assign pat_rise2[2] = 1'b1;

      assign pat_fall2[2] = 1'b0;

      assign pat_rise3[2] = 1'b0;

      assign pat_fall3[2] = 1'b1;

      assign pat_rise0[1] = 1'b1;

      assign pat_fall0[1] = 1'b0;

      assign pat_rise1[1] = 1'b1;

      assign pat_fall1[1] = 1'b0;

      assign pat_rise2[1] = 1'b0;

      assign pat_fall2[1] = 1'b1;

      assign pat_rise3[1] = 1'b0;

      assign pat_fall3[1] = 1'b1;