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//*****************************************************************************

//   ____  ____

//  /   /\/   /

// /___/  \  /    Vendor: Xilinx

// \   \   \/     Version:%version

//  \   \         Application: MIG

//  /   /         Filename: mig_7series_v2_3_poc_pd.v

// /___/   /\     Date Last Modified: $$

// \   \  /  \    Date Created:Tue 15 Jan 2014

//  \___\/\___\

//

//Device: Virtex-7

//Design Name: DDR3 SDRAM

//Purpose: IDDR used as phase detector.  The pos_edge and neg_edge stuff

//         prevents any noise that could happen when the phase shift clock is very

//         nearly aligned to the fabric clock.

//Reference:

//Revision History:

//*****************************************************************************

`timescale 1 ps / 1 ps

module mig_7series_v2_3_poc_pd #

  (parameter POC_USE_METASTABLE_SAMP    = "FALSE",

   parameter SIM_CAL_OPTION             = "NONE",

   parameter TCQ                        = 100)

  (/*AUTOARG*/

  // Outputs

  pd_out,

  // Inputs

  iddr_rst, clk, kclk, mmcm_ps_clk

  );

  input iddr_rst;

  input clk;

  input kclk;

  input mmcm_ps_clk;

  wire q1;

  IDDR #

    (.DDR_CLK_EDGE    ("OPPOSITE_EDGE"),

     .INIT_Q1         (1'b0),

     .INIT_Q2         (1'b0),

     .SRTYPE          ("SYNC"))

  u_phase_detector

    (.Q1              (q1),

     .Q2              (),

     .C               (mmcm_ps_clk),

     .CE              (1'b1),

     .D               (kclk),

     .R               (iddr_rst),

     .S               (1'b0));

  // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle.  FIXME

  reg pos_edge_samp;

  generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes

    always @(posedge clk) pos_edge_samp <= #TCQ q1;

  end else begin : eXes

    reg q1_delayed;

    reg rising_clk_seen;

    always @(posedge mmcm_ps_clk) begin

      rising_clk_seen <= 1'b0;

      q1_delayed <= 1'bx;

    end

    always @(posedge clk) begin

      rising_clk_seen = 1'b1;

      if (rising_clk_seen) q1_delayed <= q1;

    end

    always @(posedge clk) begin

      pos_edge_samp <= q1_delayed;

    end

  end endgenerate

  reg pd_out_r;

  always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp;

  output pd_out;

  assign pd_out = pd_out_r;

endmodule // mic_7series_v2_3_poc_pd