URL
https://opencores.org/ocsvn/usb_fpga_2_14/usb_fpga_2_14/trunk
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
ZTEX |
SET_FLAG MODE BATCH
|
| 2 |
|
|
SET_FLAG STANDALONE_MODE TRUE
|
| 3 |
|
|
SET_PREFERENCE upgrade_mode yes
|
| 4 |
|
|
SET_PREFERENCE ipi_mode no
|
| 5 |
|
|
SET_PREFERENCE devicefamily artix7
|
| 6 |
|
|
SET_PREFERENCE device xc7a35t
|
| 7 |
|
|
SET_PREFERENCE speedgrade -1
|
| 8 |
|
|
SET_PREFERENCE package csg324
|
| 9 |
|
|
SET_PREFERENCE verilogsim true
|
| 10 |
|
|
SET_PREFERENCE vhdlsim false
|
| 11 |
|
|
SET_PREFERENCE designentry Verilog
|
| 12 |
|
|
SET_PREFERENCE outputdirectory /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.14/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
|
| 13 |
|
|
SET_PREFERENCE subworkingdirectory /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.14/memfifo.srcs/sources_1/ip/mig_7series_0/_tmp/
|
| 14 |
|
|
SET_PREFERENCE flowvendor Other
|
| 15 |
|
|
SET_PREFERENCE tool vivado
|
| 16 |
|
|
SET_PREFERENCE compnamestatus 0
|
| 17 |
|
|
SET_PARAMETER component_name mig_7series_0
|
| 18 |
|
|
SET_PARAMETER xml_input_file /drv_s2/usb-fpga/ztex/examples/memfifo/fpga-2.14/memfifo.srcs/sources_1/ip/mig_7series_0/mig_b.prj
|
| 19 |
|
|
SET_PARAMETER data_dir_path /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_2
|
| 20 |
|
|
SET_CORE_NAME Memory Interface Generator (MIG 7 Series)
|
| 21 |
|
|
SET_CORE_VERSION 2.2
|
| 22 |
|
|
SET_CORE_VLNV xilinx.com:ip:mig_7series:2.2
|
| 23 |
|
|
SET_CORE_PATH /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_2
|
| 24 |
|
|
SET_CORE_DATASHEET /drv_s2/xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_2/data/docs/ds176_7series_MIS.pdf
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.